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Preliminary User's Manual
PD784938 Subseries
16-Bit Single-Chip Microcontrollers Hardware
PD784935 PD784936 PD784937 PD784938 PD78F4938
Document No. U13987EJ1V0UM00 (1st edition) Date Published September 1999 N CP(K)
(c)
Printed in Japan
1999
[MEMO]
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Preliminary User's Manual U13987EJ1V0UM00
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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FIP, IEBus, Inter Equipment Bus, and EEPROM are trademarks of NEC Corporation. MS-DOS, Windows, and Windows NT are either trademarks or registered trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. NEWS and NEWS-OS are trademarks of Sony Corporation. Ethernet is a trademark of Xerox Corporation. OSF/Motif is a trademark of Open Software Foundation, Inc. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON.
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Preliminary User's Manual U13987EJ1V0UM00
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed: PD78F4938 The customer must judge the need for license: PD784935, 784936, 784937, 784938 The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
* The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. * Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M5D 98. 12
Preliminary User's Manual U13987EJ1V0UM00
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
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Preliminary User's Manual U13987EJ1V0UM00
INTRODUCTION
Target Readers
This manual is intended for users who understand the functions of the PD784938 Subseries to design application systems.
Purpose
The purpose of this manual is to give users an understanding of the various hardware functions of the PD784938 Subseries.
Organization
The PD784938 Subseries user's manual is divided into two volumes - hardware (this manual) and instruction. Hardware Pin functions Internal block functions Interrupts Other internal peripheral functions Certain operating precautions apply to these products. These precautions are stated at the relevant points in the text of each chapter, and are also summarized at the end of each chapter. Be sure to read them. Instruction CPU functions Addressing Instruction set
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How to Read This Manual
Readers are required to have a general knowledge of electric engineering, logic circuits and microcomputers. * Unless otherwise specified The PD784938 is treated as the representative model. If using the PD784935, 784936, 784937, and 78F4938, take the PD784938 for the PD784935, 784936, 784937, and 78F4938. To understand overall functions of the PD784938 Subseries: Read this manual in the order of the CONTENTS. To learn about differences from the PD784908 Subseries: See 1.8 Main Differences with PD784908 Subseries. If the device operates strangely after debugging: Cautions are summarized at the end of each chapter, so refer to the cautions for the relevant function. To learn the detailed functions of a register whose register name is known: Use APPENDIX C REGISTER INDEX. To learn the details of the instruction functions: Refer to 78K/IV Series User's Manual-Instruction (U10905E) separately available. To learn about the electrical characteristics: Refer to Data Sheets. To learn about application examples of each function: Refer to Application Note separately available.
Conventions Data significance: Note: Caution: Remark: Higher digits on the left and lower digits on the right Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Decimal ...................... x x x x Hexadecimal ............... x x x x H Active low representation: x x x (Overscore over pin or signal name)
Numerical representation: Binary ......................... x x x x B or x x x x
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Preliminary User's Manual U13987EJ1V0UM00
Register Notation
7 EDC B
6 1
5 0
4 x
3 A
2 1
1 0
0 x
Where the bit number is marked with a circle, the bit name is reserved for NEC's assembler and is defined as an sfr variable by the #pragma sfr directive for C compiler. Write Operation 0 or 1 is written. The operation is not affected by either value. 0 must be written 1 must be written A value is written according to the function to be used. A value is read according to the operating status. Read Operation 0 or 1 is read.
Code combinations marked "Setting prohibited" in the register notations in the text must not be written.
Easily confused characters : 0 (Zero), O (Letter O) : 1 (One), l (Lowercase letter L), I (Uppercase letter I) Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device related documents
Document Name Document No. Japanese English U13572E U13573E -- This manual U10095E U10905E -- --
PD784935, 784936, 784937, 784938 Data Sheet PD78F4938 Preliminary Product Information PD784938 Subseries Special Function Register Table PD784938 Subseries User's Manual - Hardware
78K/IV Series Application Note - Software Basics 78K/IV Series User's Manual - Instruction 78K/IV Series Instruction Table 78K/IV Series Instruction Set
U13572J U13573J To be prepared U13987J U10095J U10905J U10594J U10595J
Preliminary User's Manual U13987EJ1V0UM00
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Documents for development tools (User's Manuals)
Document Name Document No. Japanese RA78K4 Assembler Package Operation Language RA78K4 Structured Assembler Preprocessor CC78K4 C Compiler Operation Language IE-78K4-NS IE-784000-R IE-784937-NS-EM1 IE-784937-R-EM1 EP-78064 SM78K4 System Simulator Windows SM78K Series System Simulator
TM
English U11334E U11162E U11743E U11517E U11518E U13356E EEU-1534 To be prepared -- EEU-1469 U10093E U10092E
U11334J U11162J U11743J U11517J U11518J U13356J U12903J To be prepared To be prepared EEU-934
Based
Reference External component user open interface specification Reference Reference
TM
U10093J U10092J
ID-78K4-NS Integrated Debugger ID78K4 Integrated Debugger Windows Based ID78K4 Integrated Debugger HP-UX , SunOS , NEWS-OSTM Based
TM
U12796J U10440J U11960J
U12796E U10440E U11960E
Reference
Documents for embedded software (User's Manuals)
Document Name Document No. Japanese 78K/IV Series Real-Time OS Fundamental Installation Debugger 78K/IV Series OS MX78K4 Basics U10603J U10604J U10364J U11779J English U10603E U10604E -- --
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
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Preliminary User's Manual U13987EJ1V0UM00
Other documents
Document Name Document No. Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Device NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcomputer-Related Products by Third Party X13769X C10535J C11531J C10983J C11892J U11416J C10535E C11531E C10983E C11892E -- English
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Preliminary User's Manual U13987EJ1V0UM00
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Preliminary User's Manual U13987EJ1V0UM00
CONTENTS
CHAPTER 1 GENERAL ........................................................................................................................... 1.1 Features .................................................................................................................................... 1.2 Ordering Information ............................................................................................................... 1.3 Pin Configuration (Top View) .................................................................................................
1.3.1 Normal operation mode ...............................................................................................................
39 41 42 43
43
1.4 1.5 1.6 1.7 1.8
Application System Configuration Example (Car Audio (Tuner, Deck)) .......................... Block Diagram .......................................................................................................................... List of Functions ...................................................................................................................... Differences among Products in PD784938 Subseries ..................................................... Main Differences with PD784908 Subseries ......................................................................
45 46 47 50 50 51 51
51
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 2.1 Pin Function Lists ....................................................................................................................
2.1.1 Normal operation mode ............................................................................................................... Normal operation mode ...............................................................................................................
2.2 2.3 2.4
Pin Functions ...........................................................................................................................
2.2.1
55
55
Input/Output Circuits and Connection of Unused Pins ..................................................... Cautions ....................................................................................................................................
62 65 67 67 73 74
75 76 76
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 3.1 Memory Space .......................................................................................................................... 3.2 Internal ROM Area .................................................................................................................... 3.3 Base Area ..................................................................................................................................
3.3.1 3.3.2 3.3.3 Vector table area .......................................................................................................................... CALLT instruction table area ....................................................................................................... CALLF instruction entry area ...................................................................................................... Internal RAM area ........................................................................................................................ Special function register (SFR) area ........................................................................................... External SFR area .......................................................................................................................
3.4
Internal Data Area ....................................................................................................................
3.4.1 3.4.2 3.4.3
77
78 81 81
3.5 3.6 3.7
External Memory Space .......................................................................................................... PD78F4938 Memory Mapping ............................................................................................... Control Registers .....................................................................................................................
3.7.1 3.7.2 3.7.3 3.7.4 Program counter (PC) .................................................................................................................. Program status word (PSW) ........................................................................................................ Use of RSS bit ............................................................................................................................. Stack pointer (SP) ........................................................................................................................ Configuration ................................................................................................................................ Functions ......................................................................................................................................
81 82 83
83 83 86 88
3.8
General-Purpose Registers ....................................................................................................
3.8.1 3.8.2
92
92 94
3.9 3.10
Special Function Registers (SFR) ......................................................................................... 97 Cautions .................................................................................................................................... 103
CHAPTER 4 CLOCK GENERATOR ...................................................................................................... 105 4.1 Configuration and Function ................................................................................................... 105
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4.2
Control Registers ..................................................................................................................... 107
4.2.1 4.2.2 Standby control register (STBC) ................................................................................................. Oscillation stabilization time specification register (OSTS) ....................................................... Clock oscillator ............................................................................................................................. Divider .......................................................................................................................................... When an external clock is input .................................................................................................. When crystal/ceramic oscillation is used .................................................................................... 107 109
4.3
Clock Generator Operation ....................................................................................................
4.3.1 4.3.2
110
110 110
4.4
Cautions ....................................................................................................................................
4.4.1 4.4.2
111
111 112
CHAPTER 5 REGULATOR ...................................................................................................................... 115 5.1 Outline of Regulator ................................................................................................................ 115 CHAPTER 6 PORT FUNCTIONS ........................................................................................................... 117 6.1 Digital Input/Output Ports ....................................................................................................... 117 6.2 Port 0 ......................................................................................................................................... 119
6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 Hardware configuration ................................................................................................................ I/O mode/control mode setting .................................................................................................... Operating status ........................................................................................................................... On-chip pull-up resistors .............................................................................................................. Transistor drive ............................................................................................................................ Hardware configuration ................................................................................................................ I/O mode/control mode setting .................................................................................................... Operating status ........................................................................................................................... On-chip pull-up resistors .............................................................................................................. Direct LED drive ........................................................................................................................... Hardware configuration ................................................................................................................ Input mode/control mode setting ................................................................................................. Operating status ........................................................................................................................... On-chip pull-up resistors .............................................................................................................. Hardware configuration ................................................................................................................ I/O mode/control mode setting .................................................................................................... Operating status ........................................................................................................................... On-chip pull-up resistors .............................................................................................................. Hardware configuration ................................................................................................................ I/O mode/control mode setting .................................................................................................... Operating status ........................................................................................................................... On-chip pull-up resistors .............................................................................................................. Direct LED drive ........................................................................................................................... Hardware configuration ................................................................................................................ I/O mode/control mode setting .................................................................................................... Operating status ........................................................................................................................... On-chip pull-up resistors .............................................................................................................. 119 120 121 123 125 127 131 132 135 136 139 141 141 141 144 148 150 153 155 156 157 159 161 162 163 164 166
6.3
Port 1 ......................................................................................................................................... 126
6.3.1 6.3.2 6.3.3 6.3.4 6.3.5
6.4
Port 2 ......................................................................................................................................... 137
6.4.1 6.4.2 6.4.3 6.4.4
6.5
Port 3 ......................................................................................................................................... 143
6.5.1 6.5.2 6.5.3 6.5.4
6.6
Port 4 ......................................................................................................................................... 155
6.6.1 6.6.2 6.6.3 6.6.4 6.6.5
6.7
Port 5 ......................................................................................................................................... 162
6.7.1 6.7.2 6.7.3 6.7.4
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6.7.5
Direct LED drive ........................................................................................................................... Hardware configuration ................................................................................................................ I/O mode/control mode setting .................................................................................................... Operating status ........................................................................................................................... On-chip pull-up resistors .............................................................................................................. Hardware configuration ................................................................................................................ I/O mode/control mode setting .................................................................................................... Operating status ........................................................................................................................... On-chip pull-up resistors .............................................................................................................. Caution ......................................................................................................................................... Hardware configuration ................................................................................................................ I/O mode/control mode setting .................................................................................................... Operating status ........................................................................................................................... On-chip pull-up resistors .............................................................................................................. Hardware configuration ................................................................................................................ I/O mode/control mode setting .................................................................................................... Operating status ........................................................................................................................... On-chip pull-up resistors ..............................................................................................................
168 170 174 176 178 179 180 181 182 182 183 184 185 187 189 193 194 197
6.8
Port 6 ......................................................................................................................................... 169
6.8.1 6.8.2 6.8.3 6.8.4
6.9
Port 7 ......................................................................................................................................... 179
6.9.1 6.9.2 6.9.3 6.9.4 6.9.5
6.10
Port 9 ......................................................................................................................................... 183
6.10.1 6.10.2 6.10.3 6.10.4
6.11
Port 10 ....................................................................................................................................... 188
6.11.1 6.11.2 6.11.3 6.11.4
6.12 6.13
Port Output Check Function .................................................................................................. 198 Cautions .................................................................................................................................... 199 201 201 203 204 206 209 211
CHAPTER 7 REAL-TIME OUTPUT FUNCTION .................................................................................. 7.1 Configuration and Function ................................................................................................... 7.2 Real-time Output Port Control Register (RTPC).................................................................. 7.3 Real-time Output Port Accesses ........................................................................................... 7.4 Operation .................................................................................................................................. 7.5 Example of Use ........................................................................................................................ 7.6 Cautions ....................................................................................................................................
CHAPTER 8 OUTLINE OF TIMER ....................................................................................................... 213 CHAPTER 9 TIMER/EVENT COUNTER 0 ........................................................................................... 9.1 Functions .................................................................................................................................. 9.2 Configuration ............................................................................................................................ 9.3 Timer/Event Counter 0 Control Registers......................................................................... 9.4 Timer Counter 0 (TM0) Operation ..........................................................................................
9.4.1 9.4.2 Basic operation ............................................................................................................................ Clear operation .............................................................................................................................
215 215 218 221 226
226 228
9.5 9.6
External Event Counter Function .......................................................................................... 230 Compare Register and Capture Register Operation ........................................................... 233
9.6.1 9.6.2 Compare operations .................................................................................................................... Capture operations ...................................................................................................................... Basic operation ............................................................................................................................ 233 235 238
9.7
Basic Operation of Output Control Circuit .......................................................................... 236
9.7.1
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9.7.2 9.7.3 9.7.4 9.7.5
Toggle output ................................................................................................................................ PWM output .................................................................................................................................. PPG output ................................................................................................................................... Software triggered one-shot pulse output ................................................................................... Operation as interval timer (1) .................................................................................................... Operation as interval timer (2) .................................................................................................... Pulse width measurement operation ........................................................................................... Operation as PWM output ........................................................................................................... Operation as PPG output ............................................................................................................ Example of software triggered one-shot pulse output ...............................................................
238 240 245 251 252 254 256 259 262 265
9.8
Examples of Use ...................................................................................................................... 252
9.8.1 9.8.2 9.8.3 9.8.4 9.8.5 9.8.6
9.9
Cautions .................................................................................................................................... 268 271 271 273 277 280
280 283
CHAPTER 10 TIMER/EVENT COUNTER 1 ......................................................................................... 10.1 Functions .................................................................................................................................. 10.2 Configuration ............................................................................................................................ 10.3 Timer/Event Counter 1 Control Registers ............................................................................ 10.4 Timer Counter 1 (TM1) Operation ..........................................................................................
10.4.1 10.4.2 Basic operation ............................................................................................................................ Clear operation .............................................................................................................................
10.5 10.6
External Event Counter Function .......................................................................................... 285 Compare Register and Capture/Compare Register Operation .......................................... 288
10.6.1 10.6.2 Compare operations .................................................................................................................... Capture operations ...................................................................................................................... Operation as interval timer (1) .................................................................................................... Operation as interval timer (2) .................................................................................................... Pulse width measurement operation ........................................................................................... 288 290 293 296 298
10.7
Examples of Use ...................................................................................................................... 293
10.7.1 10.7.2 10.7.3
10.8
Cautions .................................................................................................................................... 301 305 305 308 312 316
316 319
CHAPTER 11 TIMER/EVENT COUNTER 2 ......................................................................................... 11.1 Functions .................................................................................................................................. 11.2 Configuration ............................................................................................................................ 11.3 Timer/Event Counter 2 Control Registers ............................................................................ 11.4 Timer Counter 2 (TM2) Operation ..........................................................................................
11.4.1 11.4.2 Basic operation ............................................................................................................................ Clear operation .............................................................................................................................
11.5 11.6 11.7
External Event Counter Function .......................................................................................... 321 One-Shot Timer Function ....................................................................................................... 324 Compare Register, Capture/Compare Register, and Capture Register Operation ......... 325
11.7.1 11.7.2 Compare operations .................................................................................................................... Capture operations ...................................................................................................................... Basic operation ............................................................................................................................ Toggle output ................................................................................................................................ PWM output .................................................................................................................................. PPG output ................................................................................................................................... 325 327 332 332 334 340
11.8
Basic Operation of Output Control Circuit .......................................................................... 330
11.8.1 11.8.2 11.8.3 11.8.4
11.9
Examples of Use ...................................................................................................................... 347
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11.9.1 11.9.2 11.9.3 11.9.4 11.9.5 11.9.6 11.9.7
Operation as interval timer (1) .................................................................................................... Operation as interval timer (2) .................................................................................................... Pulse width measurement operation ........................................................................................... Operation as PWM output ........................................................................................................... Operation as PPG output ............................................................................................................ Operation as external event counter ........................................................................................... Operation as one-shot timer ........................................................................................................
347 350 353 356 360 364 366
11.10 Cautions .................................................................................................................................... 369 CHAPTER 12 TIMER 3 ........................................................................................................................... 12.1 Function .................................................................................................................................... 12.2 Configuration ............................................................................................................................ 12.3 Timer 3 Control Registers ...................................................................................................... 12.4 Timer Counter 3 (TM3) Operation ..........................................................................................
12.4.1 12.4.2 Basic operation ............................................................................................................................ Clear operation .............................................................................................................................
373 373 374 376 378
378 380
12.5 12.6 12.7
Compare Register Operation ................................................................................................. 382 Example of Use ........................................................................................................................ 383 Cautions .................................................................................................................................... 385 387 387 388 390
390 390 391 392
CHAPTER 13 WATCHDOG TIMER ....................................................................................................... 13.1 Configuration ............................................................................................................................ 13.2 Watchdog Timer Mode Register (WDM)................................................................................ 13.3 Operation ..................................................................................................................................
13.3.1 13.3.2 Count operation ............................................................................................................................ Interrupt priorities ......................................................................................................................... General cautions on use of watchdog timer ............................................................................... Cautions on PD784938 Subseries watchdog timer ..................................................................
13.4
Cautions .................................................................................................................................... 391
13.4.1 13.4.2
CHAPTER 14 WATCH TIMER ................................................................................................................ 393 CHAPTER 15 PWM OUTPUT UNIT ..................................................................................................... 395 15.1 PWM Output Unit Configuration ............................................................................................ 395 15.2 PWM Output Unit Control Registers ..................................................................................... 397
15.2.1 15.2.2 15.2.3 PWM control register (PWMC) .................................................................................................... PWM prescaler register (PWPR) ................................................................................................ PWM modulo registers (PWM0, PWM1) ..................................................................................... Basic PWM output operation ....................................................................................................... PWM pulse output enabling/disabling ......................................................................................... PWM pulse active level specification .......................................................................................... PWM pulse width rewrite cycle specification .............................................................................. 397 398 398 399 400 400 401
15.3
PWM Output Unit Operation ................................................................................................... 399
15.3.1 15.3.2 15.3.3 15.3.4
15.4
Caution ...................................................................................................................................... 402
CHAPTER 16 A/D CONVERTER ........................................................................................................... 403 16.1 Configuration ............................................................................................................................ 403 16.2 A/D Converter Mode Register (ADM) .................................................................................... 407
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16.3 16.4
A/D Current Cut Select Register (IEAD) ............................................................................... 410 Operation .................................................................................................................................. 411
16.4.1 16.4.2 16.4.3 16.4.4 16.4.5 Basic A/D converter operation ..................................................................................................... Select mode ................................................................................................................................. Scan mode ................................................................................................................................... A/D conversion operation start by software ................................................................................ A/D conversion operation start by hardware .............................................................................. 411 415 416 418 420
16.5 16.6
External Circuit of A/D Converter .......................................................................................... 423 Cautions .................................................................................................................................... 423
CHAPTER 17 OUTLINE OF SERIAL INTERFACE ............................................................................ 425 CHAPTER 18 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O ............................... 427 18.1 Switching between Asynchronous Serial Interface Mode and 3-Wire Serial I/O Mode . 428 18.2 Asynchronous Serial Interface Mode ................................................................................... 429
18.2.1 18.2.2 18.2.3 18.2.4 18.2.5 18.2.6 18.2.7 Configuration in asynchronous serial interface mode ................................................................ Asynchronous serial interface control registers ......................................................................... Data format ................................................................................................................................... Parity types and operations ......................................................................................................... Transmission ................................................................................................................................ Reception ..................................................................................................................................... Receive errors .............................................................................................................................. Configuration in 3-wire serial I/O mode ...................................................................................... Clocked serial interface mode registers (CSIM1, CSIM2) ......................................................... Basic operation timing ................................................................................................................. Operation when transmission only is enabled ............................................................................ Operation when reception only is enabled ................................................................................. Operation when transmission/reception is enabled ................................................................... Corrective action in case of slippage of serial clock and shift operations ................................ Baud rate generator configuration .............................................................................................. Baud rate generator control register (BRGC, BRGC2) .............................................................. Baud rate generator operation .................................................................................................... Baud rate setting in asynchronous serial interface mode .......................................................... 429 432 435 436 437 438 439 440 443 444 446 446 447 447 448 450 452 454
18.3
3-Wire Serial I/O Mode ............................................................................................................ 440
18.3.1 18.3.2 18.3.3 18.3.4 18.3.5 18.3.6 18.3.7
18.4
Baud Rate Generator ............................................................................................................... 448
18.4.1 18.4.2 18.4.3 18.4.4
18.5
Cautions .................................................................................................................................... 456 457 457 458 459
459 462 464 465 465 465
CHAPTER 19 3-WIRE SERIAL I/O MODE ......................................................................................... 19.1 Function .................................................................................................................................... 19.2 Configuration ............................................................................................................................ 19.3 Control Registers .....................................................................................................................
19.3.1 Clocked serial interface mode register (CSIM, CSIM3) ............................................................. Basic operation timing ................................................................................................................. Operation when transmission only is enabled ............................................................................ Operation when reception only is enabled ................................................................................. Operation when transmission/reception is enabled ................................................................... Corrective action in case of slippage of serial clock and shift operations ................................
19.4
3-Wire Serial I/O Mode ............................................................................................................ 461
19.4.1 19.4.2 19.4.3 19.4.4 19.4.5
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CHAPTER 20 IEBus CONTROLLER ..................................................................................................... 467 20.1 IEBus Controller Function ...................................................................................................... 467
20.1.1 20.1.2 20.1.3 20.1.4 20.1.5 20.1.6 20.1.7 20.1.8 Communication protocol of IEBus ............................................................................................... Determination of bus mastership (arbitration) ............................................................................ Communication mode .................................................................................................................. Communication address .............................................................................................................. Broadcasting communication ...................................................................................................... Transmission format of IEBus ..................................................................................................... Transmit data ............................................................................................................................... Bit format ...................................................................................................................................... 467 468 468 468 469 469 477 479
20.2 20.3 20.4
Simple IEBus Controller ......................................................................................................... 480 IEBus Controller Configuration ............................................................................................. 481 Internal Registers of IEBus Controller ................................................................................. 483
20.4.1 20.4.2 Internal register list ...................................................................................................................... Description of internal registers .................................................................................................. Interrupt control block .................................................................................................................. Interrupt source list ...................................................................................................................... Master transmission ..................................................................................................................... Master reception .......................................................................................................................... Slave transmission ....................................................................................................................... Slave reception ............................................................................................................................ Interval of occurrence of interrupt for IEBus control .................................................................. 483 484 500 501 502 504 505 506 507
20.5
Interrupt Operations of IEBus Controller ............................................................................. 500
20.5.1 20.5.2
20.6
Interrupt Generation Timing and Main CPU Processing .................................................... 502
20.6.1 20.6.2 20.6.3 20.6.4 20.6.5
20.7
Cautions when Using IEBus Controller ................................................................................ 510 511 511 513 514
514 515 515
CHAPTER 21 CLOCK OUTPUT FUNCTION ....................................................................................... 21.1 Configuration ............................................................................................................................ 21.2 Clock Output Mode Register (CLOM) ................................................................................... 21.3 Operation ..................................................................................................................................
21.3.1 21.3.2 21.3.3 Clock output ................................................................................................................................. 1-bit output port ............................................................................................................................ Operation in standby mode .........................................................................................................
21.4
Cautions .................................................................................................................................... 515
CHAPTER 22 EDGE DETECTION FUNCTION ................................................................................... 517 22.1 Edge Detection Function Control Registers ........................................................................ 517
22.1.1 22.1.2 External interrupt mode registers (INTM0, INTM1) .................................................................... Sampling clock selection register (SCS0) .................................................................................. 517 520
22.2 22.3 22.4 22.5
Edge Detection for Pins P20, P25, and P26 ......................................................................... P21 Pin Edge Detection .......................................................................................................... Pin Edge Detection for Pins P22 to P24 ............................................................................... Cautions ....................................................................................................................................
521 522 523 524
CHAPTER 23 INTERRUPT FUNCTIONS .............................................................................................. 525 23.1 Interrupt Request Sources ..................................................................................................... 526
23.1.1 23.1.2 Software interrupts ....................................................................................................................... Operand error interrupts .............................................................................................................. 528 528
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23.1.3 23.1.4
Non-maskable interrupts .............................................................................................................. Maskable interrupts ...................................................................................................................... Vectored interrupt service ............................................................................................................ Macro service ............................................................................................................................... Context switching ......................................................................................................................... Interrupt control registers ............................................................................................................ Interrupt mask registers (MK0/MK1) ........................................................................................... In-service priority register (ISPR) ................................................................................................ Interrupt mode control register (IMC) .......................................................................................... Watchdog timer mode register (WDM) ....................................................................................... Program status word (PSW) ........................................................................................................ BRK instruction software interrupt acknowledgment operation ................................................. BRKCS instruction software interrupt (software context switching) acknowledgment operation ..........................................................................................................
528 528 529 529 529 533 538 540 541 542 543 544 544
23.2
Interrupt Service Modes ......................................................................................................... 529
23.2.1 23.2.2 23.2.3
23.3
Interrupt Service Control Registers ...................................................................................... 530
23.3.1 23.3.2 23.3.3 23.3.4 23.3.5 23.3.6
23.4
Software Interrupt Acknowledgment Operations ................................................................ 544
23.4.1 23.4.2
23.5 23.6 23.7
Operand Error Interrupt Acknowledgment Operation ........................................................ 546 Non-Maskable Interrupt Acknowledgment Operation ........................................................ 546 Maskable Interrupt Acknowledgment Operation ................................................................. 550
23.7.1 23.7.2 23.7.3 Vectored interrupt ......................................................................................................................... Context switching ......................................................................................................................... Maskable interrupt priority levels ................................................................................................ Outline of macro service function ................................................................................................ Types of macro service ................................................................................................................ Basic macro service operation .................................................................................................... Operation at end of macro service .............................................................................................. Macro service control registers ................................................................................................... Macro service type A ................................................................................................................... Macro service type B ................................................................................................................... Macro service type C ................................................................................................................... Counter mode ............................................................................................................................... 552 552 554 560 560 563 564 566 569 574 579 592
23.8
Macro Service Function .......................................................................................................... 560
23.8.1 23.8.2 23.8.3 23.8.4 23.8.5 23.8.6 23.8.7 23.8.8 23.8.9
23.9 When Interrupt Requests and Macro Service are Temporarily Held Pending ................ 594 23.10 Instructions whose Execution is Temporarily Suspended by an Interrupt or Macro Service ........................................................................................................................... 596 23.11 Interrupt and Macro Service Operation Timing ................................................................... 596
23.11.1 Interrupt acknowledge processing time ...................................................................................... 23.11.2 Processing time of macro service ............................................................................................... 597 598
23.12 Restoring Interrupt Function to Initial State ........................................................................ 599 23.13 Cautions .................................................................................................................................... 600 CHAPTER 24 LOCAL BUS INTERFACE FUNCTION ........................................................................ 603 24.1 Memory Expansion Function ................................................................................................. 603
24.1.1 24.1.2 24.1.3 Memory expansion mode register (MM) ..................................................................................... Memory map with external memory expansion .......................................................................... Basic operation of local bus interface ......................................................................................... 603 605 614
24.2
Wait Function ........................................................................................................................... 615
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24.2.1 24.2.2 24.2.3
Wait function control registers ..................................................................................................... Address waits ............................................................................................................................... Access waits ................................................................................................................................. Control registers ........................................................................................................................... Operations .................................................................................................................................... Hold mode register (HLDM) ........................................................................................................ Operation ......................................................................................................................................
615 618 621 629 630 634 635
24.3
Pseudo-Static RAM Refresh Function .................................................................................. 628
24.3.1 24.3.2
24.4
Bus Hold Function ................................................................................................................... 634
24.4.1 24.4.2
24.5
Cautions .................................................................................................................................... 636
CHAPTER 25 STANDBY FUNCTION .................................................................................................... 637 25.1 Configuration and Function ................................................................................................... 637 25.2 Control Registers ..................................................................................................................... 639
25.2.1 25.2.2 Standby control register (STBC) ................................................................................................. Oscillation stabilization time specification register (OSTS) ....................................................... HALT mode setting and operating status .................................................................................... HALT mode release ..................................................................................................................... STOP mode setting and operating status ................................................................................... STOP mode release .................................................................................................................... IDLE mode setting and operating status .................................................................................... IDLE mode release ...................................................................................................................... 639 641 642 642 646 647 650 651
25.3
HALT Mode ................................................................................................................................ 642
25.3.1 25.3.2
25.4
STOP Mode ............................................................................................................................... 646
25.4.1 25.4.2
25.5
IDLE Mode ................................................................................................................................. 650
25.5.1 25.5.2
25.6 25.7
Check Items when STOP Mode/IDLE Mode is Used ........................................................... 653 Cautions .................................................................................................................................... 655
CHAPTER 26 RESET FUNCTION ......................................................................................................... 657 26.1 Reset Function ......................................................................................................................... 657 26.2 Caution ...................................................................................................................................... 662 CHAPTER 27 ROM CORRECTION ....................................................................................................... 27.1 ROM Correction Functions ..................................................................................................... 27.2 ROM Correction Configuration .............................................................................................. 27.3 Control Register for ROM Correction ................................................................................... 27.4 Use of ROM Correction ........................................................................................................... 27.5 Conditions for Executing ROM Correction .......................................................................... 663 663 665 667 669 670
CHAPTER 28 PD78F4938 PROGRAMMING ...................................................................................... 671 28.1 Internal Memory Size Switching Register (IMS) .................................................................. 672 28.2 Flash Memory Programming Using Flashpro II and Flashpro III ...................................... 673
28.2.1 28.2.2 28.2.3 Selecting communication mode .................................................................................................. Flash memory programming functions ........................................................................................ Connecting Flashpro II or Flashpro III ........................................................................................ 673 674 675
CHAPTER 29 INSTRUCTION OPERATIONS ....................................................................................... 677 29.1 Conventions ............................................................................................................................. 677
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29.2 29.3
List of Operations .................................................................................................................... 681 Instructions Listed by Type of Addressing .......................................................................... 705 709 712 713 714
714 716
APPENDIX A DEVELOPMENT TOOLS ................................................................................................ A.1 Language Processing Software ............................................................................................. A.2 Flash Memory Programming Tools ....................................................................................... A.3 Debugging Tools ......................................................................................................................
A.3.1 A.3.2 Hardware ...................................................................................................................................... Software .......................................................................................................................................
A.4 A.5
Drawings of Conversion Socket (EV-9200GF-100) and Recommended Board Mounting Pattern .............................................................................. 718 Check Sheet for PD784938 Subseries Development Tools ............................................. 720
APPENDIX B EMBEDDED SOFTWARE ................................................................................................ 723 APPENDIX C REGISTER INDEX ........................................................................................................... 725 C.1 Register Name Index ............................................................................................................... 725 C.2 Register Symbol Index ............................................................................................................ 728
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Figure No. 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 4-1 4-2 4-3 4-4 4-5 4-6 4-7 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 Title Pin Input/Output Circuits ............................................................................................................................. Page 64 69 70 71 72 79 82 83 83 88 89 90 92 93 105 106 108 109 111 112 113 115 117 119 120 121 122 123 124 125 127 128 129 130 131 131 132
PD784935 Memory Map ............................................................................................................................ PD784936 Memory Map ............................................................................................................................ PD784937 Memory Map ............................................................................................................................ PD784938, 78F4938 Memory Map ...........................................................................................................
Internal RAM Memory Map ......................................................................................................................... Internal Memory Size Switching Register (IMS) ......................................................................................... Program Counter (PC) Format .................................................................................................................... Program Status Word (PSW) Format ......................................................................................................... Stack Pointer (SP) Format .......................................................................................................................... Data Saved to Stack Area ........................................................................................................................... Data Restored from Stack Area .................................................................................................................. General-Purpose Register Format .............................................................................................................. General-Purpose Register Addresses ........................................................................................................ Clock Generator Block Diagram .................................................................................................................. Clock Oscillator External Circuitry .............................................................................................................. Standby Control Register (STBC) Format .................................................................................................. Oscillation Stabilization Time Specification Register (OSTS) Format ....................................................... Signal Extraction with External Clock Input ................................................................................................ Cautions on Resonator Connection ............................................................................................................ Incorrect Example of Resonator Connection .............................................................................................. Regulator Peripherals Block Diagram ......................................................................................................... Port Configuration ........................................................................................................................................ Port 0 Block Diagram ................................................................................................................................... Port 0 Mode Register (PM0) Format ........................................................................................................... Port Specified as Output Port ..................................................................................................................... Port Specified as Input Port ........................................................................................................................ Pull-Up Resistor Option Register L (PUOL) Format .................................................................................. Pull-Up Resistor Specification (Port 0) ....................................................................................................... Example of Transistor Drive ........................................................................................................................ P12 (Port 1) Block Diagram ........................................................................................................................ P13 (Port 1) Block Diagram ........................................................................................................................ P14 (Port 1) Block Diagram ........................................................................................................................ Block Diagram of P10, P11, and P15 to P17 (Port 1) ................................................................................ Port 1 Mode Register (PM1) Format ........................................................................................................... Port 1 Mode Control Register (PMC1) Format ........................................................................................... Port Specified as Output Port .....................................................................................................................
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LIST OF FIGURES (2/12)
Figure No. 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 6-36 6-37 6-38 6-39 6-40 6-41 6-42 6-43 6-44 6-45 6-46 6-47 6-48 6-49 6-50 6-51 6-52 6-53 6-54 6-55 6-56 Title Port Specified as Input Port ........................................................................................................................ Control Specification .................................................................................................................................... Pull-Up Resistor Option Register L (PUOL) Format .................................................................................. Pull-Up Resistor Specification (Port 1) ....................................................................................................... Example of Direct LED Drive ...................................................................................................................... Block Diagram of P20 to P24, P26, and P27 (Port 2) ............................................................................... P25 (Port 2) Block Diagram ........................................................................................................................ Port Specified as Input Port ........................................................................................................................ Pull-Up Resistor Option Register L (PUOL) Format .................................................................................. Pull-Up Specification (Port 2) ...................................................................................................................... P30 (Port 3) Block Diagram ........................................................................................................................ Block Diagram of P31 and P34 to P37 (Port 3) ......................................................................................... P32 (Port 3) Block Diagram ........................................................................................................................ P33 (Port 3) Block Diagram ........................................................................................................................ Port 3 Mode Register (PM3) Format ........................................................................................................... Port 3 Mode Control Register (PMC3) Format ........................................................................................... Port Specified as Output Port ..................................................................................................................... Port Specified as Input Port ........................................................................................................................ Control Specification .................................................................................................................................... Pull-Up Resistor Option Register L (PUOL) Format .................................................................................. Pull-Up Specification (Port 3) ...................................................................................................................... Port 4 Block Diagram ................................................................................................................................... Port 4 Mode Register (PM4) Format ........................................................................................................... Port Specified as Output Port ..................................................................................................................... Port Specified as Input Port ........................................................................................................................ Pull-Up Resistor Option Register L (PUOL) Format .................................................................................. Pull-Up Specification (Port 4) ...................................................................................................................... Example of Direct LED Drive ...................................................................................................................... Port 5 Block Diagram ................................................................................................................................... Port 5 Mode Register (PM5) Format ........................................................................................................... Port Specified as Output Port ..................................................................................................................... Port Specified as Input Port ........................................................................................................................ Pull-Up Resistor Option Register L (PUOL) Format .................................................................................. Pull-Up Specification (Port 5) ...................................................................................................................... Example of Direct LED Drive ...................................................................................................................... P60 to P63 (Port 6) Block Diagram ............................................................................................................ P64 and P65 (Port 6) Block Diagram ......................................................................................................... P66 (Port 6) Block Diagram ........................................................................................................................ P67 (Port 6) Block Diagram ........................................................................................................................ Port 6 Mode Register (PM6) Format ........................................................................................................... Port Specified as Output Port ..................................................................................................................... Page 133 134 135 136 136 139 140 141 141 142 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 170 171 172 173 175 176
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Figure No. 6-57 6-58 6-59 6-60 6-61 6-62 6-63 6-64 6-65 6-66 6-67 6-68 6-69 6-70 6-71 6-72 6-73 6-74 6-75 6-76 6-77 6-78 6-79 6-80 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 8-1 9-1 9-2 9-3 9-4 Title Port Specified as Input Port ........................................................................................................................ Pull-Up Resistor Option Register L (PUOL) Format .................................................................................. Pull-Up Specification (Port 6) ...................................................................................................................... Port 7 Block Diagram ................................................................................................................................... Port 7 Mode Register (PM7) Format ........................................................................................................... Port Specified as Output Port ..................................................................................................................... Port Specified as Input Port ........................................................................................................................ Port 9 Block Diagram ................................................................................................................................... Port 9 Mode Register (PM9) Format ........................................................................................................... Port Specified as Output Port ..................................................................................................................... Port Specified as Input Port ........................................................................................................................ Pull-Up Resistor Option Register H (PUOH) Format ................................................................................. Pull-Up Specification (Port 9) ...................................................................................................................... P100 to P104 (Port 10) Block Diagram ...................................................................................................... P105 (Port 10) Block Diagram .................................................................................................................... P106 (Port 10) Block Diagram .................................................................................................................... P107 (Port 10) Block Diagram .................................................................................................................... Port 10 Mode Register (PM10) Format ...................................................................................................... Port 10 Mode Control Register (PMC10) Format ....................................................................................... Port Specified as Output Port ..................................................................................................................... Port Specified as Input Port ........................................................................................................................ Control Specification .................................................................................................................................... Pull-Up Resistor Option Register H (PUOH) Format ................................................................................. Pull-Up Specification (Port 10) .................................................................................................................... Real-Time Output Port Block Diagram ........................................................................................................ Real-Time Output Port Control Register (RTPC) Format .......................................................................... Port 0 Buffer Register (P0H, P0L) Configuration ....................................................................................... Real-Time Output Port Operation Timing ................................................................................................... Real-Time Output Port Operation Timing (2-channel independent control example) ............................... Real-Time Output Port Operation Timing ................................................................................................... Real-Time Output Function Control Register Settings ............................................................................... Real-Time Output Function Setting Procedure ........................................................................................... Interrupt Request Servicing when Real-Time Output Function is Used .................................................... Timer Block Diagram ................................................................................................................................... Timer/Event Counter 0 Block Diagram ....................................................................................................... Timer Control Register 0 (TMC0) Format ................................................................................................... Prescaler Mode Register 0 (PRM0) Format ............................................................................................... Capture/Compare Control Register 0 (CRC0) Format ............................................................................... Page 177 178 178 179 180 181 182 183 184 185 186 187 187 189 190 191 192 193 193 194 195 196 197 197 202 203 204 207 208 209 210 210 211 214 219 221 222 223
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LIST OF FIGURES (4/12)
Figure No. 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 9-34 9-35 9-36 9-37 9-38 9-39 9-40 9-41 9-42 9-43 9-44 Title Timer Output Control Register (TOC) Format ............................................................................................ One-Shot Pulse Output Control Register (OSPC) Format ......................................................................... Basic Operation of Timer Counter 0 (TM0) ................................................................................................ TM0 Clearance by Match with Compare Register (CR01) ........................................................................ Clear Operation when CE0 Bit is Cleared (0) ............................................................................................ Timer/Event Counter 0 External Event Count Timing ................................................................................ Example of the Case where the External Event Counter does Not Distinguish between One Valid Edge Input and No Valid Edge Input ......................................................................................... To Distinguish whether One or No Valid Edge has been Input with External Event Counter .................. Compare Operation ..................................................................................................................................... TM0 Clearance After Match Detection ........................................................................................................ Capture Operation ....................................................................................................................................... Toggle Output Operation ............................................................................................................................. PWM Pulse Output ...................................................................................................................................... Example of PWM Output Using TM0 .......................................................................................................... Example of PWM Output when CR00 = FFFFH ........................................................................................ Example of Compare Register (CR00) Rewrite ......................................................................................... Example of 100% Duty with PWM Output .................................................................................................. When Timer/Event Counter 0 is Stopped During PWM Signal Output ..................................................... Example of PPG Output Using TM0 ........................................................................................................... Example of PPG Output when CR00 = CR01 ............................................................................................ Example of Compare Register (CR00) Rewrite ......................................................................................... Example of 100% Duty with PPG Output ................................................................................................... Example of Extended PPG Output Cycle ................................................................................................... When Timer/Event Counter 0 is Stopped During PPG Signal Output ....................................................... Example of Software Triggered One-Shot Pulse Output ........................................................................... Interval Timer Operation (1) Timing ............................................................................................................ Control Register Settings for Interval Timer Operation (1) ........................................................................ Interval Timer Operation (1) Setting Procedure ......................................................................................... Interval Timer Operation (1) Interrupt Request Servicing .......................................................................... Interval Timer Operation (2) Timing ............................................................................................................ Control Register Settings for Interval Timer Operation (2) ........................................................................ Interval Timer Operation (2) Setting Procedure ......................................................................................... Pulse Width Measurement Timing .............................................................................................................. Control Register Settings for Pulse Width Measurement .......................................................................... Pulse Width Measurement Setting Procedure ........................................................................................... Interrupt Request Servicing that Calculates Pulse Width .......................................................................... Example of Timer/Event Counter 0 PWM Signal Output ........................................................................... Control Register Settings for PWM Output Operation ............................................................................... PWM Output Setting Procedure .................................................................................................................. Changing PWM Output Duty ....................................................................................................................... 231 232 233 234 235 238 240 241 241 242 243 244 245 246 247 248 249 250 251 252 253 253 253 254 255 255 256 257 257 258 259 259 260 261 Page 224 225 227 228 229 230
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Figure No. 9-45 9-46 9-47 9-48 9-49 9-50 9-51 9-52 9-53 9-54 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 Title Example of Timer/Event Counter 0 PPG Signal Output ............................................................................ Control Register Settings for PPG Output Operation ................................................................................ PPG Output Setting Procedure ................................................................................................................... Changing PPG Output Duty ........................................................................................................................ Example of Timer/Event Counter 0 One-Shot Pulse Output ..................................................................... Control Register Settings for One-Shot Pulse Output ............................................................................... One-Shot Pulse Output Setting Procedure ................................................................................................. Operation when Counting is Started ........................................................................................................... Example of the Case where the External Event Counter does Not Distinguish between One Valid Edge Input and No Valid Edge Input ......................................................................................... To Distinguish whether One or No Valid Edge has been Input with External Event Counter .................. Timer/Event Counter 1 Block Diagram ....................................................................................................... Timer Control Register 1 (TMC1) Format ................................................................................................... Prescaler Mode Register 1 (PRM1) Format ............................................................................................... Capture/Compare Control Register 1 (CRC1) Format ............................................................................... Basic Operation in 8-Bit Operation Mode (BW1 = 0) ................................................................................. Basic Operation in 16-Bit Operation Mode (BW1 = 1) ............................................................................... TM1 Clearance by Match with Compare Register (CR10, CR11) ............................................................. TM1 Clearance after Capture Operation .................................................................................................... Clear Operation when CE1 Bit is Cleared (to 0) ........................................................................................ Timer/Event Counter 1 External Event Count Timing ................................................................................ Example of the Case where the External Event Counter does Not Distinguish between One Valid Edge Input and No Valid Edge Input ......................................................................................... To Distinguish whether One or No Valid Edge has been Input with External Event Counter .................. Compare Operation in 8-Bit Operation Mode ............................................................................................. Compare Operation in 16-Bit Operation Mode ........................................................................................... TM1 Clearance after Match Detection ........................................................................................................ Capture Operation in 8-Bit Operation Mode ............................................................................................... Capture Operation in 16-Bit Operation Mode ............................................................................................. TM1 Clearance after Capture Operation .................................................................................................... Interval Timer Operation (1) Timing ............................................................................................................ Control Register Settings for Interval Timer Operation (1) ........................................................................ Interval Timer Operation (1) Setting Procedure ......................................................................................... Interval Timer Operation (1) Interrupt Request Servicing .......................................................................... Interval Timer Operation (2) Timing (when CR11 is used as Compare Register) .................................... Control Register Settings for Interval Timer Operation (2) ........................................................................ Interval Timer Operation (2) Setting Procedure ......................................................................................... Pulse Width Measurement Timing (when CR11 is used as Capture Register) ........................................ Control Register Settings for Pulse Width Measurement .......................................................................... Pulse Width Measurement Setting Procedure ........................................................................................... 286 287 288 289 289 290 291 292 293 294 295 295 296 297 297 298 299 300 269 270 274 277 278 279 281 282 283 283 284 285 Page 262 262 263 264 265 266 267 268
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LIST OF FIGURES (6/12)
Figure No. 10-29 10-30 10-31 10-32 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 11-33 11-34 Title Interrupt Request Servicing that Calculates Pulse Width .......................................................................... Operation when Counting is Started ........................................................................................................... Example of the Case where the External Event Counter does Not Distinguish between One Valid Edge Input and No Valid Edge Input ......................................................................................... To Distinguish whether One or No Valid Edge has been Input with External Event Counter .................. Timer/Event Counter 2 Block Diagram ....................................................................................................... Timer Control Register 1 (TMC1) Format ................................................................................................... Prescaler Mode Register 1 (PRM1) Format ............................................................................................... Capture/Compare Control Register 2 (CRC2) Format ............................................................................... Timer Output Control Register (TOC) Format ............................................................................................ Basic Operation in 8-Bit Operation Mode (BW2 = 0) ................................................................................. Basic Operation in 16-Bit Operation Mode (BW2 = 1) ............................................................................... TM2 Clearance by Match with Compare Register (CR20/CR21) .............................................................. TM2 Clearance after Capture Operation .................................................................................................... Clear Operation when CE2 Bit is Cleared (0) ............................................................................................ Timer/Event Counter 2 External Event Count Timing ................................................................................ Example of the Case where the External Event Counter does Not Distinguish between One Valid Edge Input and No Valid Edge Input ......................................................................................... To Distinguish whether One or No Valid Edge has been Input with External Event Counter .................. One-Shot Timer Operation .......................................................................................................................... Compare Operation in 8-Bit Operation Mode ............................................................................................. Compare Operation in 16-Bit Operation Mode ........................................................................................... TM2 Clearance after Match Detection ........................................................................................................ Capture Operation in 8-Bit Operation Mode ............................................................................................... Capture Operation in 16-Bit Operation Mode ............................................................................................. TM2 Clearance after Capture Operation .................................................................................................... Toggle Output Operation ............................................................................................................................. PWM Pulse Output (BW2 = 0) .................................................................................................................... PWM Pulse Output (BW2 = 1) .................................................................................................................... Example of PWM Output Using TM2W ....................................................................................................... Example of PWM Output when CR20W = FFFFH ..................................................................................... Example of Compare Register (CR20W) Rewrite ...................................................................................... Example of 100% Duty with PWM Output .................................................................................................. When Timer/Event Counter 2 is Stopped During PWM Signal Output ..................................................... Example of PPG Output Using TM2 ........................................................................................................... Example of PPG Output when CR20 = CR21 ............................................................................................ Example of Compare Register Rewrite ...................................................................................................... Example of 100% Duty with PPG Output ................................................................................................... Example of Extended PPG Output Cycle ................................................................................................... When Timer/Event Counter 2 is Stopped During PPG Signal Output ....................................................... 322 323 324 325 326 327 328 329 330 332 335 336 337 337 338 338 339 341 342 343 344 345 346 302 303 309 312 313 314 315 317 318 319 319 320 321 Page 300 301
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Figure No. 11-35 11-36 11-37 11-38 11-39 11-40 11-41 11-42 11-43 11-44 11-45 11-46 11-47 11-48 11-49 11-50 11-51 11-52 11-53 11-54 11-55 11-56 11-57 11-58 11-59 11-60 11-61 11-62 11-63 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 Title Interval Timer Operation (1) Timing ............................................................................................................ Control Register Settings for Interval Timer Operation (1) ........................................................................ Interval Timer Operation (1) Setting Procedure ......................................................................................... Interval Timer Operation (1) Interrupt Request Servicing .......................................................................... Interval Timer Operation (2) Timing ............................................................................................................ Control Register Settings for Interval Timer Operation (2) ........................................................................ Interval Timer Operation (2) Setting Procedure ......................................................................................... Pulse Width Measurement Timing .............................................................................................................. Control Register Settings for Pulse Width Measurement .......................................................................... Pulse Width Measurement Setting Procedure ........................................................................................... Interrupt Request Servicing that Calculates Pulse Width .......................................................................... Example of Timer/Event Counter 2 PWM Signal Output ........................................................................... Control Register Settings for PWM Output Operation ............................................................................... PWM Output Setting Procedure .................................................................................................................. Changing PWM Output Duty ....................................................................................................................... Example of Timer/Event Counter 2 PPG Signal Output ............................................................................ Control Register Settings for PPG Output Operation ................................................................................ PPG Output Setting Procedure ................................................................................................................... Changing PPG Output Duty ........................................................................................................................ External Event Counter Operation (single edge) ....................................................................................... Control Register Settings for External Event Counter Operation .............................................................. External Event Counter Operation Setting Procedure ............................................................................... One-Shot Timer Operation .......................................................................................................................... Control Register Settings for One-Shot Timer Operation .......................................................................... One-Shot Timer Operation Setting Procedure ........................................................................................... One-Shot Timer Operation Start Procedure from Second Time Onward .................................................. Operation when Counting is Started ........................................................................................................... Example of the Case where External Event Counter does Not Distinguish between One Valid Edge Input and No Valid Edge Input ......................................................................................... To Distinguish whether One or No Valid Edge has been Input with External Event Counter .................. Timer 3 Block Diagram ................................................................................................................................ Timer Control Register 0 (TMC0) Format ................................................................................................... Prescaler Mode Register 0 (PRM0) Format ............................................................................................... Basic Operation in 8-Bit Operation Mode (BW3 = 0) ................................................................................. Basic Operation in 16-Bit Operation Mode (BW3 = 1) ............................................................................... TM3 Clearance by Match with Compare Register (CR30) ........................................................................ Clear Operation when CE3 Bit is Cleared (0) ............................................................................................ Compare Operation ..................................................................................................................................... Interval Timer Operation Timing .................................................................................................................. Control Register Settings for Interval Timer Operation .............................................................................. 370 371 374 376 377 378 379 380 381 382 383 384 Page 347 348 349 349 350 351 352 353 354 355 355 356 357 358 359 360 361 362 363 364 365 365 366 367 368 368 369
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Figure No. 12-11 12-12 13-1 13-2 14-1 14-2 15-1 15-2 15-3 15-4 15-5 15-6 15-7 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 17-1 18-1 18-2 18-3 18-4 18-5 Title Interval Timer Operation Setting Procedure ............................................................................................... Operation when Counting is Started ........................................................................................................... Watchdog Timer Block Diagram .................................................................................................................. Watchdog Timer Mode Register (WDM) Format ........................................................................................ Watch Timer Mode Register (WM) Format ................................................................................................. Block Diagram of Watch Timer .................................................................................................................... PWM Output Unit Configuration .................................................................................................................. PWM Control Register (PWMC) Format ..................................................................................................... PWM Prescaler Register (PWPR) Format .................................................................................................. Basic PWM Output Operation ..................................................................................................................... PWM Output Active Level Setting ............................................................................................................... PWM Output Timing Example 1 (PWM pulse width rewrite cycle = 212/fPWMC) .........................................
8
Page 384 385 387 389 393 394 395 397 398 399 400 401 402 404 405 408 410 410 412 413 415 416 417 418 419 421 422 424 425 428 430 433 434 435
PWM Output Timing Example 2 (PWM pulse width rewrite cycle = 2 /fPWMC) .......................................... A/D Converter Block Diagram ..................................................................................................................... Example of Capacitor Connection on A/D Converter Pins ........................................................................ A/D Converter Mode Register (ADM) Format ............................................................................................ A/D Current Cut Select Register (IEAD) Format ........................................................................................ A/D Current Cut Select Register Function .................................................................................................. Basic A/D Converter Operation ................................................................................................................... Relationship between Analog Input Voltage and A/D Conversion Result ................................................. Select Mode Operation Timing .................................................................................................................... Scan Mode 0 Operation Timing ................................................................................................................... Scan Mode 1 Operation Timing ................................................................................................................... Software Start Select Mode A/D Conversion Operation ............................................................................ Software Start Scan Mode A/D Conversion Operation .............................................................................. Hardware Start Select Mode A/D Conversion Operation ........................................................................... Hardware Start Scan Mode A/D Conversion Operation ............................................................................. Example of Capacitor Connection on A/D Converter Pins ........................................................................ Example of Serial Interface ......................................................................................................................... Switching between Asynchronous Serial Interface Mode and 3-Wire Serial I/O Mode ............................ Asynchronous Serial Interface Block Diagram ........................................................................................... Format of Asynchronous Serial Interface Mode Register (ASIM) and Asynchronous Serial Interface Mode Register 2 (ASIM2) ......................................................................... Format of Asynchronous Serial Interface Status Register (ASIS) and Asynchronous Serial Interface Status Register 2 (ASIS2) ........................................................................ Asynchronous Serial Interface Transmit/Receive Data Format .................................................................
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Figure No. 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 18-15 Title Asynchronous Serial Interface Transmission Completion Interrupt Timing .............................................. Asynchronous Serial Interface Reception Completion Interrupt Timing .................................................... Receive Error Timing ................................................................................................................................... Example of 3-Wire Serial I/O System Configuration .................................................................................. 3-Wire Serial I/O Mode Block Diagram ....................................................................................................... Format of Clocked Serial Interface Mode Register 1 (CSIM1) and Clocked Serial Interface Mode Register 2 (CSIM2) ................................................................................... 3-Wire Serial I/O Mode Timing .................................................................................................................... Example of Connection to 2-Wire Serial I/O .............................................................................................. Baud Rate Generator Block Diagram ......................................................................................................... Format of Baud Rate Generator Control Register (BRGC) and Baud Rate Generator Control Register 2 (BRGC2) ................................................................................... 19-1 19-2 19-3 19-4 19-5 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 20-16 20-17 20-18 20-19 20-20 20-21 Clocked Serial Interface Block Diagram ..................................................................................................... Format of Clocked Serial Interface Mode Register (CSIM) and Clocked Serial Interface Mode Register 3 (CSIM3) ................................................................................... Example of 3-Wire Serial I/O System Configuration .................................................................................. 3-Wire Serial I/O Mode Timing .................................................................................................................... Operation when Reception is Disabled ....................................................................................................... IEBus Transmission Signal Format ............................................................................................................. Master Address Field ................................................................................................................................... Slave Address Field ..................................................................................................................................... Control Field ................................................................................................................................................. Telegraph Length Field ................................................................................................................................ Data Field ..................................................................................................................................................... Bit Configuration of Slave Status ................................................................................................................ Configuration of Lock Address .................................................................................................................... Bit Format of IEBus ..................................................................................................................................... IEBus Controller Block Diagram .................................................................................................................. Bus Control Register (BCR) Format ........................................................................................................... Unit Address Register (UAR) Format .......................................................................................................... Slave Address Register (SAR) Format ....................................................................................................... Partner Address Register (PAR) Format ..................................................................................................... Control Data Register (CDR) Format .......................................................................................................... Interrupt Generation Timing (in case of <1>, <3>, <4>) ............................................................................ Interrupt Generation Timing (in case of <2>, <5>) ..................................................................................... INTIE2 Interrupt Generation Timing in Locked Status (in case of <4>, <5>) ........................................... INTIE2 Interrupt Generation Timing in Locked Status (in case of <3>) .................................................... Telegraph Length Register (DLR) Format .................................................................................................. Data Register (DR) Format ......................................................................................................................... 459 461 462 464 469 470 471 473 473 474 477 478 479 481 484 486 486 486 487 488 488 489 489 490 491 451 458 443 444 445 449 Page 437 438 439 440 441
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Figure No. 20-22 20-23 20-24 20-25 20-26 20-27 20-28 21-1 21-2 21-3 21-4 22-1 22-2 22-3 22-4 22-5 22-6 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 23-9 23-10 23-11 23-12 23-13 23-14 23-15 23-16 23-17 23-18 23-19 23-20 23-21 Title Unit Status Register (USR) Format ............................................................................................................ Broadcasting Communication Flag Operation Example ............................................................................ Interrupt Status Register (ISR) Format ....................................................................................................... Slave Status Register (SSR) Format .......................................................................................................... Success Count Register (SCR) Format ...................................................................................................... Communication Count Register (CCR) Format .......................................................................................... Configuration of Interrupt Control Block ..................................................................................................... Clock Output Function Configuration .......................................................................................................... Clock Output Mode Register (CLOM) Format ............................................................................................ Clock Output Operation Timing ................................................................................................................... One-Bit Output Port Operation .................................................................................................................... External Interrupt Mode Register 0 (INTM0) Format ................................................................................. External Interrupt Mode Register 1 (INTM1) Format ................................................................................. Sampling Clock Selection Register (SCS0) Format ................................................................................... Edge Detection for Pins P20, P25, and P26 .............................................................................................. P21 Pin Edge Detection .............................................................................................................................. Edge Detection for Pins P22 to P24 ........................................................................................................... Interrupt Control Registers (xxICn) ............................................................................................................. Interrupt Mask Register (MK0, MK1) Format ............................................................................................. In-Service Priority Register (ISPR) Format ................................................................................................ Interrupt Mode Control Register (IMC) Format .......................................................................................... Watchdog Timer Mode Register (WDM) Format ........................................................................................ Program Status Word (PSWL) Format ....................................................................................................... Context Switching Operation by Execution of a BRKCS Instruction ......................................................... Return from BRKCS Instruction Software Interrupt (RETCSB instruction operation) .............................. Non-Maskable Interrupt Request Acknowledgment Operations ................................................................ Interrupt Acknowledgment Processing Algorithm ....................................................................................... Context Switching Operation by Generation of an Interrupt Request ....................................................... Return from Interrupt that Uses Context Switching by Means of RETCS Instruction .............................. Examples of Servicing when Another Interrupt Request is Generated During Interrupt Service ............ Examples of Servicing of Simultaneously Generated Interrupts ............................................................... Differences in Level 3 Interrupt Acknowledgment According to IMC Register Setting ............................. Differences between Vectored Interrupt and Macro Service Processing .................................................. Macro Service Processing Sequence ......................................................................................................... Operation at End of Macro Service when VCIE = 0 .................................................................................. Operation at End of Macro Service when VCIE = 1 .................................................................................. Macro Service Control Word Format .......................................................................................................... Macro Service Mode Register Format ........................................................................................................ Page 492 493 494 498 499 499 500 511 513 514 515 518 519 520 521 522 523 534 538 540 541 542 543 544 545 547 551 552 553 555 558 559 560 563 564 565 566 567
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Figure No. 23-22 23-23 23-24 23-25 23-26 23-27 23-28 23-29 23-30 23-31 23-32 23-33 23-34 23-35 23-36 23-37 23-38 23-39 23-40 23-41 23-42 24-1 24-2 24-3 24-4 24-5 24-6 24-7 24-8 24-9 24-10 24-11 24-12 24-13 24-14 24-15 Title Macro Service Data Transfer Processing Flow (Type A) ........................................................................... Type A Macro Service Channel ................................................................................................................... Asynchronous Serial Reception .................................................................................................................. Macro Service Data Transfer Processing Flow (Type B) ........................................................................... Type B Macro Service Channel ................................................................................................................... Parallel Data Input Synchronized with External Interrupts ........................................................................ Parallel Data Input Timing ........................................................................................................................... Macro Service Data Transfer Processing Flow (Type C) ........................................................................... Type C Macro Service Channel .................................................................................................................. Stepping Motor Open Loop Control by Real-Time Output Port ................................................................. Data Transfer Control Timing ...................................................................................................................... Single-Phase Excitation of 4-Phase Stepping Motor ................................................................................. 1-2-Phase Excitation of 4-Phase Stepping Motor ...................................................................................... Automatic Addition Control + Ring Control Block Diagram 1 (when output timing varies with 1-2-phase excitation) ............................................................................... Automatic Addition Control + Ring Control Timing Diagram 1 (when output timing varies with 1-2-phase excitation) ............................................................................... Automatic Addition Control + Ring Control Block Diagram 2 (1-2-phase excitation constant-velocity operation) ..................................................................................... Automatic Addition Control + Ring Control Timing Diagram 2 (1-2-phase excitation constant-velocity operation) ..................................................................................... Macro Service Data Transfer Processing Flow (counter mode) ................................................................ Counter Mode .............................................................................................................................................. Counting Number of Edges ......................................................................................................................... Interrupt Request Generation and Acknowledgment (unit: clocks) ........................................................... Memory Expansion Mode Register (MM) Format ...................................................................................... 591 592 593 593 596 604 606 608 610 612 614 614 615 616 618 622 623 625 627 629 590 589 588 Page 570 572 573 575 576 577 578 580 582 584 585 587 587
PD784935 Memory Map ............................................................................................................................ PD784936 Memory Map ............................................................................................................................ PD784937 Memory Map ............................................................................................................................ PD784938 Memory Map ............................................................................................................................
Read Timing ................................................................................................................................................. Write Timing ................................................................................................................................................. Memory Expansion Mode Register (MM) Format ...................................................................................... Programmable Wait Control Register (PWC1/PWC2) Format ................................................................... Address Wait Function Read/Write Timing ................................................................................................. Wait Control Spaces .................................................................................................................................... Access Wait Function Read Timing ............................................................................................................ Access Wait Function Write Timing ............................................................................................................ Timing with External Wait Signal ................................................................................................................. Refresh Mode Register (RFM) Format .......................................................................................................
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Figure No. 24-16 24-17 24-18 24-19 24-20 24-21 25-1 25-2 25-3 25-4 25-5 25-6 25-7 26-1 26-2 26-3 27-1 27-2 27-3 27-4 28-1 28-2 28-3 28-4 A-1 A-2 A-3 Title Refresh Area Specification Register (RFA) Format ................................................................................... Pulse Refresh Operation in Internal Memory Access ................................................................................ Refresh Pulse Output Operation ................................................................................................................. Timing for Return from Self-Refresh Operation .......................................................................................... Hold Mode Register (HLDM) Format .......................................................................................................... Hold Mode Timing ........................................................................................................................................ Standby Mode Transition Diagram .............................................................................................................. Standby Function Block Diagram ................................................................................................................ Standby Control Register (STBC) Format .................................................................................................. Oscillation Stabilization Time Specification Register (OSTS) Format ....................................................... STOP Mode Release by NMI Input ............................................................................................................. STOP Mode Release by INTP4/INTP5 Input ............................................................................................. Example of Address/Data Bus Processing ................................................................................................. Reset Signal Acknowledgment .................................................................................................................... Power-On Reset Operation ......................................................................................................................... Reset Input Timing ....................................................................................................................................... ROM Correction Block Diagram .................................................................................................................. Memory Mapping Example (PD784938) ................................................................................................... ROM Correction Address Register (CORAH, CORAL) Format ................................................................. ROM Correction Control Register (CORC) Format .................................................................................... Internal Memory Size Switching Register (IMS) Format ............................................................................ Communication Mode Selection Format ..................................................................................................... Flashpro II and Flashpro III Connection in 3-Wire Serial I/O Mode .......................................................... Flashpro II and Flashpro III Connection in UART Mode ............................................................................ Development Tool Configuration ................................................................................................................. Package Drawing of EV-9200GF-100 (reference) (unit: mm) .................................................................... Recommended Board Mounting Pattern of EV-9200GF-100 (reference) (unit: mm) ............................... Page 630 631 632 633 634 635 637 638 640 641 648 649 654 657 658 661 665 666 667 668 672 673 675 675 710 718 719
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Table No. 2-1 2-2 2-3 2-4 2-5 3-1 3-2 3-3 3-4 3-5 3-6 4-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 7-1 7-2 8-1 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 Title Port 1 Operation Modes .............................................................................................................................. Port 2 Operation Modes .............................................................................................................................. Port 3 Operation Modes .............................................................................................................................. Port 6 Operation Modes .............................................................................................................................. Pin Input/Output Circuit Types and Recommended Connection of Unused Pins ..................................... Vector Table .................................................................................................................................................. Internal RAM Area ....................................................................................................................................... Internal Memory Size Switching Register (IMS) Setting Value .................................................................. Register Bank Selection .............................................................................................................................. Correspondence between Function Names and Absolute Names ............................................................ List of Special Function Registers (SFRs) .................................................................................................. Time Required to Change Division Ratio ................................................................................................... Port Functions .............................................................................................................................................. Number of Input/Output Ports ..................................................................................................................... Port 1 Operation Modes .............................................................................................................................. Port 2 Operation Modes .............................................................................................................................. Port 3 Operation Modes .............................................................................................................................. Port 4 Operation Modes .............................................................................................................................. Port 5 Operation Modes .............................................................................................................................. Port 6 Operation Modes .............................................................................................................................. Port 6 Control Pin Function ......................................................................................................................... P60 to P65 Control Pin Specification .......................................................................................................... Port 10 Operation Modes ............................................................................................................................ Operations when Port 0 and Port 0 Buffer Registers (P0H, P0L) are Manipulated ................................. Real-Time Output Port Output Triggers (when P0MH = P0ML = 1) .......................................................... Operations of Timer ..................................................................................................................................... Timer/Event Counter 0 Interval Time .......................................................................................................... Timer/Event Counter 0 Programmable Square-Wave Output Setting Range ........................................... Timer/Event Counter 0 Pulse Width Measurement Range ........................................................................ Timer/Event Counter 0 Pulse Width Measurement Time ........................................................................... Timer Output (TO0/TO1) Operations .......................................................................................................... TO0, TO1 Toggle Output (fXX = 12.58 MHz) ............................................................................................... TO0, TO1 PWM Cycle (fXX = 12.58 MHz) ................................................................................................... TO0 PPG Output (fXX = 12.58 MHz) ........................................................................................................... Page 55 56 57 58 62 75 78 82 85 96 98 110 118 118 126 137 143 156 163 169 174 174 188 204 206 213 215 216 217 218 237 239 240 246
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Table No. 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 12-1 14-1 16-1 18-1 18-2 18-3 18-4 18-5 19-1 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 22-1 Title Timer/Event Counter 1 Intervals ................................................................................................................. Timer/Event Counter 1 Pulse Width Measurement Range ........................................................................ Timer/Event Counter 1 Pulse Width Measurement Time ........................................................................... Maximum Input Frequency and Minimum Input Pulse Width that can be Counted as Events ................ Timer/Event Counter 2 Intervals ................................................................................................................. Timer/Event Counter 2 Programmable Square-Wave Output Setting Range ........................................... Timer/Event Counter 2 Pulse Width Measurement Range ........................................................................ Clocks Enabled to be Input to Timer/Event Counter 2 ............................................................................... Timer Output (TO2/TO3) Operations .......................................................................................................... TO2/TO3 Toggle Output (fXX = 12.58 MHz) ................................................................................................ TO2/TO3 PWM Cycle (fXX = 12.58 MHz, BW2 = 0) ................................................................................... TO2/TO3 PWM Cycle (fXX = 12.58 MHz, BW2 = 1) ................................................................................... TO2 PPG Output (fXX = 12.58 MHz) ........................................................................................................... Timer 3 Intervals .......................................................................................................................................... Relation between Count Clock and Watch Timer Operation ..................................................................... A/D Conversion Time ................................................................................................................................... Differences between UART/IOE1 and UART2/IOE2 Names ..................................................................... Receive Error Causes .................................................................................................................................. Baud Rate Setting Methods ........................................................................................................................ Examples of BRGC Settings when Baud Rate Generator is Used ........................................................... Examples of Settings when External Baud Rate Input (ASCK) is Used ................................................... Differences in Name between IOE0 and IOE3 ........................................................................................... Transfer Rate and Maximum Number of Transmit Bytes in Communication Mode 1 .............................. Contents of Control Bits .............................................................................................................................. Control Field for Locked Slave Unit ............................................................................................................ Control Field for Unlocked Slave Unit ......................................................................................................... Contents of Telegraph Length Bit ................................................................................................................ Meaning of Slave Status ............................................................................................................................. Comparison between Existing and Simple IEBus Interface Functions ..................................................... Internal Registers of IEBus Controller ........................................................................................................ Interrupt Source List .................................................................................................................................... IEBus Controller Operation (Slave Status Request) of PD784938 Subseries ....................................... Pins P20 to P26 and Use of Detected Edge .............................................................................................. Page 271 272 273 285 305 306 307 307 331 333 335 336 341 373 394 414 427 439 454 454 455 457 468 472 473 473 473 477 480 483 501 510 517
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Table No. Title Page
23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 24-1 25-1 25-2 25-3 25-4 25-5 25-6 25-7 26-1 26-2 27-1 27-2 28-1 28-2 28-3 28-4 29-1 29-2 29-3 29-4 29-5
Interrupt Request Service Modes ............................................................................................................... Interrupt Request Sources .......................................................................................................................... Control Registers ......................................................................................................................................... Interrupt Control Register Flags Corresponding to Interrupt Request ...................................................... Multiple Interrupt Servicing .......................................................................................................................... Interrupts for which Macro Service can be Used ....................................................................................... Interrupt Acknowledge Processing Time ..................................................................................................... Macro Service Processing Time .................................................................................................................. System Clock Frequency and Refresh Pulse Output Cycle when Pseudo-Static RAM is Used ............. Operating States in HALT Mode ................................................................................................................. HALT Mode Release and Operations after Release .................................................................................. HALT Mode Release by Maskable Interrupt Request ................................................................................ Operating States in STOP Mode ................................................................................................................. STOP Mode Release and Operations after Release ................................................................................. Operating States in IDLE Mode .................................................................................................................. IDLE Mode Release and Operations after Release ................................................................................... Pin Statuses During Reset Input and After Reset Release ....................................................................... Hardware Status After Reset ....................................................................................................................... Differences between 78K/IV ROM Correction and 78K/0 ROM Correction .............................................. ROM Correction Configuration .................................................................................................................... Differences between the PD78F4938 Mask ROM Versions .................................................................... Internal Memory Size Switching Register (IMS) Settings .......................................................................... Communication Mode .................................................................................................................................. Flash Memory Programming Functions ...................................................................................................... List of Instructions by 8-Bit Addressing ...................................................................................................... List of Instructions by 16-Bit Addressing .................................................................................................... List of Instructions by 24-Bit Addressing .................................................................................................... List of Instructions by Bit Manipulation Instruction Addressing ................................................................. List of Instructions by Call/Return Instruction/Branch Instruction Addressing ..........................................
525 526 530 531 554 561 597 598 630 642 643 645 646 647 650 651 658 659 664 665 671 672 673 674 705 706 707 707 708
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[MEMO]
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The PD784938 Subseries consists of 78K/IV Series products that combine a 78K/IV Series CPU core enabling mounting large-capacity memory and a IEBusTM (Inter Equipment BusTM) controller. The 78K/IV Series consists of 16-bit single-chip microcontrollers, and comes with a high-performance CPU that has various functions including a function to access 1-Mbyte memory spaces. The PD784938 Subseries is based on the PD784908 Subseries. It features expanded internal ROM and RAM capacities and the addition of a ROM correction function. The PD784938 has a 256-Kbyte mask ROM and 10,240-byte RAM on chip. Besides an IEBus controller, it features among other things a high-performance timer counter, an 8-bit A/D converter, a PWM output function, a 2-channel independent serial interface, and a watch timer. The PD784937 replaces the mask ROM of the PD784938 with a 192-Kbyte mask ROM. The PD784936 replaces the mask ROM and RAM of the PD784938 with a 128-Kbyte mask ROM and a 6,656-byte RAM. The PD784935 replaces the mask ROM and RAM of the PD784938 with a 96-Kbyte mask ROM and a 5,120-byte RAM. The PD78F4938 replaces the mask ROM of the PD784938 with flash memory. The PD784938 Subseries product lineup is as follows.
Flash memory models
PD78F4938
Flash memory RAM 256 Kbytes 10,240 bytes
Mask ROM models
PD784938
ROM 256 Kbytes RAM 10,240 bytes
PD784937
ROM 192 Kbytes RAM 8,192 bytes
PD784936
ROM 128 Kbytes RAM 6,656 bytes
PD784935
ROM 96 Kbytes RAM 5,120 bytes
These models can be used in the following fields: * Car audio, etc.
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78K/IV Series Product Lineup
: In mass production : Under development
I2C bus supported
Multi-master I2C bus supported
PD784038Y PD784038
Standard models Enhanced internal memory capacity, pin compatible with the PD784026 Multi-master I2C bus supported PD784216Y/ 784216AY
PD784225Y PD784225
80 pins, added ROM correction
PD784026
Enhanced A/D, 16-bit timer, and power management
Multi-master I2C bus supported
PD784218Y PD784218
Enhanced internal memory capacity, added ROM correction
PD784216/ 784216A
100 pins, enhanced I/O and internal memory capacity
PD784054 PD784046
ASSP models On-chip 10-bit A/D
PD784955
For DC inverter control
PD784938 PD784908
On-chip IEBus controller Enhanced function of the PD784908, enhanced internal memory capacity, added ROM correction Multi-master I2C bus supported
PD784928Y PD784928 PD784915
For software servo control, on-chip analog circuit for VCR, enhanced timer Enhanced function of the PD784915
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1.1 Features * 78K/IV Series * High-speed instruction execution * Minimum instruction execution time: 320 ns (@ 6.29-MHz operation) 160 ns (@ 12.58-MHz operation) * Instruction set suitable for control applications * Data memory expansion function (1-Mbyte memory space: 2 bank specification pointers) * Interrupt controller (4-level priority system) * Vectored interrupt service/macro service/context switching * Standby functions: HALT/STOP/IDLE modes * Internal memory: * ROM Mask ROM: 256 Kbytes (PD784938) 192 Kbytes (PD784937) 128 Kbytes (PD784936) 96 Kbytes (PD784935) Flash memory: 256 Kbytes (PD78F4938) * RAM: 10,240 bytes (PD784938, 78F4938) 8,192 bytes (PD784937) 6,656 bytes (PD784936) 5,120 bytes (PD784935) * I/O pins: 80 * Software programmable pull-up: 70 inputs * Direct LED drive capability: * N-ch open-drain: * Serial interface * UART/IOE (3-wire serial I/O): 2 channels (with on-chip baud rate generator) * CSI (3-wire serial I/O): 2 channels * Real-time output ports (combination with timer/counter allows independent control of 2-system stepping motors) * A/D converter (8-bit resolution x 8 channels) * PWM outputs (12-bit resolution x 2 channels) * On-chip simple model with IEBus controller * Watch timer (operation with main clock possible in the IDLE mode) * Power-saving regulator * High-performance timer/counter * Timer/event counter (16 bits) x 3 units * Timer (16 bits) x 1 unit * Watchdog timer: 1 channel * Clock output function: fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16 can be selected * On-chip ROM correction function 24 outputs 4 outputs * Direct transistor drive capability: 8 outputs
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1.2 Ordering Information
Part Number Package 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) Mask ROM Mask ROM Mask ROM Mask ROM Flash memory Internal ROM
PD784935GF-xxx-3BA PD784936GF-xxx-3BA PD784937GF-xxx-3BA PD784938GF-xxx-3BA PD78F4938GF-3BA
Remark xxx indicates ROM code suffix.
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1.3 Pin Configuration (Top View) 1.3.1 Normal operation mode * 100-pin plastic QFP (14 x 20 mm)
PD784935GF-xxx-3BA, 784936GF-xxx-3BA, 784937GF-xxx-3BA, 784938GF-xxx-3BA, 78F4938GF-3BA
P25/INTP4/ASCK/SCK1
P23/INTP2/CI
P31/TxD/SO1
P30/RxD/SI1
P26/INTP5
P24/INTP3
P22/INTP1
P21/INTP0
P32/SCK0
AVDDNote 2
AVSSNote 3
P36/T02 P37/T03 P100 P101 P102 P103 P104 P105/SCK3 P106/SI3 P107/SO3 RESET XT2 XT1 VSS X2 X1 REGOFF REGC VDD P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/HLDAK P66/WAIT/HLDRQ P65/WR
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P77/ANI7
P33/SO0
P35/TO1
P34/TO0
P20/NMI
P27/SI0
AVREF1
RX
TX
P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 IC/VPPNotes 1, 4 PWM1 PWM0 P17 P16 P15 P14/TxD2/SO2 P13/RxD2/SI2 P12/ASCK2/SCK2 P11 P10 ASTB/CLKOUT P90 P91 P92 P93 P94 P95 P96 P97 P40/AD0 P41/AD1 P42/AD2
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
Notes
1. Connect the IC (Internally Connected)/VPP pin directly to VSS. 2. Connect the AVDD pin directly to VDD. 3. Connect the AVSS pin directly to VSS. 4. The VPP pin is used only in the PD78F4938.
P43/AD3
VSS
P64/RD
P63/A19
P62/A18
P61/A17
P60/A16
P57/A15
P56/A14
P55/A13
P54/A12
VDD
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A8 to A19: AD0 to AD7: ANI0 to ANI7: ASCK, ASCK2: ASTB: AVDD: AVREF1: AVSS: CI: CLKOUT: HLDAK: HLDRQ: NMI: P00 to P07: P10 to P17: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P67: P70 to P77: P90 to P97: P100 to P107: Note
Address Bus Address/Data Bus Analog Input Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Clock Input Clock Output Hold Acknowledge Hold Request Non-maskable Interrupt Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port9 Port10
PWM0, PWM1: RD: REFRQ: REGC: REGOFF: RESET: RX: RxD, RxD2: SCK0 to SCK3: SI0 to SI3: SO0 to SO3: TEST: TO0 to TO3: TxD, TxD2: TX: VDD: VPPNote: VSS: WAIT: WR: X1, X2: XT1, XT2:
Pulse Width Modulation 0, 1 Read Strobe Refresh Request Regulator Capacitance Regulator Off Reset IEBus Receive Data Receive Data Serial Clock Serial Input Serial Output Test Timer Output Transmit Data IEBus Transmit Data Power Supply Programming Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Watch)
INTP0 to INTP5: Interrupt from Peripherals
The VPP pin is used only in the PD78F4938.
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1.4 Application System Configuration Example (Car Audio (Tuner, Deck))
PD784938
IEBus Interrupt input General-purpose port Cassette deck unit
Front panel Remote controller signal receiver circuit
PC2800A, etc.
FIPTM Key matrix
FIP controller/driver PD16312, etc. LED
3-wire serial I/O SIO with automatic transmit/receive function
Tuner pack
CD unit (changer, single CD, etc.)
DSP unit Audio system control circuit Electronic volume EEPROMTM 3-wire serial I/O IEBus controller IEBus driver/ receiver TV unit
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1.5 Block Diagram
NMI INTP0 to INTP5 INTP3 TO0 TO1
PROGRAMMABLE INTERRUPT CONTROLLER
UART/IOE2 BAUD-RATE GENERATOR UART/IOE1 BAUD-RATE GENERATOR CLOCKED SERIAL INTERFACE CLOCKED SERIAL INTERFACE3 CLOCK OUTPUT
RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SCK0 SO0 SI0 SCK3 SO3 SI3 ASTB/CLKOUT AD0 to AD7 A8 to A15 A16 to A19 RD WR WAIT/HLDRQ REFRQ/HLDAK D0 to D7Note A0 to A16Note CENote OENote PGMNote
TIMER/EVENT COUNTER0 (16 BITS)
INTP0
TIMER/EVENT COUNTER1 (16 BITS)
INTP1 INTP2/CI TO2 TO3
TIMER/EVENT COUNTER2 (16 BITS)
78 K/IV CPU CORE
ROM
TIMER3 (16 BITS)
P00 to P03 P04 to P07
REAL-TIME OUTPUT PORT
BUS I/F
PWM0 PWM PWM1
RAM
PORT0 ANI0 to ANI7 AVDD AVREF1 AVSS INTP5 A/D CONVERTER PORT1 PORT2 PORT3 PORT4 TX RX RESET TEST X1 X2 REGC REGOFF VPPNote VDD VSS XT1 XT2 IEBus CONTROLLER PORT5 PORT6 PORT7 SYSTEM CONTROL (REGULATOR) WATCHDOG TIMER PORT9 PORT10
P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P90 to P97 P100 to P107
WATCH TIMER
Note
PD78F4938 only
Remark The capacities of the internal ROM and RAM varies depending on the product.
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1.6 List of Functions
Part Number Item Number of basic instructions (mnemonics) General-purpose register Minimum instruction execution time 8 bits x 32 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping) 320 ns/636 ns/1.27 s/2.54 s (@6.29-MHz operation) 160 ns/320 ns/636 ns/1.27 s (@12.58-MHz operation) 96 Kbytes (mask ROM) 5,120 bytes 128 Kbytes (mask ROM) 6,656 bytes 192 Kbytes (mask ROM) 8,192 bytes 256 Kbytes (mask ROM) 10,240 bytes 256 Kbytes (flash memory) 113
PD784935
PD784936
PD784937
PD784938
PD78F4938
Internal memory
ROM
RAM Memory space I/O port Total Input I/O Pins with ancillary functionsNote LED direct drive output Transistor direct drive N-ch open-drain
1 Mbyte with program and data memories combined 80 8 72 24 8 4 4 bits x 2, or 8 bits x 1 Internal (simple version) Timer/event counter 0 (16 bits): Timer counter x 1 Capture register x 1 Compare register x 2 Timer/event counter 1 (16 bits): Timer counter x 1 Capture register x 1 Capture/compare register x 1 Compare register x 1 Timer/event counter 2: Timer counter x 1 Capture register x 1 Capture/compare register x 1 Compare register x 1 Timer 3: Timer counter x 1 Compare register x 1 Pulse output * Toggle output * PWM/PPG output * One-shot pulse output Real-time output port
Real-time output port IEBus controller Timer/counter
Pulse output * Toggle output * PWM/PPG output
Watch timer
Generates interrupt request at intervals of 0.5 second (internal watch clock oscillator) Main clock (12.58 MHz (MAX.)) or watch clock (32.7 kHz) selectable as input clock Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, and fCLK/16 (can also be used as 1-bit output port) 12-bit resolution x 2 channels UART/IOE (3-wire serial I/O): 2 channels (with baud rate generator) CSI (3-wire serial I/O): 2 channels 8-bit resolution x 8 channels 1 channel HALT/STOP/IDLE mode
Clock output PWM output Serial interface
A/D converter Watchdog timer Standby
Note
The pins with ancillary functions are included in the I/O pins.
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Part Number Item Interrupt Hardware source Software source Non-maskable Maskable
PD784935
PD784936
PD784937
PD784938
PD78F4938
27 (Internal: 20, External: 7 (sampling clock variable input: 1)) BRK instruction, BRKCS instruction, operand error Internal: 1, External: 1 Internal: 19, External: 6 4 levels of programmable priority 3 processing type: Vectored interrupt/macro service/context switching * VDD = 4.0 to 5.5 V (Main clock: @ fXX = 12.58-MHz operation, Internal system clock = @ fXX, fCYK = 79 ns) * VDD = 3.5 to 5.5 V (Other than above, fCYK = 159 ns) * VDD = 4.5 to 5.5 V (Main clock: @ fXX = 12.58MHz operation, Internal system clock = @ fXX, fCYK = 79 ns) * VDD = 4.0 to 5.5 V (Other than above, fCYK = 159 ns)
Supply voltage
Package
100-pin plastic QFP (14 x 20 mm)
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The outline of the timer is as follows (for details, refer to CHAPTER 8 OUTLINE OF TIMER)
Name Item Count width 8 bits 16 bits Operation mode Interval timer External event counter One-shot timer Function Timer output Toggle output PWM/PPG output One-shot pulse Real-time output Pulse width measurement Number of interrupt requests outputNote -- 1 input 2 1 input 2 -- 2ch -- -- -- -- -- -- -- 2 inputs 2 2ch 2ch 2ch 2ch 1ch -- -- -- -- -- -- -- -- 1 Timer/Event Counter 0 -- Timer/Event Counter 1 Timer/Event Counter 2 Timer 3
Note
The one-shot pulse output function is used to make a pulse output level active by software and inactive by hardware (interrupt request signal). This function is different from the one-shot timer function of timer/event counter 2 in nature.
The outline of the serial interface is as follows (for details, refer to CHAPTER 17 OUTLINE OF SERIAL INTERFACE).
Function 3-wire serial I/O mode Asynchronous serial I/O mode SBI mode UART/IOE1 (MSB first/LSB first switchable) (On-chip dedicated baud rate generator ) -- UART/IOE2 (MSB first/LSB first switchable) (On-chip dedicated baud rate generator ) -- IOE0 (MSB first/LSB first switchable) -- (MSB first/LSB first switchable) IOE3 (MSB first/LSB first switchable) -- (MSB first/LSB first switchable)
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1.7 Differences among Products in PD784938 Subseries
Part Number Item Internal memory ROM 96 Kbytes (mask ROM) 5,120 bytes 128 Kbytes (mask ROM) 6,656 bytes 192 Kbytes (mask ROM) 8,192 bytes 256 Kbytes (mask ROM) 10,240 bytes 256 Kbytes (flash memory)
PD784935
PD784936
PD784937
PD784938
PD78F4938
RAM
1.8 Main Differences with PD784908 Subseries The PD784938 Subseries replaces the PROM of PROM products in the PD784908 Subseries with flash memory and added a ROM correction function.
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2.1 Pin Function Lists 2.1.1 Normal operation mode (1) Port pins (1/2)
Pin Name P00 to P07 Input/Output Input/output Alternate Function -- Function Port 0 (P0): * 8-bit input/output port * Can be used as real-time output ports (4 bits x 2) * Input/output can be specified in 1-bit units * For input mode pins, on-chip pull-up resistor connection can be specified at once by means of software * Transistor drive capability Port 1 (P1): * 8-bit input/output port * Input/output can be specified in 1-bit units * For input mode pins, on-chip pull-up resistor connection can be specified at once by means of software * LED drive capability
P10 P11 P12 P13 P14 P15 to P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 to P37
Input/output
-- -- ASCK2/SCK2 RxD2/SI2 TxD2/SO2 --
Input
NMI INTP0 INTP1 INTP2/CI INTP3 INTP4/ASCK/SCK1 INTP5 SI0
Port 2 (P2): * 8-bit input/output port * P20 cannot be used as a general-purpose port (non-maskable interrupt). Input level can be confirmed in the interrupt routine. * For P22 to P27, on-chip pull-up resistor connection can be specified by means of software in 6-bit units * The P25/INTP4/ASCK/SCK1 pin operates as the SCK1 output pin in accordance with the CSIM1 register specification
Input/output
RxD/SI1 TxD/SO1 SCK0 SO0 TO0 to TO3
Port 3 (P3): * 8-bit input/output port * Input/output can be specified in 1-bit units * For input mode pins, on-chip pull-up resistor connection can be specified at once by means of software * P32 and P33 can be set in N-ch open-drain mode
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(1) Port pins (2/2)
Pin Name P40 to P47 Input/Output Input/output Alternate Function AD0 to AD7 Function Port 4 (P4): * 8-bit input/output port * Input/output can be specified in 1-bit units * For input mode pins, on-chip pull-up resistor connection can be specified at once by means of software * LED drive capability Port 5 (P5): * 8-bit input/output port * Input/output can be specified in 1-bit units * For input mode pins, on-chip pull-up resistor connection can be specified at once by means of software * LED drive capability Port 6 (P6): * 8-bit input/output port * Input/output can be specified in 1-bit units * For input mode pins, on-chip pull-up resistor connection can be specified at once by means of software
P50 to P57
Input/output
A8 to A15
P60 to P63 P64 P65 P66 P67 P70 to P77
Input/output
A16 to A19 RD WR WAIT/HLDRQ REFRQ/HLDAK
Input/output
ANI0 to ANI7
Port 7 (P7): * 8-bit input/output port * Input/output can be specified in 1-bit units
P90 to P97
Input/output
--
Port 9 (P9): * 8-bit input/output port * Input/output can be specified in 1-bit units * For input mode pins, on-chip pull-up resistor connection can be specified at once by means of software Port 10 (P10): * 8-bit input/output port * Input/output can be specified in 1-bit units * For input mode pins, on-chip pull-up resistor connection can be specified at once by means of software * P105 and P107 can be set in N-ch open-drain mode
P100 to P104 P105 P106 P107
Input/output
-- SCK3 SI3 SO3
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(2) Non-port pins (1/2)
Pin Name TO0/TO3 CI RxD RxD2 TxD TxD2 ASCK ASCK2 SI0 SI1 SI2 SI3 SO0 SO1 SO2 SO3 SCK0 SCK1 SCK2 SCK3 NMI INTP0 Input Input/output Output Input Input Output Input/Output Output Input Input Alternate Function P34 to P37 P23/INTP2 P30/SI1 P13/SI2 P31/SO1 P14/SO2 P25/INTP4/SCK1 P12/SCK2 P27 P30/RxD P13/RxD2 P106 P33 P31/TxD P14/TxD2 P107 P32 P25/INTP4/ASCK P12/ASCK2 P105 P20 P21 Timer output Count clock input to timer/event counter 2 Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data input (3-wire serial I/O0) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data input (3-wire serial I/O3) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial data output (3-wire serial I/O3) Serial clock input/output (3-wire serial I/O0) Serial clock input/output (3-wire serial I/O1) Serial clock input/output (3-wire serial I/O2) Serial clock input/output (3-wire serial I/O3) External interrupt requests -- * Count clock input to timer/event counter 1 * CR11 or CR12 capture trigger signal INTP1 P22 * Count clock input to timer/event counter 2 * CR22 capture trigger signal * Count clock input to timer/event counter 2 * CR21 capture trigger signal INTP3 P24 * Count clock input to timer/event counter 0 * CR02 capture trigger signal -- A/D converter conversion start trigger input Time division address/data bus (external memory connection) Upper address bus (external memory connection) Upper address with address extension (external memory connection) External memory read strobe External memory write strobe Wait insertion External pseudo-static memory refresh pulse output Bus hold request input Bus hold response output Function
INTP2
P23/CI
INTP4 INTP5 AD0 to AD7 A8 to A15 A16 to A19 RD WR WAIT REFRQ HLDRQ HLDAK Input/output Output Output Output Output Input Output Input Output
P25/ASCK0/SCK1 P26 P40 to P47 P50 to P57 P60 to P63 P64 P65 P66/HLDRQ P67/HLDAK P66/WAIT P67/REFRQ
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(2) Non-port pins (2/2)
Pin Name ASTB CLKOUT PWM0 PWM1 RX TX REGC Input/Output Output Output Output Output Input Output -- Alternate Function CLKOUT ASTB -- -- -- -- -- Function Time division address (A0 to A7) latch timing output (during external memory access) Clock output PWM output 0 PWM output 1 Data input (IEBus) Data output (IEBus) Connection of capacitor for regulator output stabilization/power supply when regulator stops Regulator operation specification signal Chip reset System clock oscillation crystal connections (clock can also be input to X1) -- -- P70 to P77 -- A/D converter analog voltage inputs A/D converter reference voltage application A/D converter positive power supply A/D converter GND Positive power supply GND Input VPP IC Internally connected. Connect directly to VSS (IC test pin). Flash memory programming mode setting. High voltage application during program write/verify. Connect directly to VSS in normal operating mode. Watch clock connection
REGOFF RESET X1 X2 XT1 XT2 ANI0 to ANI7 AVREF1 AVDD AVSS VDD VSS IC VPP
-- Input Input -- Input -- Input --
-- -- --
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2.2 Pin Functions 2.2.1 Normal operation mode (1) P00 to P07 (Port 0) ... 3-state input/output Port 0 is an 8-bit input/output port with an output latch, and has direct transistor drive capability. Input/output can be specified in 1-bit units by setting the port 0 mode register (PM0). Each pin incorporates a software programmable pull-up resistor. P00 to P03 and P04 to P07 can output the port 0 buffer register (P0L, P0H) contents at any time interval as 4-bit or 8-bit real-time output port. The real-time output port control register (RTPC) is used to select whether this port is used as a normal output port or a real-time output port. When RESET is input, port 0 is set as an input port (output high-impedance state), and the output latch contents become undefined. (2) P10 to P17 (Port 1) ... 3-state input/output Port 1 is an 8-bit input/output port with an output latch. Input/output can be specified in 1-bit units by setting the port 1 mode register (PM1). Each pin incorporates a software programmable pull-up resistor. This port has direct LED drive capability. Pins P12 to P14 can also be made to function as serial input/output pins by setting the port 1 mode control register (PMC1). When RESET is input, port 1 is set as an input port (output high-impedance state), and the output latch contents are undefined. Table 2-1. Port 1 Operation Modes
Pin Name P10 P11 P12 P13 P14 P15 to P17 Port Mode Input/output port Control Signal Input/Output Mode -- -- ASCK2/SCK2 input/output RxD2/SI2 input TxD2/SO2 output -- Operation to Operate as Control Pin -- -- Set (to 1) PMC12 bit of PMC1 Set (to 1) PMC13 bit of PMC1 Set (to 1) PMC14 bit of PMC1 --
(a) Port mode P12 to P14 operate as port mode pins when the relevant bits of the port 1 mode control (PMC1) register are cleared (0), and P10 and P11 and P15 to P17 always operate as port mode pins. Input/output can be specified in 1-bit units by setting the port 1 mode register (PM1). (b) Control signal input/output mode P12 to P14 can be set as control pins in 1-bit units by setting the port 1 mode control (PMC1) register. (i) ASCK2/SCK2 ASCK2 is the asynchronous serial interface baud rate clock input pin. SCK2 is the serial clock input/output pin (in 3-wire serial I/O2 mode). (ii) RxD2/SI2 RxD2 is the asynchronous serial interface serial data input pin. SI2 is the serial data input pin (in 3-wire serial I/O2 mode). (iii) TxD2/SO2 TxD2 is the asynchronous serial interface serial data output pin. SO2 is the serial data output pin (in 3-wire serial I/O2 mode).
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(3) P20 to P27 (Port 2) ... Input Port 2 is an 8-bit input-only port. P22 to P27 incorporate a software programmable pull-up resistor. As well as operating as an input port, port 2 pins also operate as control signal input pins, such as external interrupt signal pins (see Table 2-2). All 8 pins are Schmitt-triggered inputs to prevent misoperation due to noise. Also, pin P25 can also be made to function as a serial clock output pin by selecting the external clock as "serial operation enabled" with the clocked serial interface mode register 1 (CSIM1). Table 2-2. Port 2 Operation Modes
Port P20 P21 Input port/NMI inputNote Input port/INTP0 input/CR11 capture trigger input/ timer/event counter 1 count clock/real-time output port trigger signal Input port/INTP1 input/CR22 capture trigger input Input port/INTP2 input/CI input Input port/INTP3 input/CR02 capture trigger input/ timer/event counter 0 count clock Input port/INTP4 input/ASCK input/SCK1 input/output Input port/INTP5 input/A/D converter external trigger input Input port/SI0 input Function
P22 P23 P24
P25 P26 P27
Note NMI input is acknowledged regardless of whether interrupts are enabled or disabled. (a) Function as port pins The pin level can always be read or tested regardless of the alternate function pin operation. (b) Functions as control signal input pins (i) NMI (Non-maskable Interrupt) The external non-maskable interrupt request input pin. Rising edge detection or falling edge detection can be specified by setting the external interrupt mode register 0 (INTM0). (ii) INTP0 to INTP5 (Interrupt from Peripherals) External interrupt request input pins. When the valid edge specified by the external interrupt mode register 0, 1 (INTM0/INTM1) is detected by pins INTP0 to INTP5, an interrupt is generated (see CHAPTER 22 EDGE DETECTION FUNCTION). In addition, pins INTP0 to INTP3 and INTP5 are also used as external trigger input pins with the various functions shown below. * INTP0 ....... Timer/event counter 1 capture trigger input pin Timer/event counter 1 external count clock input pin Real-time output port trigger input pin * INTP1 ....... Timer/event counter 2 capture trigger input pin to capture register (CR22) * INTP2 ....... Timer/event counter 2 external count clock input pin Capture trigger input pin to capture/compare register (CR21) * INTP3 ....... Timer/event counter 0 capture trigger input pin Timer/event counter 0 external count clock input pin * INTP5 ....... A/D converter external trigger input pin
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(iii) CI (Clock Input) The timer/event counter 2 external clock input pin. (iv) ASCK (Asynchronous Serial Clock) The external baud rate clock input pin. (v) SCK1 (Serial Clock) The serial clock input/output pin (in 3-wire serial I/O1 mode). (vi) SI0 (Serial Input 0) The serial data input pin (in 3-wire serial I/O0 mode). (4) P30 to P37 (Port 3) ... 3-state input/output Port 3 is an 8-bit input/output port with an output latch. Input/output can be specified bit-wise by setting the port 3 mode register (PM3). Each pin incorporates a software programmable pull-up resistor. P32 and P33 can be set in the N-ch opendrain mode. In addition to its function as an input/output port, port 3 also has various control signal pin alternate functions. The operation mode can be specified in 1-bit units by setting the port 3 mode control register (PMC3), as shown in Table 2-3. The pin level of any pin can always be read or tested regardless of the alternate-function operation. When RESET is input, port 3 is set as an input port (output high-impedance state), and the output latch contents are undefined. Table 2-3. Port 3 Operation Modes (n = 0 to 7)
Mode Setting Condition P30 P31 P32 P33 P34 P35 P36 P37 Port Mode PMC3n = 0 Input/output port Control Signal Input/Output Mode PMC3n = 1 RxD input / SI1 input TxD output / SO1 output SCK0 input/output SO0 output TO0 output TO1 output TO2 output TO3 output
(a) Port mode Each port specified as port mode by the port 3 mode control register (PMC3) can be specified as input/output in 1bit units by setting the port 3 mode register (PM3). (b) Control signal input/output mode Pins can be set as control pins in 1-bit units by setting the port 3 mode control register (PMC3). (i) RxD (Receive Data) /SI1 (Serial Input 1) RxD is the asynchronous serial interface serial data input pin. SI1 is the serial data input pin (in 3-wire serial I/O1 mode).
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(ii)
TxD (Transmit Data) /SO1 (Serial Output 1) TxD is the asynchronous serial interface serial data output pin. SO1 is the serial data output pin (in 3-wire serial I/O1 mode).
(iii) SCK0 (Serial Clock 0) SCK0 is the clocked serial interface serial clock input/output pin (in 3-wire serial I/O 0 mode). (iv) SO0 (Serial Output 0) SO0 is the serial data output pin (in 3-wire serial I/O 0 mode). (v) TO0 to TO3 (Timer Output) The timer output pins. (5) P40 to P47 (Port 4) ... 3-state input/output Port 4 is an 8-bit input/output port with an output latch. Input/output can be specified in 1-bit units by setting the port 4 mode register (PM4). Each pin incorporates a software programmable pull-up resistor. This port has direct LED drive capability. Port 4 also functions as the time division address/data bus (AD0 to AD7) by the memory expansion mode register (MM) when external memory or I/Os are expanded. When RESET is input, port 4 is set as an input port (output high-impedance state), and the output latch contents are undefined. (6) P50 to P57 (Port 5) ... 3-state input/output Port 5 is an 8-bit input/output port with an output latch. Input/output can be specified in 1-bit units by setting the port 5 mode register (PM5). Each pin incorporates a software programmable pull-up resistor. This port has direct LED drive capability. In addition, P50 to P57 can be selected by means of the memory expansion mode register (MM) in 2-bit units as pins that function as the address bus (A8 to A15) when external memory or I/Os are expanded. When RESET is input, port 5 is set as an input port (output high-impedance state), and the output latch contents are undefined. (7) P60 to P67 (Port 6) ... 3-state input/output Port 6 is an 8-bit input/output port with an output latch. P60 to P67 incorporate a software programmable pull-up resistor. In addition to its function as a port, port 6 also has various alternate-function control signal pin functions, as shown in Table 2-4. Operations as control pins are performed by the respective function operations. When RESET is input, P60 to P67 are set as input port pins (output high-impedance state), and the output latch contents are undefined. Table 2-4. Port 6 Operation Modes
Pin Name P60 to P63 P64 P65 P66 Port Mode Input/output ports Control Signal Input/Output Mode A16 to A19 output RD output WR output WAIT input HLDRQ input P67 HLDAK output REFRQ output Set (to 1) the RFEN bit of the RFM Operation to Operate as Control Pin Specified in 2-bit units by bits MM3 to MM0 of the MM External memory expansion mode is specified by bits MM3 to MM0 of the MM Specified by setting bits PWn1 & PWn0 (n = 0 to 7) of the PWC1 & PWC2 and P66 to input mode Bus hold enabled by the HLDE bit of the HLDM
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(a) Port mode Each port not set in the control mode can be set in the input or output mode in 1-bit units by using the port 6 mode register (PM6). (b) Control signal input/output mode (i) A16 to A19 (Address Bus) Upper address bus output pins in case of external memory space expansion (10000H to FFFFFH). These pins operate in accordance with the memory expansion mode register (MM). (ii) RD (Read Strobe) Pin that outputs the strobe signal for an external memory read operation. Operates in accordance with the memory expansion mode register (MM). (iii) WR (Write Strobe) Pin that outputs the strobe signal for an external memory write operation. Operates in accordance with the memory expansion mode register (MM). (iv) WAIT (Wait) Wait signal input pin. Operates in accordance with the programmable wait control registers (PWC1, PWC2). (v) REFRQ (Refresh Request) This pin outputs refresh pulses to pseudo-static memory when this memory is connected externally. Operates in accordance with the refresh mode register (RFM). (vi) HLDRQ (Hold Request) External bus hold request signal input pin. (HLDM). (vii) HLDAK (Hold Acknowledge) Bus hold acknowledge signal output pin. (HLDM). (8) P70 to P77 (Port 7) ... 3-state input/output Port 7 is an 8-bit input/output port. In addition to operating as an input/output port, it also operates as the A/D converter analog input pins (ANI0 to ANI7). Input/output can be specified in 1-bit units by setting the port 7 mode register (PM7). The levels of these pins can always be read or tested, regardless of the alternate-function operation. When RESET is input, port 7 is set as an input port (output high-impedance state), and the output latch contents are undefined. (9) P90 to P97 (Port 9) ... 3-state input/output Port 9 is an 8-bit input/output port with an output latch. Input/output can be specified in 1-bit units by setting the port 9 mode register (PM9). Each pin incorporates a software programmable pull-up resistor. When RESET is input, port 9 is set as an input port (output high-impedance state), and the output latch contents are undefined. Operates in accordance with the hold mode register Operates in accordance with the hold mode register
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(10) P100 to P107 (Port 10) ... 3-state input/output Port 10 is an 8-bit input/output port with an output latch. Input/output can be specified in 1-bit units by setting the port 10 mode register (PM10). Each pin incorporates a software programmable pull-up resistor. P105 and P107 can be set in the N-ch open-drain mode. P105 to P107 pins also function as the serial input/output pin by the port 10 mode control register (PMC10). When RESET is input, port 10 is set as an input port (output high-impedance state), and the output latch contents are undefined. (11) ASTB (Address Strobe)/CLKOUT (Clock Output) ... Output This pin outputs the timing signal that latches address information externally in order to access an external address. It also operates as the pin that supplies the clock to an external device. (12) X1, X2 (Crystal) The internal clock oscillation crystal connection pins. When the clock is supplied externally, it is input to the X1 pin. Usually signal with the inverse phase of the X1 pin signal phase is input to the X2 pin (Refer to 4.3.1 Clock oscillator). (13) RESET (Reset) ... Input Active-low reset input (14) AVREF1 A/D converter reference voltage input pin (15) AVDD A/D converter power supply pin. This should be made at the same potential as the VDD pin. (16) AVSS A/D converter GND pin. This should be made at the same potential as the VSS pin. (17) VDD Positive power supply pins. All VDD pins should be connected to the positive power supply. (18) VSS GND potential pins. All VSS pins should be connected to the ground. (19) XT1 and XT2 These pins connect a crystal for watch clock oscillation. (20) PWM0 and PWM1 These pins function as PWM output pins when so specified by the PWM control register (PWMC). (21) RX IEBus data input pin (22) TX IEBus data output pin (23) REGC This pin connects a capacitor for stabilizing the regulator output. Supply a voltage same as VDD to this pin when the regulator is stopped (refer to Figure 5-1. Regulator Peripherals Block Diagram).
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(24) REGOFF This pin controls the regulator operation by operating or stopping the regulator. (25) VPP (PD78F4938) only High-voltage apply pin for flash memory programming mode setting and program write/verify (26) IC IC test pin. Connect directly to VSS.
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2.3 Input/Output Circuits and Connection of Unused Pins Table 2-5 shows the input/output circuit types of the pins that have functions, and the connection method when that function is not used. Each input/output circuit type is shown in Figure 2-1. Table 2-5. Pin Input/Output Circuit Types and Recommended Connection of Unused Pins (1/2)
Pin Name Input/Output Circuit Type 5-A Input/Output Recommended Connection of Unused Pins Input: Connect to VDD
P00 to P07 P10, P11 P12/ASCK2/SCK2 P13/RxD2/SI2 P14/TxD2/SO2 P15 to P17 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1
Input/output
Output: Leave open 8-A 5-A
2
Input
Connect to VDD or VSS
2-A
Connect to VDD
8-A
Input/output
Input:
Connect to VDD
Output: Leave open P26/INTP5 P27/SI0 P30/RxD/SI1 P31/TxD/SO1 P32/SCK0 P33/SO0 P34/TO0 to P37/TO3 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK 5-A 10-A 5-A Input/output Input: Connect to VDD 2-A Input Connect to VDD
Output: Leave open
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Table 2-5. Pin Input/Output Circuit Types and Recommended Connection of Unused Pins (2/2)
Pin Name Input/Output Circuit Type 20 5-A Input/Output Recommended Connection of Unused Pins Input: Connect to VDD or VSS
P70/ANI0 to P77/ANI7 P90 to P97 P100 to P104 P105/SCK3 P106/SI3 P107/SO3 ASTB/CLKOUT RESET IC/VPP XT2 XT1 REGOFF REGC PWM0, PWM1 RX TX AVREF1 AVSS AVDD
Note
Input/output
Output: Leave open
10-A 8-A 10-A 4 2 1 -- -- 1 -- 3 2 3 -- -- Output Input Output Input Leave open Connect to VDD or VSS Leave open Connect to VSS -- Input Output Input Leave open -- Directly connect to VSS Leave open Connect to VSS Connect to VDD
Connect to VDD
Note
The VPP pin is used only in the PD78F4938.
Caution If the input/output mode is undefined for an input/output alternate-function pin, it should be connected to VDD via a resistor of several tens of k (especially when the reset input pin goes to the low-level input voltage or over upon powering on, and when input/output is switched by software.) Remark The type numbers are standard for the 78K Series, and therefore are not necessarily serial numbers within each product (there are non-incorporated circuits).
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Figure 2-1. Pin Input/Output Circuits
Type 1 P IN N Type 5-A Pullup enable Data
VDD
VDD P VDD P IN/OUT Output disable N
Type 2 IN Type 8-A Schmitt-triggered input with hysteresis characteristics. Pullup enable Type 2-A Data VDD P Pullup enable Output disable N VDD P IN/OUT Input enable VDD P
IN Type 10-A Schmitt-triggered input with hysteresis characteristics. Pullup enable Type 3 VDD VDD P-ch data N-ch OUT Open drain Output disable N Data P IN/OUT VDD P
Type 20 Type 4 VDD Data P OUT Output Disable N Comparator + VREF (Threshold voltage) Input enable Output disable Data
VDD P IN/OUT N
P N
Push-pull output allowing output to be set to high impedance (P-ch & N-ch both off).
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2.4 Cautions When connecting unused pins, if the input/output mode is undefined for an input/output alternate function, it should be connected to VDD with a resistor of several tens of k (especially when the reset input pin becomes the low-level input voltage or over upon powering on, and when input/output is switched by software.)
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[MEMO]
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3.1 Memory Space The PD784938 can access a 1-Mbyte memory space. The mapping of the internal data area (special function registers and internal RAM) depends on the LOCATION instruction. A LOCATION instruction must be executed after reset release, and can only be used once. The program after reset release must be as follows: RSTVCT CSEG DW to INITSEG CSEG MOVG BASE SP, #STKBGN RSTSTRT: LOCATION 0H; or LOCATION 0FH AT 0 RSTSTRT
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(1) When LOCATION 0 instruction is executed * Internal memory The internal data area and internal ROM area are follows:
Part Number Internal Data Area 0EB00H to 0FFFFH Internal ROM Area 00000H to 0EAFFH 10000H to 17FFFH 00000H to 0E4FFH 10000H to 1FFFFH 00000H to 0DEFFH 10000H to 2FFFFH 00000H to 0D5FFH 10000H to 3FFFFH
PD784935 PD784936 PD784937 PD784938 PD78F4938
0E500H to 0FFFFH
0DF00H to 0FFFFH
0D600H to 0FFFFH
Caution The following areas of the internal ROM that overlap the internal data area cannot be used when the LOCATION 0 instruction is executed.
Part Number Area That Cannot Be Used 0EB00H to 0FFFFH (5,376 bytes) 0E500H to 0FFFFH (6,192 bytes) 0DF00H to 0FFFFH (8,448 bytes) 0D600H to 0FFFFH (10,752 bytes)
PD784935 PD784936 PD784937 PD784938 PD78F4938
* External memory The external memory is accessed in the external memory expansion mode. (2) When LOCATION 0FH instruction is executed * Internal memory The internal data area and internal ROM area are follows:
Part Number Internal Data Area FEB00H to FFFFFH FE500H to FFFFFH FDF00H to FFFFFH FD600H to FFFFFH Internal ROM Area 00000H to 17FFFH 00000H to 1FFFFH 00000H to 2FFFFH 00000H to 3FFFFH
PD784935 PD784936 PD784937 PD784938 PD78F4938
* External memory The external memory is accessed in the external memory expansion mode.
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Figure 3-1. PD784935 Memory Map
When location 0 instruction is executed
FFFFF H
When location 0FH instruction is executed
F F F F F F F F F F FF FD FD F0 EF F F 0 0 F H Special function registers (SFRs) H H Note 1 (256 bytes) H H
0FEFF H
FFEFF H
External memoryNote 1 (928 Kbytes)
0FE80 H 0FE7F H
General-purpose registers (128 bytes)
FFE80 H FFE7F H FEB0 0 H FEAFF H
Internal RAM (5,120 bytes)
18000H 17FFFH
1 0 0 0 0 0
0 F F F F F
00 FF FD FD F0 EF
0 F F 0 0 F
H H Special function registers (SFRs) H H Note 1 (256 bytes) H H
Internal ROM (32,768 bytes)
0FE39 H 0FE06 H
Macro service control word area (42 bytes) Data area (512 bytes)
FFE2F H FFE06 H
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Internal RAM (5,120 bytes)
0EB0 0 H 0EAFF H
0FD0 0 H 0FCFF H
FFD0 0 H FFCFF H
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Program/data area (4,608 bytes)
0EB0 0 H FEB0 0 H
External memoryNote 1 (944,896 bytes)
17FFFH 10000H
17FFFH
Note 2
0EAFF H
Note 4
Program/data area Note 3
01000H 00FFFH
Internal ROM (60,160 bytes)
00800H 007FFH 00080H 0007FH 00040H 0003FH 00000H 00000H
CALLF entry area (2 Kbytes)
18000H 17FFFH
CALLT table area (64 bytes) Vector table area (64 bytes)
Note 4
Internal ROM (96 Kbytes)
00000H
Notes 1. Accessed in external memory expansion mode. 2. The 5,376 bytes of this area can be used as internal ROM only when the LOCATION 0FH instruction is executed. 3. 92,928 bytes when the LOCATION 0 instruction is executed, and 98,304 bytes when the LOCATION 0FH instruction is executed. 4. Base area, reset or interrupt entry area, excluding internal RAM in the case of reset.
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FFFFF H
Figure 3-2. PD784936 Memory Map
When location 0 instruction is executed
When location 0FH instruction is executed
F F F F F F F F F F FF FD FD F0 EF F F 0 0 F H Special function registers (SFRs) H H Note 1 (256 bytes) H H
0FEFF H
FFEFF H
External memory Note 1 (896 Kbytes)
0FE80 H 0FE7F H
General-purpose registers (128 bytes)
FFE80 H FFE7F H FE500 H FE4FF H
Internal RAM (6,656 bytes)
20000H 1FFFFH
1 0 0 0 0 0
0 F F F F F
00 FF FD FD F0 EF
0 F F 0 0 F
H H Special function registers (SFRs) H H Note 1 (256 bytes) H H
Internal ROM (65,536 bytes)
0FE39 H 0FE06 H
Macro service control word area (42 bytes) Data area (512 bytes)
FFE2F H FFE06 H
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Internal RAM (6,656 bytes)
0E500 H 0E4FF H
0FD0 0 H 0FCFF H
FFD0 0 H FFCFF H
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Program/data area (6,144 bytes)
0E500 H FE500 H
External memoryNote 1 (910,720 bytes)
1FFFFH 10000H
1FFFFH
Note 2
0E4FF H
Note 4
Program/data area Note 3
01000H 00FFFH
Internal ROM (58,624 bytes)
00800H 007FFH 00080H 0007FH 00040H 0003FH 00000H 00000H
CALLF entry area (2 Kbytes)
20000H 1FFFFH
CALLT table area (64 bytes) Vector table area (64 bytes)
Internal ROM (128 Kbytes)
Note 4
00000H
Notes 1. Accessed in external memory expansion mode. 2. The 6,912 bytes of this area can be used as internal ROM only when the LOCATION 0FH instruction is executed. 3. 124,160 bytes when the LOCATION 0 instruction is executed, and 131,072 bytes when the LOCATION 0FH instruction is executed. 4. Base area, reset or interrupt entry area, excluding internal RAM in the case of reset.
Figure 3-3. PD784937 Memory Map
When location 0 instruction is executed
FFFFFH
When location 0FH instruction is executed
FFFFF FFFDF FFFD0 FFF00 FFEFF H H H H H
Special function registers (SFR)
Note 1
(256 bytes)
0FEFFH
FFEFFH
External memory (832 Kbytes)
0FE80H 0FE7FH
General-purpose registers (128 bytes)
FFE80H FFE7FH FDF00H FDEFFH
Internal RAM (8,192 bytes)
30000H 2FFFFH 10000H 0FFFFH 0FFDF 0FFD0 0FF00 0FEFF H H H H
Internal ROM (131,072 bytes)
Special function registers (SFRs)
Note 1
0FE39H 0FE06H
Macro service control word area (42 bytes) Data area (512 bytes)
FFE2FH FFE06H
(256 bytes)
0FD00H 0FCFFH
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FFD00H FFCFFH
Internal RAM (8,192 bytes)
0DF00H 0DEFFH 0DF00H
External memoryNote 1 (843,520 bytes)
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Program/data area (7,680 bytes)
FDF00H
2FFFFH 10000H
2FFFFH
Note 2
0DEFFH
Note 4
Program/data areaNote 3
30000H 2FFFFH
Internal ROM (57,088 bytes)
01000H 00FFFH
CALLF entry area (2 Kbytes)
00800H 007FFH 00080H 0007FH 00040H 0003FH
Internal ROM (192 Kbytes) CALLT table area (64 bytes) Vector table area (64 bytes)
Note 4
00000H
00000H
00000H
Notes 1. Accessed in external memory expansion mode. 2. The 8,488 bytes of this area can be used as internal ROM only when the LOCATION 0FH instruction is executed. 3. 188,160 bytes when the LOCATION 0 instruction is executed, and 196,608 bytes when the LOCATION 0FH instruction is executed. 4. Base area, reset or interrupt entry area, excluding internal RAM in the case of reset.
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FFFFFH
Figure 3-4. PD784938, 78F4938 Memory Map
When LOCATION 0 instruction is executed
When LOCATION 0FH instruction is executed
F F F F F H Special FFFDFH F F F D 0 H Note 1 FFF00H FFEFFH
function registers (SFRs) (256 bytes)
External memory Note 1 (832 Kbytes)
40000H 3FFFFH
0FEFFH
FFEFFH
General-purpose register (128 bytes)
0FE80H 0FE7FH FFE80H FFE7FH FD600H FD5FFH
Internal RAM (10,240 bytes)
Internal ROM (196,608 bytes)
10000H 0FFFFH Special 0FFDFH 0 F F D 0 H Note 1 0FF00H 0FEFFH
0FE39H
function registers (SFRs) (256 bytes)
0FE06H
Macro service control word area (42 bytes) Data area (512 bytes)
FFE39H FFE06H
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Internal RAM (10,240 bytes)
0D600H 0D5FFH
0FD00H 0FCFFH
FFD00H FFCFFH
Program/data area (9,728 bytes)
0D600H FD600H
External memory Note 1 (843,520 bytes)
3FFFFH 10000H
3FFFFH
Note 2
0DEFFH
Internal ROM (54,768 bytes)
Note 4
Program/data area
01000H 00FFFH
Note 3
40000H 3FFFFH
CALLF entry area (2 Kbytes)
00800H 007FFH 00080H 0007FH 00040H 0003FH
CALLT table area (64 bytes) Vector table area (64 bytes)
Internal ROM (256 Kbytes)
Note 4
00000H
00000H
00000H
Notes 1. Accessed in external memory expansion mode. 2. The 10,496 bytes of this area can be used as internal ROM only when the LOCATION 0FH instruction is executed. 3. 251,647 bytes when the LOCATION 0 instruction is executed, and 262,143 bytes when the LOCATION 0FH instruction is executed. 4. Base area, reset or interrupt entry area, excluding internal RAM in the case of reset. 5. In the case of PD78F4938: Flash memory
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3.2 Internal ROM Area The PD784938 Subseries products shown below incorporate ROM which is used to store programs, table data, etc. If the internal ROM area and internal data area overlap when the LOCATION 0 instruction is executed, the internal data area is accessed, and the overlapping part of the internal ROM area cannot be accessed.
Part Number
Internal ROM
Address Space LOCATION 0 Instruction LOCATION 0FH Instruction
PD784935 PD784936 PD784937 PD784938 PD78F4938
96 Kbytes x 8 bits 128 Kbytes x 8 bits 192 Kbytes x 8 bits 256 Kbytes x 8 bits
00000H to 0EAFFH 10000H to 17FFFH 00000H to 0E4FFH 10000H to 1FFFFH 00000H to 0DEFFH 10000H to 2FFFFH 00000H to 0D5FFH 10000H to 3FFFFH
00000H to 17FFFH
00000H to 1FFFFH
00000H to 2FFFFH
00000H to 3FFFFH
The internal ROM can be accessed at high speed. Normally, fetches are performed at the same speed as external ROM, but if the IFCH bit of the memory expansion mode register (MM) is set (to 1), the high-speed fetch function is used and internal ROM fetches are performed at high speed (2-byte fetch performed in 2 system clocks). When the instruction execution cycle equal to an external ROM fetch is selected, wait insertion is performed by the wait function, but when high-speed fetches are used, wait insertion is not performed for internal ROM. RESET input sets the instruction execution cycle equal to the external ROM fetch cycle.
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3.3 Base Area The space from 0 to FFFFH comprises the base area. The base area is the object for the following uses: * Reset entry address * Interrupt entry address * CALLT instruction entry address * 16-bit immediate addressing mode (with instruction address addressing) * 16-bit direct addressing mode * 16-bit register addressing mode (with instruction address addressing) * 16-bit register indirect addressing mode * Short direct 16-bit memory indirect addressing mode The vector table area, CALLT instruction table area and CALLF instruction entry area are allocated to the base area. When the LOCATION 0 instruction is executed, the internal data area is located in the base area. Note that, in the internal data area, program fetches cannot be performed from the internal high-speed RAM area or special function register (SFR) area. Also, internal RAM area data should only be used after initialization has been performed.
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3.3.1 Vector table area The 64-byte area from 00000H to 0003FH is reserved as the vector table area. The vector table area stores the program start addresses used when a branch is made as the result of RESET input or generation of an interrupt request. When context switching is used by an interrupt, the number of the register bank to be switched to is stored here. Any portion not used as the vector table can be used as program memory or data memory. 16-bit values can be written to the vector table. Therefore, branches can only be made within the base area. Table 3-1. Vector Table
Vector Table Address 0003CH 0003EH 00000H 00002H 00004H 00006H 00008H 0000AH 0000CH 0000EH 00010H 00012H 00014H 00016H 00018H 0001AH 0001CH 0001EH 00020H 00022H 00024H 00026H 00028H 0002AH 0002CH 0002EH 00032H 00034H 00036H 00038H Interrupt Source Operand error BRK Reset (RESET input) NMI WDT INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC20 INTC21 INTC30 INTP4 INTP5 INTAD INTSER1 INTSR1/INTCSI1 INTST1 INTCSI INTSER2 INTSR2/INTCSI2 INTST2 INTIE1 INTIE2 INTW INTCSI3
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3.3.2 CALLT instruction table area The 1-byte call instruction (CALLT) subroutine entry addresses can be stored in the 64-byte area from 00040H to 0007FH. The CALLT instruction references this table, and branches to a base area address written in the table as a subroutine. As the CALLT instruction is one byte in length, use of the CALLT instruction for subroutine calls written frequently throughout the program enables the program object size to be reduced. The table can contain up to 32 subroutine entry addresses, and therefore it is recommended that they be recorded in order of frequency. If this area is not used as the CALLT instruction table, it can be used as ordinary program memory or data memory. 3.3.3 CALLF instruction entry area A subroutine call can be made directly to the area from 00800H to 00FFFH with the 2-byte call instruction (CALLF). As the CALLF instruction is a two-byte call instruction, it enables the object size to be reduced compared with use of the direct subroutine call CALL instruction (3 or 4 bytes). Writing subroutines directly in this area is an effective means of exploiting the high-speed capability of the device. If you wish to reduce the object size, writing an unconditional branch (BR) instruction in this area and locating the subroutine itself outside this area will result in a reduced object size for subroutines that are called from five or more points. In this case, only the 4 bytes of the BR instruction are occupied in the CALLF entry area, enabling the object size to be reduced in a large number of subroutines.
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3.4 Internal Data Area The internal data area consists of the internal RAM area and special function register area (see Figures 3-1, 3-2, and 3-3). The final address of the internal data area can be specified by means of the LOCATION instruction as either 0FFFFH (when a LOCATION 0 instruction is executed) or FFFFFH (when a LOCATION 0FH instruction is executed). Selection of the addresses of the internal data area by means of the LOCATION instruction must be executed once immediately after reset release, and once the selection is made, it cannot be changed. The program after reset release must be as shown in the example below. If the internal data area and another area are allocated to the same addresses, the internal data area is accessed and the other area cannot be accessed. Example RSTVCT CSEG DW to INITSEG CSEG MOVG BASE SP, #STKBGN RSTSTRT: LOCATION 0H; or LOCATION 0FH AT 0 RSTSTRT
Caution When the LOCATION 0 instruction is executed, it is necessary to ensure that the program after reset release does not overlap the internal data area. It is also necessary to make sure that the entry addresses of the service routines for non-maskable interrupts such as NMI do not overlap the internal data area. Also, initialization must be performed for maskable interrupt entry areas, etc., before the internal data area is referenced.
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3.4.1 Internal RAM area The PD784938 incorporates general-purpose static RAM. This area is configured as follows: Peripheral RAM (PRAM) Internal RAM area Internal high-speed RAM (IRAM) Table 3-2. Internal RAM Area
Internal RAM Part Number Internal RAM Area Peripheral RAM: PRAM 5,120 bytes (0EB00H to 0FEFFH) 6,656 bytes (0E500H to 0FEFFH) 8,192 bytes (0DF00H to 0FEFFH) 10,240 bytes (0D600H to 0FEFFH) 4,608 bytes (0EB00H to 0FCFFH) 6,144 bytes (0E500H to 0FCFFH) 7,680 bytes (0DF00H to 0FCFFH) 9,728 bytes (0D600H to 0FCFFH) Internal High-Speed RAM: IRAM 512 bytes (0FD00H to 0FEFFH)
PD784935 PD784936 PD784937 PD784938 PD78F4938
Remark The addresses in the table are the values that apply when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown above.
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The internal RAM memory map is shown in Figure 3-5. Figure 3-5. Internal RAM Memory Map
00FEFFH
General-purpose register area 00FE80H Short direct addressing 1 permissible range 00FE39H Macro service control word area 00FE06H
00FE00H 00FDFFH
Internal high-speed RAM
Short direct addressing 2 permissible range 00FD20H 00FD1FH
00FD00H 00FCFFH
Peripheral RAM
Differs depending on productNote
Note
PD784935: PD784936: PD784937:
00EB00H 00E500H 00DF00H
PD784938, 78F4938: 00D600H
Remark The addresses in the figure are the values that apply when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown above.
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(1) Internal high-speed RAM (IRAM) The internal high-speed RAM (IRAM) allows high-speed accesses to be made. The short direct addressing mode for highspeed accesses can be used on FD20H to FEFFH in this area. There are two kinds of short direct addressing mode, short direct addressing 1 and short direct addressing 2, according to the target address. The function is the same in both of these addressing modes. With some instructions, the word length is shorter with short direct addressing 2 than with short direct addressing 1. See the 78K/IV Series User's Manual Instructions for details. A program fetch cannot be performed from IRAM. If a program fetch is performed from an address onto which IRAM is mapped, CPU inadvertent loop will result. The following areas are reserved in IRAM. * General-purpose register area: * Macro service channel area: FE80H to FEFFH FE00H to FEFFH (the address is specified by the macro service control word)
* Macro service control word area: FE06H to FE39H (excluding 0FE22H, 0FE23H, 0FE2AH, 0FE2BH, 0FE30H, 0FE31H)
If the reserved function is not used in these areas, they can be used as ordinary data memory. Remark The addresses in this text are those that apply when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown in the text. (2) Peripheral RAM (PRAM) The peripheral RAM (PRAM) is used as ordinary program memory or data memory. When used as program memory, the program must be written to the peripheral RAM beforehand by a program. Program fetches from peripheral RAM are fast, with a 2-byte fetch being executed in 2 clocks.
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3.4.2 Special function register (SFR) area The on-chip peripheral hardware special function registers (SFRs) are mapped onto the area from 0FF00H to 0FFFFH (see Figures 3-1, 3-2, 3-3, and 3-4). The area from 0FFD0H to 0FFDFH is mapped as an external SFR area, and allows externally connected peripheral I/Os, etc., to be accessed in external memory expansion mode (specified by the memory expansion mode register (MM)) by the ROMless product or on-chip ROM products. Caution Addresses onto which SFRs are not mapped should not be accessed in this area. If such an address is accessed by mistake, the CPU may become deadlocked. A deadlock can only be released by reset input. Remark The addresses in this text are those that apply when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown in the text. 3.4.3 External SFR area In PD784938 Subseries products, the 16-byte area from 0FFD0H to 0FFDFH in the SFR area (when the LOCATION 0 is executed; 0FFFD0H to 0FFFDFH when the LOCATION 0FH instruction is executed) is mapped as an external SFR area. When the external memory expansion mode is set in a ROM-less product or on-chip ROM product, externally connected peripheral I/Os, etc., can be accessed using the address bus or address/data bus, etc. As the external SFR area can be accessed by SFR addressing, peripheral I/O and similar operations can be performed easily, the object size can be reduced, and macro service can be used. Bus operations for accesses to the external SFR area are performed in the same way as for ordinary memory accesses. 3.5 External Memory Space The external memory space is a memory space that can be accessed in accordance with the setting of the memory expansion mode register (MM). It can store programs, table data, etc., and can have peripheral I/O devices allocated to it.
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3.6 PD78F4938 Memory Mapping The memory size switching register (IMS) specifies the internal memory size. With the PD78F4938, users are able to select the internal memory capacity using the IMS so that the same memory map as that of mask ROM versions with a different internal memory capacity can be achieved. The IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to FFH. Figure 3-6. Internal Memory Size Switching Register (IMS)
Address: 0FFFCCH 7 IMS 1 6 1 After reset: FFH 5 ROM1 4 ROM0 W/R 3 1 2 1 1 RAM1 0 RAM0
ROM1 0 0 1 1
ROM0 0 1 0 1
Internal ROM Capacity Selection 256 Kbytes 96 Kbytes 128 Kbytes 192 Kbytes
RAM1 0 0 1 1
RAM0 0 1 0 1
Internal RAM Capacity Selection 10,240 bytes 5,120 bytes 6,656 bytes 8,192 bytes
Caution The IMS is not contained in mask ROM products (PD784935, 784936, 784937, 784938). The IMS setting to obtain the same memory map as mask ROM products are shown in Table 3-3. Table 3-3. Internal Memory Size Switching Register (IMS) Setting Value
Mask ROM Product IMS Setting Value DDH EEH FFH CCH
PD784935 PD784936 PD784937 PD784938
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3.7 Control Registers Control registers consist of the program counter (PC), program status word (PSW), and stack pointer (SP). 3.7.1 Program counter (PC) This is a 20-bit binary counter that holds address information on the next program to be executed (see Figure 3-7). Normally, the PC is incremented automatically by the number of bytes in the fetched instruction. When an instruction associated with a branch is executed, the immediate data or register contents are set in the PC. Upon RESET input, the 16-bit data in address 0 and 1 is set in the low-order 16 bits, and 0000 in the high-order 4 bits of the PC. Figure 3-7. Program Counter (PC) Format
19 PC 0
3.7.2 Program status word (PSW) The program status word (PSW) is a 16-bit register comprising various flags that are set or reset according to the result of instruction execution. Read accesses and write accesses are performed in high-order 8-bit (PSWH) and low-order 8-bit (PSWL) units. Individual flags can be manipulated by bit-manipulation instructions. The contents of the PSW are automatically saved to the stack when a vectored interrupt request is acknowledged or a BRK instruction is executed, and automatically restored when an RETI or RETB instruction is executed. When context switching is used, the contents are automatically saved in RP3, and automatically restored when an RETCS or RETCSB instruction is executed. RESET input resets (to 0) all bits. "0" must always be written to the bits written as "0" in Figure 3-8. The contents of bits written as "-" are undefined when read. Figure 3-8. Program Status Word (PSW) Format
Symbol PSWH 7 UF 6 RBS2 5 RBS1 4 RBS0 3 - 2 - 1 - 0 -
7 PSWL S
6 Z
5 RSS
4 AC
3 IE
2 P/V
1 0
0 CY
The flags are described below. (1) Carry flag (CY) The carry flag records a carry or borrow resulting from an operation. This flag also records the shifted-out value when a shift/rotate instruction is executed, and functions as a bit accumulator when a bit-manipulation instruction is executed. The status of the CY flag can be tested with a conditional branch instruction.
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(2) Parity/overflow flag (P/V) The P/V flag performs the following two kinds of operation associated with execution of an operation instruction. The status of the P/V flag can be tested with a conditional branch instruction. * Parity flag operation Set (to 1) when the number of bits set (to 1) as the result of execution of a logical operation instruction, shift/rotate instruction, or a CHKL or CHKLA instruction is even, and reset (to 0) if odd. When a 16-bit shift instruction is executed, however, only the low-order 8 bits of the operation result are valid for the parity flag. * Overflow flag operation Set (1) only when the numeric range expressed as a two's complement is exceeded as the result of execution of a arithmetic operation instruction, and reset (to 0) otherwise. More specifically, the value of this flag is the exclusive OR of the carry into the MSB and the carry out of the MSB. For example, the two's complement range in an 8-bit arithmetic operation is 80H (-128) to 7FH (+127), and the flag is set (to 1) if the operation result is outside this range, and reset (to 0) if within this range. Example The operation of the overflow flag when an 8-bit addition instruction is executed is shown below. When the addition of 78H (+120) and 69H (+105) is performed, the operation result is E1H (+225), and the two's complement limit is exceeded, with the result that the P/V flag is set (to 1). Expressed as a two's complement, E1H is -31. 78H (+120) +) 69H (+105) = 0 CY When the following two negative numbers are added together, the operation result is within the two's complement range, and therefore the P/V flag is reset (to 0). FBH (-5) +) F0H (-16) = 1 CY (3) Interrupt request enable flag (IE) This flag controls CPU interrupt request acknowledgment operations. When "0", interrupts are disabled, and only non-maskable interrupts and unmasked macro service can be acknowledged. All other interrupts are disabled. When "1", the interrupt enabled state is set, and enabling of interrupt request acknowledgment is controlled by the interrupt mask flags corresponding to the individual interrupt requests and the priority of the individual interrupts. The IE flag is set (to 1) by execution of an EI instruction, and reset (to 0) by execution of a DI instruction or acknowledgment of an interrupt. 1111 1110 1011 0000 1011 = -21 P/V = 0 0111 1110 1000 1001 0001 = -31 P/V = 1
= +) 0110
= +) 1111
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(4) Auxiliary carry flag (AC) The AC flag is set (to 1) when there is a carry out of bit 3 or a borrow into bit 3 as the result of an operation, and reset (to 0) otherwise. This flag is used when the ADJBA or ADJBS instruction is executed. (5) Register set selection flag (RSS) The RSS flag specifies the general-purpose registers that function as X, A, C, and B, and the general-purpose register pairs (16-bit) that function as AX and BC. This flag is provided to maintain compatibility with the 78K/III Series, and must be set to 0 except when using a 78K/III Series program. (6) Zero flag (Z) The Z flag records the fact that the result of an operation is "0". It is set (to 1) when the result of an operation is "0", and reset (to 0) otherwise. The status of the Z flag can be tested with a conditional branch instruction. (7) Sign flag (S) The S flag records the fact that the MSB is "1" as the result of an operation. It is set (to 1) when the MSB is "1" as the result of an operation, and reset (to 0) otherwise. The status of the S flag can be tested with a conditional branch instruction. (8) Register bank selection flag (RBS0 to RBS2) This is a 3-bit flag used to select one of the 8 register banks (register bank 0 to register bank 7) (see Table 3-4). It stores 3-bit information which indicates the register bank selected by execution of a SEL RBn instruction, etc. Table 3-4. Register Bank Selection
RBS2 0 0 0 0 1 1 1 1 RBS1 0 0 1 1 0 0 1 1 RBS0 0 1 0 1 0 1 0 1 Specified Register Bank Register bank 0 Register bank 1 Register bank 2 Register bank 3 Register bank 4 Register bank 5 Register bank 6 Register bank 7
(9) User flag (UF) This flag can be set and reset in the user program, and used for program control.
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3.7.3 Use of RSS bit Basically, the RSS bit should be fixed at 0 at all times. The following explanation refers to the case where a 78K/III Series program is used, and the program used sets the RSS bit to 1. This explanation can be skipped if the RSS bit is fixed at 0. The RSS bit is provided to allow the functions of A (R1), X (R0), B (R3), C (R2), AX (RP0), and BC (RP1) to be used by registers R4 to R7 (RP2, RP3) as well. Effective use of this bit enables efficient programs to be written in terms of program size and program execution. However, careless use can result in unforeseen problems. Therefore, the RSS bit should always be set to 0. The RSS bit should only be set to 1 when a 78K/III Series program is used. Use of the RSS bit set to 0 in all programs will improve programming and debugging efficiency. Even when using a program in which the RSS bit set to 1 is used, it is recommended that the program be amended if possible so that it does not set the RSS bit to 1. (1) RSS bit specification * Registers used by instructions for which the A, X, B, C, and AX registers are directly entered in the operand column of the operation list (see 28.2) * Registers specified as implied by instructions that use the A, AX, B, and C registers by means of implied addressing * Registers used in addressing by instructions that use the A, B, and C registers in indexed addressing and based indexed addressing The registers used in these cases are switched as follows according to the RSS bit.
*
When RSS = 0 AR1, XR0, BR3, CR2, AXRP0, BCRP1
*
When RSS = 1 AR5, XR4, BR7, CR6, AXRP2, BCRP3
Registers used other than those mentioned above are always the same irrespective of the value of the RSS bit. With the NEC assembler (RA78K4), the register operation code generated when the A, X, B, C, AX, and BC registers are described by those names is determined by the assembler RSS pseudo-instruction. When the RSS bit is set or reset, an RSS pseudo-instruction must be written immediately before (or immediately after) the relevant instruction (see example below). * When RSS is set to 0 RSS 0 CLR1 PSWL. 5 MOV B, A ; This description is equivalent to "MOV R3, R1". ; RSS pseudo-instruction
* When RSS is set to 1 RSS 1 SET1 PSWL. 5 MOV B, A ; This description is equivalent to "MOV R7, R5".
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(2) Operation code generation method with RA78K4 * With RA78K4, if there is an instruction with the same function as an instruction for which A or AX is directly entered in the operand column of the instruction operation list, the operation code for which A or AX is directly entered in the operand column is generated first. Example The function is the same when B is used as r in a MOV A,r instruction, and when A is used as r and B is used as r' in a MOVr,r' instruction, and the same description (MOV,A,B) is used in the assembler source program. In this case, RA78K4 generates code equivalent to the MOV A, r instruction. * If A, X, B, C, AX, or BC is written in an instruction for which r, r', rp, and rp' are specified in the operand column, the A, X, B, C, AX, and BC instructions generate an operation code that specifies the following registers according to the operand of the RA78K4 RSS pseudo-instruction.
Register A X B C AX BC
RSS = 0 R1 R0 R3 R2 RP0 RP1
RSS = 1 R5 R4 R7 R6 RP2 RP3
* If R0 to R7 or RP0 to RP4 is written as r, r', rp, or rp' in the operand column, an operation code in accordance with that specification is output (an operation code for which A or AX is directly entered in the operand column is not output.) * Descriptions R1, R3, R2 or R5, R7, R6 cannot be used for registers A, B, and C used in indexed addressing and based indexed addressing. (3) Operating precautions Switching the RSS bit has the same effect as having two register sets. However, when writing a program, care must be taken to ensure that the static program description and dynamic RSS bit changes at the time of program execution always coincide. Also, a program that sets RSS to 1 cannot be used by a program that uses the context switching function, and therefore program usability is poor. Moreover, since different registers are used with the same name, program readability is poor and debugging is difficult. Therefore, if it is necessary to set RSS to 1, these disadvantages must be fully taken into consideration when writing a program. A register not specified by the RSS bit can be accessed by writing its absolute name.
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3.7.4 Stack pointer (SP) The stack pointer is a 24-bit register that holds the start address of the stack area (LIFO type: 00000H to FFFFFFH) (see Figure 3-9). It is used to address the stack area when subroutine processing or interrupt servicing is performed. Be sure to write "0" in the high-order 4 bits. The contents of the SP are decremented before a write to the stack area and incremented after a read from the stack area (see Figures 3-10 and 3-11). The SP is accessed by dedicated instructions. The SP contents are undefined after RESET input, and therefore the SP must always be initialized by an initialization program directly after reset release (before a subroutine call or interrupt acknowledgment). Example SP initialization MOVG SP, #0FEE0H;SP 0FEE0H (when used from FEDFH) Figure 3-9. Stack Pointer (SP) Format
23 SP 0
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Figure 3-10. Data Saved to Stack Area
PUSH sfr instruction stack SP SP- 1 SPSP- 1 SP SP- 1 SP- 2 SPSP- 2 PUSH sfrp instruction stack
Upper byte Lower byte
PUSH PSW instruction stack SP SP- 1 SP- 2 SPSP- 2 SP SP- 1 SP- 2 SP- 3 SPSP- 3
PUSH rg instruction stack
PSWH7 to Undefined PSWH4 PSWL
Upper byte Middle byte Lower byte
CALL, CALLF, CALLT instruction stack SP SP- 1 Undefined PC19 to PC16 SP- 2 PC15 to PC8 SP- 3 PC7 to PC0 SPSP- 3 SP SP- 1 SP- 2 SP- 3 SP- 4 SPSP- 4
Vectored interrupt stack
PUSH post, PUSHU post instruction (in case of PUSH AX, RP2, RP3) stack SP SP- 1 SP- 2 SP- 3 SP- 4 SP- 5 SP- 6 SPSP- 6
PSWH7 to PC19 to PSWH4 PC16 PSWL PC15 to PC8 PC7 to PC0
R7 R6 R5 R4 A X
RP3 RP2 AX
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Figure 3-11. Data Restored from Stack Area
POP sfr instruction stack SPSP+1 SP+1 SP SPSP+2 SP+1 SP
POP sfrp instruction stack
Upper byte Lower byte
POP PSW instruction stack SPSP+2 SP+1 PSWH7 to -Note PSWH4 SP PSWL SPSP+3 SP+2 SP+1 SP
POP rg instruction stack
Upper byte Middle byte Lower byte
RET instruction stack SPSP+3 SP+2 SP+1 SP -
Note
RETI, RETB instruction stack SPSP+4
POP post, POPU post instruction (In case of POP AX, RP2, RP3) stack SPSP+6 SP+5 SP+4 SP+3 SP+2 SP+1 SP R7 R6 R5 R4 A X
PC19 to PC16
PC15 to PC8 PC7 to PC0
PSWH7 to PC19 to SP+3 PSWH4 PC16 PSWL SP+2 PC15 to PC8 SP+1 PC7 to PC0 SP
RP3 RP2 AX
Note
This 4-bit data is ignored.
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Cautions 1. With stack addressing, the entire 1-Mbyte space can be accessed but a stack area cannot be reserved in the SFR area or internal ROM area. 2. The stack pointer (SP) is undefined after RESET input. Moreover, non-maskable interrupts can still be acknowledged when the SP is in an undefined state. An unanticipated operation may therefore be performed if a non-maskable interrupt request is generated when the SP is in the undefined state directly after reset release. To avoid this risk, the program after reset release must be written as follows. RSTVCT CSEG DW to INITSEG CSEG BASE RSTSTRT : LOCATION 0H ; or LOCATION 0FH MOVG SP, #STKBGN AT 0
RSTSTRT
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3.8 General- Purpose Registers 3.8.1 Configuration There are sixteen 8-bit general-purpose registers, and two 8-bit general-purpose registers can be used together as a 16-bit general-purpose register. In addition, four of the 16-bit general-purpose registers can be combined with an 8-bit register for address extension, and used as 24-bit address specification registers. General-purpose registers other than the V, U, T, and W registers for address extension are mapped onto internal RAM. These register sets are provided in 8 banks, and can be switched by means of software or the context switching function. Upon RESET input, register bank 0 is selected. The register bank used during program execution can be checked by reading the register bank selection flag (RBS0, RBS1, RBS2) in the PSW. Figure 3-12. General-Purpose Register Format
7 A (R1)
07 X (R0) AX (RP0) B (R3) BC (RP1) R5 RP2 R7 RP3 R6 R4 C (R2)
0
V VVP (RG4) U UUP (RG5) T
R9 VP (RP4) R11 UP (RP5) D (R13) DE (RP6) TDE (RG6)
R8
R10
E (R12)
W
H (R15) HL (RP7) WHL (RG7)
L (R14) 8 banks
23
15
0
Remark Absolute names are shown in parentheses.
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Figure 3-13. General-Purpose Register Addresses
8-bit processing FEFFHNote RBNK0 RBNK1 RBNK2 RBNK3 RBNK4 RBNK5 RBNK6 FE80HNote RBNK7 7 H (R15) (FH) D (R13) (DH) R11(BH) R9 (9H) R7 (7H) R5 (5H) B (R3) (3H) A (R1) (1H) 07 L (R14) (EH) E (R12) (CH) R10 (AH) R8 (8H) R6 (6H) R4 (4H) C (R2) (2H) X (R0) (0H) 0 15
16-bit processing HL (RP7) (EH) DE (RP6) (CH) UP (RP5) (AH) VP (RP4) (8H) RP3 (6H) RP2 (4H) BC (RP1) (2H) AX (RP0) (0H) 0
Note
When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H should be added to the address values shown above.
Caution R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers respectively by setting the RSS bit of the PSW to 1, but this function should only be used when using a 78K/III Series program. Remark When the register bank is changed, and it is necessary to return to the original register bank, an SEL RBn instruction should be executed after saving the PSW to the stack with a PUSH PSW instruction. When returning to the original register bank, if the stack location does not change the POP PSW instruction should be used. When the register bank is changed by a vectored interrupt service program, etc., the PSW is automatically saved to the stack when an interrupt is acknowledged and restored by an RETI or RETB instruction, so that, if only one register bank is used in the interrupt service routine, only an SEL RBn instruction needs be executed, and execution of a PUSH PSW and POP PSW instruction is not necessary. Example When register bank 2 is specified
PUSH PSW SEL RB2
Operations in register bank 2 POP PSW
......
......
......
Operations in original register bank
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3.8.2 Functions In addition to being manipulated in 8-bit units, the general-purpose registers can also be manipulated in 16-bit units by pairing two 8-bit registers. Also, four of the 16-bit registers can be combined with an 8-bit register for address extension and manipulated in 24-bit units. Each register can be used in a general-purpose way for temporary storage of an operation result and as the operand of an inter-register operation instruction. The area from 0FE80H to 0FEFFH (when the LOCATION 0 instruction is executed; 0FFE80H to 0FFEFFH when the LOCATION 0FH instruction is executed) can be given an address specification and accessed as ordinary data memory irrespective of whether or not it is used as the general-purpose register area. As 8 register banks are provided in the 78K/IV Series, efficient programs can be written by using different register banks for normal processing and processing in the event of an interrupt. The registers have the following specific functions. A (R1): * Register mainly used for 8-bit data transfers and operation processing. Can be used in combination with all addressing modes for 8-bit data. * Can also be used for bit data storage. * Can be used as the register that stores the offset value in indexed addressing and based indexed addressing. X (R0): * Can be used for bit data storage. AX (RP0): * Register mainly used for 16-bit data transfers and operation processing. Can be used in combination with all addressing modes for 16-bit data. AXDE: * Used for 32-bit data storage when a DIVUX, MACW, or MACSW instruction is executed. B (R3): * Has a loop counter function, and can be used by the DBNZ instruction. * Can be used as the register that stores the offset value in indexed addressing and based indexed addressing. * Used as the MACW and MACSW instruction data pointer. C (R2): * Has a loop counter function, and can be used by the DBNZ instruction. * Can be used as the register that stores the offset value in based indexed addressing. * Used as the counter in a string instruction and the SACW instruction. * Used as the MACW and MACSW instruction data pointer. RP2: * Used to save the low-order 16 bits of the program counter (PC) when context switching is used. RP3: * Used to save the high-order 4 bits of the program counter (PC) and the program status word (PSW) (excluding bits 0 to 3 of PSWH) when context switching is used.
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VVP (RG4): * Has a pointer function, and operates as the register that specifies the base address in register indirect addressing, based addressing and based indexed addressing. UUP (RG5): * Has a user stack pointer function, and enables a stack separate from the system stack to be implemented by means of the PUSHU and POPU instructions. * Has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. DE (RP6), HL (RP7): * Operate as the registers that store the offset value in indexed addressing and based indexed addressing. TDE (RG6): * Has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. * Used as the pointer in a string instruction and the SACW instruction. WHL (RG7): * Register used mainly for 24-bit data transfers and operation processing. * Has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. * Used as the pointer in a string instruction and the SACW instruction.
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In addition to the function name that emphasizes the specific function of the register (X, A, C, B, E, D, L, H, AX, BC, VP, UP, DE, HL, VVP, UUP, TDE, WHL), each register can also be described by its absolute name (R0 to R15, RP0 to RP7, RG4 to RG7). The correspondence between these names is shown in Table 3-5. Table 3-5. Correspondence between Function Names and Absolute Names (a) 8-bit registers
Absolute Name Function Name RSS = 0 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 E D L H E D L H X A C B X A C B RSS = 1Note RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 VP UP DE HL
(b) 16-bit registers
Absolute Name Function Name RSS = 0 AX BC AX BC VP UP DE HL RSS = 1Note
(c) 24-bit registers
Absolute Name RG4 RG5 RG6 RG7 Function Name VVP UUP TDE WHL
Note RSS should only be set to 1 when a 78K/III Series program is used. Remark R8 to R11 have no function name.
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3.9 Special Function Registers (SFR) These are registers to which a special function is assigned, such as on-chip peripheral hardware mode registers, control registers, etc. They are mapped onto the 256-byte space from 0FF00H to 0FFFFHNote. Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, the area is FFF00H to FFFFFH. Caution Addresses onto which SFRs are not assigned should not be accessed in this area. If such an address is as accessed by mistake, the PD784938 may become deadlocked. A deadlock can only be released by reset input. A list of special function registers (SFRs) is given in Table 3-6. The meaning of the items in the table is as explained below. * Symbol ............................... Symbol that indicates the incorporated SFR. This is a reserved word in the NEC assembler (RA78K4). With the C compiler (CC78K4), this symbol can be used as an sfr variable by means of a #pragma sfr command. * R/W .................................... Indicates whether the corresponding SFR is read/write enabled. R/W: Read/write enabled R: W: Read-only Write-only
* Manipulable Bit Units ......... Indicates the applicable manipulation bit units when the corresponding SFR is manipulated. A 16-bit-manipulable SFR can be written in the operand "sfrp", and when specified by an address, an even address is specified. A bit-manipulable SFR can be written in a bit manipulation instruction. * After Reset ......................... Indicates the status of the register after RESET input.
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Table 3-6. List of Special Function Registers (SFRs) (1/5)
AddressNote Special Function Register (SFR) Name Symbol R/W Manipulable Bit Units 1 Bit 0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF09H 0FF0AH 0FF0EH 0FF0FH 0FF10H 0FF12H 0FF14H 0FF15H 0FF16H 0FF17H 0FF18H 0FF19H 0FF1AH 0FF1BH 0FF1CH 0FF1DH 0FF20H 0FF21H 0FF23H 0FF24H 0FF25H 0FF26H 0FF27H 0FF29H 0FF2AH 0FF2EH 0FF30H Port 0 buffer register H Compare register (timer/event counter 0) Capture/compare register (timer/event counter 0) Compare register L (timer/event counter 1) Compare register H (timer/event counter 1) Capture/compare register L (timer/event counter 1) Capture/compare register H (timer/event counter 1) Compare register L (timer/event counter 2) Compare register H (timer/event counter 2) Capture/compare register L (timer/event counter 2) Capture/compare register H (timer/event counter 2) Compare register L (timer 3) Compare register H (timer 3) Port 0 mode register Port 1 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 7 mode register Port 9 mode register Port 10 mode register Real-time output port control register Capture/compare control register 0 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 9 Port 10 Port 0 buffer register P0 P1 P2 P3 P4 P5 P6 P7 P9 P10 P0L P0H CR00 CR01 CR10 -- CR11 -- CR20 -- CR21 -- CR30 -- PM0 PM1 PM3 PM4 PM5 PM6 PM7 PM9 PM10 RTPC CRC0 CR30W CR21W CR20W CR11W CR10W R R/W R/W -- -- -- -- -- -- -- -- -- -- -- -- -- 8 Bits 16 Bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 00H 10H FFH -- -- -- -- -- -- -- -- -- -- -- -- 00H Undefined Undefined After Reset
Note
When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, "F0000H" should be added to the value shown.
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Table 3-6. List of Special Function Registers (SFRs) (2/5)
AddressNote Special Function Register (SFR) Name Symbol R/W Manipulable Bit Units 1 Bit 0FF31H 0FF32H 0FF33H 0FF36H 0FF38H 0FF39H 0FF3AH 0FF3BH 0FF41H 0FF43H 0FF4AH 0FF4EH 0FF4FH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF5CH 0FF5DH 0FF5EH 0FF5FH 0FF68H 0FF6AH 0FF6CH 0FF6FH 0FF70H 0FF71H 0FF72H 0FF74H 0FF78H 0FF79H 0FF7AH Prescaler mode register 0 Timer control register 0 Prescaler mode register 1 Timer control register 1 A/D converter mode register A/D conversion result register A/D current cut select register Watch timer mode register PWM control register PWM prescaler register PWM modulo register 0 PWM modulo register 1 ROM correction control register ROM correction address register H ROM correction address register L Timer counter 3 Timer counter 2 Timer counter 1 TM1 -- TM2 -- TM3 -- PRM0 TMC0 PRM1W TMC1 ADM ADCR IEAD WM PWMC PWPR PWM0 PWM1 CORC CORAH CORAL R R/W R/W TM3W TM2W TM1W Timer output control register Capture/compare control register 1 Capture/compare control register 2 Capture register (timer/event counter 0) Capture register L (timer/event counter 1) Capture register H (timer/event counter 1) Capture register L (timer/event counter 2) Capture register H (timer/event counter 2) Port 1 mode control register Port 3 mode control register Port 10 mode control register Pull-up resistor option register L Pull-up resistor option register H Timer counter 0 TOC CRC1 CRC2 CR02 CR12 -- CR22 -- PMC1 PMC3 PMC10 PUOL PUOH TM0 R R/W CR22W CR12W R R/W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 Bits 16 Bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000H 00H 05H 00H Undefined Undefined 00H 11H 00H 11H 00H -- -- -- -- -- 0000H 00H -- -- -- 10H 0000H 00H After Reset
Note
When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, "F0000H" should be added to the value shown.
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Table 3-6. List of Special Function Registers (SFRs) (3/5)
AddressNote Special Function Register (SFR) Name Symbol R/W Manipulable Bit Units 1 Bit 0FF7DH 0FF80H 0FF82H 0FF84H 0FF85H 0FF86H 0FF88H 0FF89H 0FF8AH 0FF8BH 0FF8CH One-shot pulse output control register Clocked serial interface mode register 3 Clocked serial interface mode register Clocked serial interface mode register 1 Clocked serial interface mode register 2 Serial shift register Asynchronous serial interface mode register Asynchronous serial interface mode register 2 Asynchronous serial interface status register Asynchronous serial interface status register 2 Serial receive buffer: UART0 Serial transmit shift register: UART0 Serial shift register: IOE1 0FF8DH Serial receive buffer: UART2 Serial transmit shift register: UART2 Serial shift register: IOE2 0FF8EH 0FF90H 0FF91H 0FFA0H 0FFA1H 0FFA4H 0FFA8H 0FFAAH Serial shift register: IOE3 Baud rate generator control register Baud rate generator control register 2 External interrupt mode register 0 External interrupt mode register 1 Sampling clock selection register In-service priority register Interrupt mode control register OSPC CSIM3 CSIM CSIM1 CSIM2 SIO ASIM ASIM2 ASIS ASIS2 RXB TXS SIO1 RXB2 TXS2 SIO2 SIO3 BRGC BRGC2 INTM0 INTM1 SCS0 ISPR IMC MK0L MK0H MK1L MK1H BCR UAR SAR PAR CDR DLR DR USR ISR R R/W R R/W MK1 MK0 R R/W W R/W R W R/W R R/W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 Bits 16 Bits -- -- -- -- -- -- -- -- -- 00H 01H 00H 0000H -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80H FFFFH 00H Undefined Undefined 00H 00H After Reset
0FFACH Interrupt mask register 0L 0FFADH Interrupt mask register 0H 0FFAEH 0FFAFH 0FFB0H 0FFB2H 0FFB4H 0FFB6H 0FFB8H 0FFB9H 0FFBAH 0FFBBH Interrupt mask register 1L Interrupt mask register 1H Bus control register Unit address register Slave address register Partner address register Control data register Telegraph length register Data register Unit status register
0FFBCH Interrupt status register
Note
When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, "F0000H" should be added to the value shown.
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Table 3-6. List of Special Function Registers (SFRs) (4/5)
AddressNote 1 Special Function Register (SFR) Name Symbol R/W Manipulable Bit Units 1 Bit 0FFBDH Slave status register 0FFBEH 0FFBFH 0FFC0H 0FFC2H 0FFC4H 0FFC5H 0FFC6H 0FFC7H 0FFC8H Success count register Communication count register Standby control register Watchdog timer mode register Memory expansion mode register Hold mode register Clock output mode register Programmable wait control register 1 Programmable wait control register 2 SSR SCR CCR STBC WDM MM HLDM CLOM PWC1 PWC2 RFM RFA OSTS -- R/W R -- -- -- -- -- -- -- 8 Bits 16 Bits Note 2 Note 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AAH AAAAH 00H 41H 01H 20H 30H 00H 20H 00H After Reset
0FFCCH Refresh mode register 0FFCDH Refresh area specification register 0FFCFH Oscillation stabilization time specification register
0FFD0H to External SFR area 0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTC00) Interrupt control register (INTC01) Interrupt control register (INTC10) Interrupt control register (INTC11) Interrupt control register (INTC20) Interrupt control register (INTC21) Interrupt control register (INTC30) Interrupt control register (INTP4)
PIC0 PIC1 PIC2 PIC3 CIC00 CIC01 CIC10 CIC11 CIC20 CIC21 CIC30 PIC4 PIC5 ADIC SERIC SRIC CSIIC1 STIC CSIIC SERIC2
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
43H
0FFECH Interrupt control register (INTP5) 0FFEDH Interrupt control register (INTAD) 0FFEEH 0FFEFH Interrupt control register (INTSER) Interrupt control register (INTSR) Interrupt control register (INTCSI1) 0FFF0H 0FFF1H 0FFF2H Interrupt control register (INTST) Interrupt control register (INTCSI) Interrupt control register (INTSER2)
Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, "F0000H" should be added to the value shown. 2. The write operation is possible by using the dedicated instruction "MOV STBC, #byte" or "MOV WDM, #byte" only. Instructions other than these cannot perform the write operation.
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Table 3-6. List of Special Function Registers (SFRs) (5/5)
AddressNote 1 Special Function Register (SFR) Name Symbol R/W Manipulable Bit Units 1 Bit 0FFF3H Interrupt control register (INTSR2) Interrupt control register (INTCSI2) 0FFF4H 0FFF6H 0FFF7H 0FFF8H 0FFF9H 0FFFCH Interrupt control register (INTST2) Interrupt control register (INTIE1) Interrupt control register (INTIE2) Interrupt control register (INTW) Interrupt control register (INTCSI3) Internal memory size switching registerNote 2 SRIC2 CSIIC2 STIC2 IEIC1 IEIC2 WIC CSIIC3 IMS R/W -- 8 Bits 16 Bits -- -- -- -- -- -- -- -- FFH 43H After Reset
Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, "F0000H" should be added to the value shown. 2. Writes to this register are only meaningful in the case of the PD78F4938.
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3.10 Cautions (1) Program fetches cannot be performed from the internal high-speed RAM area (0FD00H to 0FEFFH when the LOCATION 0 instruction is executed; FFD00H to FFEFFH when the LOCATION 0FH instruction is executed). (2) Special function registers (SFRs) Addresses onto which SFRs are not assigned should not be accessed in the area 0FF00H to 0FFFFHNote. If such an address is accessed by mistake, the PD784938 may become deadlocked. A deadlock can only be released by reset input. Note When the LOCATION 0 instruction is executed; FFF00H to FFFFFH when the LOCATION 0FH instruction is executed. (3) Stack pointer (SP) operation With stack addressing, the entire 1-Mbyte space can be accessed, but a stack area cannot be reserved in the SFR area or internal ROM area. (4) Stack pointer (SP) initialization The SP is undefined after RESET input, while non-maskable interrupts can be acknowledged directly after reset release. Therefore, an unforeseen operation may be performed if a non-maskable interrupt request is generated while the SP is in the undefined state directly after reset release. To minimize this risk, the following program should be coded without fail after reset release. RSTVCT CSEG DW to INITSEG RSTSTRT : CSEG BASE LOCATION 0H ; or LOCATION 0FH MOVG SP, #STKBGN AT 0 RSTSTRT
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4.1 Configuration and Function The clock generator generates and controls the internal clock and internal system clock supplied to the CPU and on-chip hardware. The clock generator block diagram is shown in Figure 4-1. Figure 4-1. Clock Generator Block Diagram
Internal bus
OSTS EXTC OSTS2 OSTS1 OSTS0 RESET SELOSC CK1 CK0 STP
STBC HLT RESET
X1 Clock oscillator X2 fXX
Frequency divider
fXX
Selector
fXX/2 fXX/4 fXX/8
fCLK
Internal system clock (CPU, watchdog timer, noise elimination circuit, A/D, PWM, interrupts, local bus interface) Internal clock (UART/IOE, CSI, noise elimination circuit, timer/counters, oscillation stabilization timer)
fXX Clock supplied to watch timer when the main clock selected (WM6 = 0)
Selector
1/2 divider SELOSC = 1
IEBus
Remark fXX: Crystal/ceramic oscillation frequency or internal clock frequency fCLK: Internal system clock frequency The clock oscillator oscillates by means of a crystal resonator/ceramic resonator connected to the X1 and X2 pins. When standby mode (STOP) is set, oscillation stops (see CHAPTER 25 STANDBY FUNCTION). It is also possible to input an external clock. In this case, the clock signal is input to the X1 pin, and the inverse phase signal to the X2 pin. The frequency divider generates an internal system clock by 1/1, 1/2, 1/4, or 1/8 scaling of the clock oscillator output (fXX) according to the setting of the standby control register (STBC).
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Figure 4-2. Clock Oscillator External Circuitry (a) Crystal/ceramic oscillation
PD784938
VSS X1
X2
(b) External clock EXTC bit of OSTS = 1
PD784938
X1
EXTC bit of OSTS = 0
PD784938
X1
PD74HC04, etc.
X2
Open
X2
Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins. 2. No other signal lines should pass through the area enclosed by the dotted line. Remark Differences between crystal resonator and ceramic resonator Generally speaking, the oscillation frequency of a crystal resonator is extremely stable. It is therefore ideal for performing high-precision time management (in clocks, frequency meters, etc.). A ceramic resonator is inferior to a crystal resonator in terms of oscillation frequency stability, but it has three advantages: a fast oscillation start-up time, small size, and low price. It is therefore suitable for general use (when high-precision time management is not required). In addition, there are products with a built-in capacitor, etc., which enable the number of parts and mounting area to be reduced.
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4.2 Control Registers 4.2.1 Standby control register (STBC) STBC is a register used to set the standby mode and select the internal system clock. See CHAPTER 25 STANDBY FUNCTION for details of the standby modes. To prevent erroneous entry into standby mode due to an inadvertent program loop, the STBC register can only be written to by a dedicated instruction. This instruction is the MOV STBC, #byte instruction, and has a special code configuration (4 bytes). A write is only performed if the 3rd and 4th bytes of the op code are mutual complements. If the 3rd and 4th bytes of the op code are not mutual complements, a write is not performed, and an operand error interrupt is generated. In this case, the return address saved in the stack area is the address of the instruction which is the source of the error. The error source address can thus be found from the return address saved on the stack area. An endless loop will result if restore from an operand error is simply performed with an RETB instruction. Because the operand error interrupt occurs only when the program hangs up (only the correct dedicated instruction is generated with the NEC's assembler RA78K4 when MOV STBC, #byte is described), make sure that the operand error interrupt processing program initializes the system. Other write instructions ("MOV STBC, A", "AND STBC, #byte", "SET1 STBC.7", etc.) are ignored, and no operation is performed. That is, a write is not performed on the STBC, and an interrupt such as an operand error interrupt is not generated. STBC can be read at any time with a data transfer instruction. RESET input sets STBC to 30H. The format of STBC is shown in Figure 4-3.
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Figure 4-3. Standby Control Register (STBC) Format
7 STBC SELOSC 6 0 5 CK1 4 CK0 3 x 2 0 1 STP 0 HLT Address 0FFC0H After reset 30H R/W R/W
STP 0 0 1 1
HLT 0 1 0 1
Operating Mode Normal mode HALT mode STOP mode IDLE mode (fXX = 12.58 MHz)
CK1 0 0 1 1 SELOSC 0 1
CK0 0 1 0 1
Internal System Clock Selection fXX (12.58 MHz)
fXX/2 (6.29 MHz) fXX/4 (3.15 MHz) fXX/8 (1.57 kHz) Oscillation Frequency Control
6.29 MHz 12.58 MHz
Cautions 1. Overwrite the SELOSC bit after performing the following settings. * Stop the IEBus (Set bit 7 of the bus control register (BCR) to "0"). * If the watch Timer is operated with the main clock selected, stop the watch timer (Set bit 3 of the watch timer mode register (WM) to "0"). 2. If the above settings are not performed, the IEBus and watch timer may perform incorrectly.
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4.2.2 Oscillation stabilization time specification register (OSTS) OSTS is a register used to select the oscillation stabilization time. OSTS can be written to only by an 8-bit transfer instruction. RESET input clears OSTS to 00H. The format of OSTS is shown in Figure 4-4. Figure 4-4. Oscillation Stabilization Time Specification Register (OSTS) Format
7 OSTS 0
6 0
5 0
4 0
3 0
2
1
0
Address
After reset 00H
R/W R/W
OSTS2 OSTS1 OSTS0 0FFCFH
Oscillation stabilization time selection (see Figure 25-4 for details)
Caution When using the regulator (refer to CHAPTER 5 REGULATOR), set a value of at least 10.4 ms, taking in consideration the regulator output stabilization time.
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4.3 Clock Generator Operation 4.3.1 Clock oscillator (1) When using crystal/ceramic oscillation The clock oscillator starts oscillating when the RESET signal is input, and stops oscillation when the STOP mode is set by the standby control register (STBC). Oscillation is resumed when the STOP mode is released. (2) When using external clock The clock oscillator supplies the clock input from the X1 pin to the internal circuitry when the RESET signal is input. 4.3.2 Divider The divider performs 1/1, 1/2, 1/4, or 1/8 scaling of the clock oscillator output, and supplies the resulting clock to the CPU, watchdog timer, noise elimination circuit, clocked serial interface (CSI), A/D converter, PWM, interrupt control circuit, and local bus interface. The division ratio is specified by the CK0 and CK1 bits of the standby control register (STBC). Controlling the division ratio to match the speed required by the CPU enables the overall power consumption to be reduced. Also, the operating speed can be selected to match the supply voltage. When RESET is input, the lowest speed (1/8) is selected. If the division ratio of the divider circuit is changed, the maximum time shown in Table 4-1 is required to change the division ratio, depending on the clock selected before change. Instruction execution continues even while the division ratio is changed, and the clock is supplied with the previous division ratio until the division ratio has been completely changed. Table 4-1. Time Required to Change Division Ratio
Previous Division Ratio None 1/2 1/4 1/8 Maximum Time Required for Change 11/fXX 12/fXX 8/fXX 8/fXX
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4.4 Cautions The following cautions apply to the clock generator. 4.4.1 When an external clock is input (1) When an external clock is input, this should be performed with a HCMOS device, or a device with the equivalent drive capability. (2) A signal should not be extracted from the X1 and X2 pins. If a signal is extracted, it should be extracted from point a in Figure 4-5. Figure 4-5. Signal Extraction with External Clock Input
PD784938
a X1
PD74HC04, etc.
X2
(3) The wiring connecting the X1 pin to the X2 pin via an inverter, in particular, should be made as short as possible.
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4.4.2 When crystal/ceramic oscillation is used (1) As the oscillator is a high-frequency analog circuit, considerable care is required. The following points, in particular, require attention. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. If oscillation is not performed normally and stably, the microcontroller will not be able to operate normally and stably, either. Also, if a high-precision oscillation frequency is required, consultation with the oscillator manufacturer is recommended. Figure 4-6. Cautions on Resonator Connection
PD784938
X2
X1
VSS
Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins. 2. No other signal lines should pass through the area enclosed by the broken lines.
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Figure 4-7. Incorrect Example of Resonator Connection (a) Wiring of connected circuits is too long
PD784938
(b) Crossed signal lines
PD784938
Pnm
X2
X1
VSS
X2
X1
VSS
(c) Wiring near high fluctuating current
(d) Current flowing through ground line of oscillator (Potentials at points A, B, and C fluctuate)
PD784938
VDD
X2
X1
VSS Pnm
PD784938
High fluctuating current
X2
X1
VSS
A
B High current
C
(e) Signal extracted
PD784938
X2
X1
VSS
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(2) When the device is powered on, and when restoring from the STOP mode, sufficient time must be allowed for the oscillation to stabilize. Generally speaking, the time required for oscillation stabilization is several milliseconds when a crystal resonator is used, and several hundred microseconds when a ceramic resonator is used. An adequate oscillation stabilization period should be secured by the following means: <1> When powered-on: RESET input (reset period) <2> When returning from STOP mode: (i) RESET input (reset period) (ii) Time of the oscillation stabilization timer that automatically starts at the valid edge of NMI, INTP4, or INTP5 signalNote (set by the oscillation stabilization time specification register (OSTS)) Note For INTP4 and INTP5, when masking is released and macro service is disabled.
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CHAPTER 5 REGULATOR
5.1 Outline of Regulator The PD784938 has a regulator that reduces the power consumption of the device (a circuit for low voltage operation). The operation of this regulator is controlled by the input level of the REGOFF pin. When the REGOFF pin is made high, the regulator is turned OFF; when it is made low, the regulator is turned ON. When the regulator is turned ON, it enables to reduce the power consumption. To stabilize the output voltage of the regulator, connect a capacitor for stabilizing the regulator (approximately 1
F) to the REGC pin.
Apply the same level as VDD to the REGC pin when the regulator is stopped. Figure 5-1 shows the block diagram of the peripherals of the regulator. Figure 5-1. Regulator Peripherals Block Diagram
REGOFF Low level: Regulator ON High level: Regulator OFF
VDD
Regulator
Internal supply voltage (Supplied to CPU and each peripheral circuit)
REGC 1 F
* Processing of REGC pin
Regulator ON Regulator OFF Connects capacitance for regulator stabilization Supplies power supply voltage
Caution For the oscillation stabilization time when the stop mode is released, set a value of at least 10.4 ms with the oscillation stabilization time specification register (OSTS), taking in consideration the regulator output oscillation stabilization time. (refer to CHAPTER 25 STANDBY FUNCTION.)
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6.1 Digital Input/Output Ports The PD784938 is provided with the ports shown in Figure 6-1, enabling various kinds of control to be performed. The function of each port is shown in Table 6-1. For ports 0 to 6, port 9, and port 10, use of an on-chip pull-up resistor can be specified by software when used as input ports. Figure 6-1. Port Configuration
P00 Port 0 P07 P10 Port 1 P17 P20 to P27 P30 Port 3 P37 P40 Port 4 P47 P50 Port 5 P57 P60 Port 6 P97 P100 Port 10 P107 P77 P67 P70 Port 7 8 Port 2
P90 Port 9
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Table 6-1. Port Functions
Port Name Port 0 Pin Names P00 to P07 Functions * Input/output can be specified in 1-bit units. * Can also operate as 4-bit real-time output ports (P00 to P03, P04 to P07). * Can drive a transistor. * Input/output can be specified in 1-bit units. * LED drive capability. * Input port * Input/output can be specified in 1-bit units. * P32/SCK0 pin and P33/SO0 pin can be set in N-ch open-drain mode. * Input/output can be specified in 1-bit units. * Can drive an LED. * Input/output can be specified in 1-bit units. * LED drive capability. Port 6 Port 7 Port 9 Port 10 P60 to P67 P70 to P77 P90 to P97 P100 to P107 * Input/output can be specified in 1-bit units. * Input/output can be specified in 1-bit units. * Input/output can be specified in 1-bit units. * Input/output can be specified in 1-bit units. * P105/SCK3 pin and P107/SO3 pin can be set in N-ch open-drain mode. -- Input mode pin specified at once 6-bit unit (P22 to P27) Input mode pins specified at once Software Pull-Up Specification Input mode pins specified at once
Port 1
P10 to P17
Port 2 Port 3
P20 to P27 P30 to P37
Port 4
P40 to P47
Port 5
P50 to P57
Table 6-2. Number of Input/Output Ports
Input/Output Ports Input ports Input/output ports Output ports Total 8 72 0 80 Total Input Mode Software Pull-Up Resistor 6 64 -- 70 Direct LED Drive -- 24 0 24 Output Mode Direct Transistor Drive -- 0 8 8
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6.2 Port 0 Port 0 is an 8-bit input/output port with an output latch, and has direct transistor drive capability. Input/output can be specified in 1-bit units by means of the port 0 mode register (PM0). Each pin incorporates a software programmable pull-up resistor. P00 to P03 and P04 to P07 can output the buffer register (P0L, P0H) contents at any time interval as 4-bit real-time output ports or one 8-bit real-time output port. The real-time output port control register (RTPC) is used to select whether this port is used as a normal output port or a real-time output port. When RESET is input, port 0 is set as an input port (output high-impedance state), and the output latch contents are undefined. 6.2.1 Hardware configuration The port 0 hardware configuration is shown in Figure 6-2. Figure 6-2. Port 0 Block Diagram
VDD WRPUOL Pull-up resistor option register L PUOL0 RDPUOL
WRRTPC
Real-time output port control register
P0LM (P0HM) RDRTPC
WRPM0
Port 0 mode register
PM0n (PM0m) RDPM0
Trigger
WRP0L
Internal bus
Buffer register
P0Ln (P0Hm) RDP0L
Selector Output latch
WROUT
P0n (P0m)
P0n (P0m) n=0,1,2,3 m=4,5,6,7
RDP0
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6.2.2 I/O mode/control mode setting The port 0 input/output mode is set by means of the port 0 mode register (PM0) as shown in Figure 6-3. Figure 6-3. Port 0 Mode Register (PM0) Format
7 PM0 PM07 6 PM06 5 PM05 4 PM04 3 PM03 2 PM02 1 PM01 0 PM00 Address 0FF20H After reset FFH R/W R/W
PM0n 0 1
P0n Pin Input/Output Mode Specification (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
When port 0 is used as a real-time output port, the P0LM and P0HM bits of the real-time output port control register (RTPC) should be set (to 1). When P0LM and P0HM are set, the respective pin output buffer is turned on and the output latch contents are output to the pin irrespective of the contents of PM0.
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6.2.3 Operating status Port 0 is an input/output port. (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once data has been written to the output latch, it is retained until data is next written to the output latchNote. Writes cannot be performed to the output latch of a port specified as a real-time output port. However, the output latch contents can be read even if it is set to the real-time output port mode. Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction. Figure 6-4. Port Specified as Output Port
WRPORT Output latch Internal bus RDOUT P0n n = 0 to 7
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(2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction, etc. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. However, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. Figure 6-5. Port Specified as Input Port
WRPORT
Output latch
P0n n = 0 to 7
Internal bus RDIN
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits which are switched between input and output. Caution is also required when manipulating the port with other 8-bit arithmetic instructions.
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6.2.4 On-chip pull-up resistors Port 0 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an on-chip pull-up resistor is to be used can be specified for each pin by means of the PUOL0 bit of the pullup resistor option register L (PUOL) and the port 0 mode register (PM0). When PUOL0 is 1, the on-chip pull-up resistors of the pins for which input is specified by PM0 are enabled (PM0n = 1, n = 0 to 7). Figure 6-6. Pull-Up Resistor Option Register L (PUOL) Format
7 PUOL 0 6 5 4 3 2 1 0 Address After reset 00H R/W R/W
PUOL6 PUOL5 PUOL4 PUOL3 PUOL2 PUOL1 PUOL0 0FF4EH
PUOL0 0 1
Port 0 Pull-Up Resistor Specification Not used in port 0 Used in port 0
Remark
When STOP mode is entered, setting PUOL to 00H is effective for reducing the current consumption.
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Figure 6-7. Pull-Up Resistor Specification (Port 0)
VDD
P07
P06
P05 Input buffer Internal bus
P01
P00
(PUOL) PUOL0
Port 0 mode register (PM0)
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6.2.5 Transistor drive In port 0, the output buffer high-level side drive capability has been increased, allowing active-high direct transistor drive. An example of the connection is shown in Figure 6-8. Figure 6-8. Example of Transistor Drive
VDD
Load
P0n
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6.3 Port 1 Port 1 is an 8-bit input/output port with an output latch. Input/output can be specified in 1-bit units by setting the port 1 mode register (PM1). Each pin incorporates a programmable pull-up resistor. This port has direct LED drive capability. In addition to their input/output port function, P10 to P14 also have an alternate function as serial interface pins. The operation mode can be specified bit-wise by setting the port 1 mode control register (PMC1), as shown in Table 6-3. The level of any pin can be read and tested at any time irrespective of the alternate-function operation. When RESET is input, port 1 is set as an input port (output high-impedance state), and the output latch contents are undefined. Table 6-3. Port 1 Operation Modes
Pin Name P10, P11 P12 P13 P14 P15 to P17 Port Mode I/O port Control Signal I/O Mode -- ASCK2 I/O/SCK2 I/O RxD2 input/SI2 input TxD2 output/SO2 output -- Operation to Operate Control Pin -- Setting PMC12 bit of PMC1 to 1 Setting PMC13 bit of PMC1 to 1 Setting PMC14 bit of PMC1 to 1 --
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6.3.1 Hardware configuration The port 1 hardware configuration is shown in Figures 6-9 to 6-12. Figure 6-9. P12 (Port 1) Block Diagram
WRPUOL Pull-up resistor option register L PUOL1 RDPUOL
WRPM1
Port 1 mode register
PM12 RDPM1
VDD
WRPMC1
Port 1 mode control register
PMC12 RDPMC1
Internal bus
External SCK2 SCK2 output
WRP1
Output latch
Selector
P12
P12 RDP1
ASCK2, SCK2 input
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Figure 6-10. P13 (Port 1) Block Diagram
WRPUOL Pull-up resistor option register L RDPUOL PUOL1 WRPM1
Port 1 mode register
PM13 RDPM1
VDD
WRPMC1 RDPMC1
Internal bus
Port 1 mode control register
PMC13
WRP1
Output latch
P13 RDP1
P13
SI2, RxD2 input
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Figure 6-11. P14 (Port 1) Block Diagram
WRPUOL
Pull-up resistor option register L PUOL1
RDPUOL
WRPM1
Port 1 mode register
VDD
PM14 RDPM1
WRPMC1
Port 1 mode control register
PMC14 RDPMC1
Internal bus
TxD2/SO2 output WRP1
Output latch Selector
P14
P14 RDP1
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Figure 6-12. Block Diagram of P10, P11, and P15 to P17 (Port 1)
WRPUOL
Pull-up resistor option register L PUOL1
RDPUOL WRPM1
VDD
Port 1 mode register
PM1n RDPM1
WRP1
Internal bus
Output latch
P1n RDP1
P1n n = 0, 1, 5 to 7
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6.3.2 I/O mode/control mode setting The port 1 input/output mode is set for each pin by means of the port 1 mode register (PM1) as shown in Figure 6-13. In addition to their input/output port function, P12 to P14 also have an alternate function as serial interface pins, and the control mode is specified by setting the port 1 mode control register (PMC1) as shown in Figure 6-14. Figure 6-13. Port 1 Mode Register (PM1) Format
7 PM1 PM17 6 PM16 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 Address 0FF21H After reset FFH R/W R/W
PM1n 0 1
P1n Pin Input/Output Mode Specification (n = 0 to 7) Output mode (output buffer on) Intput mode (output buffer off)
Figure 6-14. Port 1 Mode Control Register (PMC1) Format
7 PMC1 0 6 0 5 0 4 3 2 1 0 0 0 Address 0FF41H After reset 00H R/W R/W
PMC14 PMC13 PMC12
PMC12 0 1
P12 Pin Control Mode Specification Input/output port mode ASCK2/SCK2 input/output mode
PMC13 0 1
P13 Pin Control Mode Specification Input/output port mode RxD2/SI2 input mode
PMC14 0 1
P14 Pin Control Mode Specification Input/output port mode TxD2/SO2 output mode
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6.3.3 Operating status Port 1 is an input/output port. Pins P12 to P14 have an alternate function as serial interface pins. (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once data has been written to the output latch, it is retained until data is next written to the output latchNote. Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction. Figure 6-15. Port Specified as Output Port
WRPORT Output latch Internal bus RDOUT
P1n n = 0 to 7
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(2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction, etc. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. However, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. Figure 6-16. Port Specified as Input Port
WRPORT
Output latch
P1n n = 0 to 7
Internal bus
RDIN
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. Therefore, if a bit manipulation instruction is used on a port that has the I/O mode or port mode and control mode, the contents of the output latch of the pin set in the input mode or control mode become undefined (excluding bits manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits which are switched between input and output. Caution is also required when manipulating the port with other 8-bit arithmetic instructions.
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(3) When specified as control signal input/output P12 to P14 (by setting (to 1) bits of the port 1 mode control register (PMC1)) can be used as control signal inputs or outputs bit-wise irrespective of the setting of the port 1 mode register (PM1). When a pin is used as a control signal, the control signal status can be seen by executing a port read instruction. Figure 6-17. Control Specification
Control (input) Control (output) PM1n = 0 P1n n = 2 to 4
RD Internal bus
PM1n = 1
(a) When port is control signal output When the port 1 mode register (PM1) is set (to 1), the control signal pin level can be read by executing a port read instruction. When PM1 is reset (to 0), the PD784938 internal control signal status can be read by executing a port read instruction. (b) When port is control signal input When the port 1 mode register (PM1) is set (to 1), control signal pin level can be read by executing a port read instruction.
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6.3.4 On-chip pull-up resistors Port 1 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an on-chip pull-up resistor is to be used can be specified for each pin by means of the PUOL1 bit of the pullup resistor option register L (PUOL) and the port 1 mode register (PM1). When PUOL1 is 1, the on-chip pull-up resistors of the pins for which input is specified by PM1 are enabled (PM1n = 1, n = 0 to 7). Also, the specification for use of the pull-up resistor is also valid for pins specified as control signal output pins (pull-up resistors are also connected to pins that function as control signal output pins). Therefore, if you do not want to connect the pullup resistors with the control signal output pin, the contents of the corresponding bits of PM1 should be set to 0 (output mode). Figure 6-18. Pull-Up Resistor Option Register L (PUOL) Format
7 PUOL 0 6 5 4 3 2 1 0 Address After reset 00H R/W R/W
PUOL6 PUOL5 PUOL4 PUOL3 PUOL2 PUOL1 PUOL0 0FF4EH
PUOL1 0 1
Port 1 Pull-Up Resistor Specification Not used in port 1 Used in port 1
Remark
When STOP mode is entered, setting PUOL to 00H is effective for reducing the current consumption.
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Figure 6-19. Pull-Up Resistor Specification (Port 1)
VDD
P17
P16
P15 Input buffer Internal bus
P11
P10
(PUOL) PUOL1
Port 1 mode register (PM1)
6.3.5 Direct LED drive In port 1, the output buffer low-level side drive capability has been reinforced allowing active-low direct LED drive. An example of such use is shown in Figure 6-20. Figure 6-20. Example of Direct LED Drive
VDD
PD784938
P1n (n = 0 to 7)
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6.4 Port 2 Port 2 is an 8-bit input-only port. P22 to P27 incorporate a software programmable pull-up resistor. As well as operating as input ports, port 2 pins also operate as control signal input pins, such as external interrupt signal pins (see Table 6-4). All 8 pins are Schmitt-triggered inputs to prevent misoperation due to noise. Table 6-4. Port 2 Operation Modes
Port Name P20 P21 Input port/NMI inputNote Input port/INTP0 input/CR11 capture trigger input/ timer/event counter 1 count clock/real-time output port trigger signal Input port/INTP1 input/CR22 capture trigger input Input port/INTP2 input/CI input Input port/INTP3 input/CR02 capture trigger input/ timer/event counter 0 count clock Input port/INTP4 input/ASCK input/SCK1 input/output Input port/INTP5 input/A/D converter external trigger input Input port/SI0 input Function
P22 P23 P24
P25 P26 P27
Note NMI input is acknowledged regardless of whether interrupts are enabled or disabled. (a) Function as port pins The pin level can always be read or tested regardless of the alternate-function operation. (b) Functions as control signal input pins (i) NMI (Non-maskable Interrupt) The external non-maskable interrupt request input pin. Rising edge detection or falling edge detection can be specified by setting the external interrupt mode register 0 (INTM0). (ii) INTP0 to INTP5 (Interrupt from Peripherals) External interrupt request input pins. When the valid edge specified by the external interrupt mode registers 0, 1 (INTM0/INTM1) is detected an interrupt is generated (see CHAPTER 22 EDGE DETECTION FUNCTION). In addition, pins INTP0 to INTP3 and INTP5 are also used as external trigger input pins with the various functions shown below. * INTP0 ....... Timer/event counter 1 capture trigger input pin External count clock input pin Real-time output port trigger input pin * INTP1 ....... Timer/event counter 2 capture register (CR22) capture trigger input pin * INTP2 ....... Timer/event counter 2 external count clock input pin Capture/compare register (CR21) capture trigger input pin * INTP3 ....... Timer/event counter 0 capture trigger input pin Timer/event counter 0 external count clock input pin * INTP5 ....... A/D converter external trigger input pin
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(iii) CI (Clock Input) The timer/event counter 2 external clock input pin (iv) ASCK (Asynchronous Serial Clock) The external baud rate clock input pin (v) SCK1 (Serial Clock 1) The serial clock input/output pin (in 3-wire serial I/O 1 mode) (vi) SI0 (Serial Input 0) The serial data input pin (in 3-wire serial I/O 0 mode)
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6.4.1 Hardware configuration The port 2 hardware configuration is shown in Figure 6-21. Figure 6-21. Block Diagram of P20 to P24, P26 and P27 (Port 2)
Note
VDD WRPUOL
Pull-up resistor option register L PUOL2
RDPUOL
RDP2
P2n n = 0 to 4, 6 Internal bus RDP2 Various interrupt control signals Edge detection circuit VDD
P27
SI0 input 3-wire serial I/O mode 0
Note P20 and P21 do not have the circuitry enclosed by the broken lines.
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Figure 6-22. P25 (Port 2) Block Diagram
WRPUOL VDD PUOL2 RDPUOL
SCK1 output mode Internal bus SCK1 output P25/ASCK/SCK1
ASCK/SCK1 input
RDP2
INTP4 input
Edge detection circuit
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6.4.2 Input mode/control mode setting Port 2 is an input-only port, and there is no register for setting the input mode. Also, control signal input is always possible, and therefore the signal to be used is determined by the control registers for individual on-chip hardware items. 6.4.3 Operating status Port 2 is an input-only port, and pin levels can always be read or tested. Figure 6-23. Port Specified as Input Port
RDIN
Internal bus
P2n n = 0 to 7
6.4.4 On-chip pull-up resistors P22 to P27 incorporate pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an on-chip pull-up resistor is to be used can be specified for all six pins, P22 to P27, together by means of the PUOL2 bit of the pull-up resistor option register L (PUOL) (bit-wise specification is not possible). P20 and P21 do not incorporate a pull-up resistor. Figure 6-24. Pull-Up Resistor Option Register L (PUOL) Format
7 PUOL 0 6 5 4 3 2 1 0 Address After reset 00H R/W R/W
PUOL6 PUOL5 PUOL4 PUOL3 PUOL2 PUOL1 PUOL0 0FF4EH
PUOL2 0 1
Port 2 Pull-Up Resistor Specification Not used in port 2 Used in pins P22 to P27
Remark
When STOP mode is entered, setting PUOL to 00H is effective for reducing the current consumption.
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Figure 6-25. Pull-Up Specification (Port 2)
VDD
P22
P23
P24 Internal bus Input buffer P25
P26
P27
PUOL2 Pull-up resistor option register L (PUOL)
Caution As P22 to P26 are not pulled up immediately after a reset, an interrupt request flag may be set depending on the function of the alternate function (INTP1 to INTP5). Therefore, the interrupt request flags should be cleared after specifying pull-up in the initialization routine.
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6.5 Port 3 Port 3 is an 8-bit input/output port with an output latch. Input/output can be specified in 1-bit units by setting the port 3 mode register (PM3). Each pin incorporates a software programmable pull-up resistor. P32 and P33 can be set in the N-ch opendrain mode. In addition to its function as an input/output port, port 3 also has various alternate-function control signal pin functions. The operation mode can be specified in 1-bit units by setting the port 3 mode control register (PMC3), as shown in Table 6-5. The pin level of all pins can always be read or tested regardless of the alternate-function pin operation. When RESET is input, port 3 is set as an input port (output high-impedance state), and the output latch contents are undefined. Table 6-5. Port 3 Operation Modes (n = 0 to 7)
Mode Setting Condition P30 P31 P32 P33 P34 P35 P36 P37 Port Mode PMC3n = 0 Input/output port Control Signal Input/Output Mode PMC3n = 1 RxD input/SI1 input TxD output/SO1 output SCK0 input/output SO0 output TO0 output TO1 output TO2 output TO3 output
(a) Port mode Each port specified as port mode by the port 3 mode control register (PMC3) can be specified as input/output bit-wise by setting the port 3 mode register (PM3). (b) Control signal input/output mode Pins can be set as control pins in 1-bit units by setting the port 3 mode control register (PMC3). (i) RxD (Receive Data) /SI1 (Serial Input 1) RxD is the asynchronous serial interface serial data input pin. SI1 is the serial data input pin (in 3-wire serial I/O 1 mode). (ii) TxD (Transmit Data) /SO1 (Serial Output 1) TxD is the asynchronous serial interface serial data output pin. SO1 is the serial data output pin (in 3-wire serial I/O 1 mode). (iii) SCK0 (Serial Clock 0) SCK0 is the clocked serial interface serial clock input/output pin (in 3-wire serial I/O 0 mode). (iv) SO0 (Serial Output 0) SO0 is the serial data output pin (in 3-wire serial I/O 0 mode). (v) TO0 to TO3 (Timer Output) Timer output pins
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6.5.1 Hardware configuration The port 3 hardware configuration is shown in Figures 6-26 to 6-29. Figure 6-26. P30 (Port 3) Block Diagram
WRPUOL Pull-up resistor option register L PUOL3 WRPM3
Port 3 mode register
RDPUOL
PM30 RDPM3
VDD
WRPMC3
Port 3 mode control register
PMC30 RDPMC3
Internal bus Output latch
WRP3
P30 RDP3
P30
SI1, RxD input
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Figure 6-27. Block Diagram of P31 and P34 to P37 (Port 3)
WRPUOL Pull-up resistor option register L PUOL3 RDPUOL
WRPM3
Port 3 mode register
VDD
PM3n RDPM3
WRPMC3
Port 3 mode control register
PMC3n RDPMC3
Internal bus
TO, SO1, TxD output WRP3
Output latch Selector
P3n n = 1, 4, 5, 6, 7
P3n RDP3
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Figure 6-28. P32 (Port 3) Block Diagram
WRPUOL Pull-up resistor option register L PUOL3 RDPUOL
WRPM3
Port 3 mode register PM32
RDPM3 SCK0 input WRPMC3 Internal bus Port 3 mode control register PMC32 RDPMC3 N-ch open-drain specification (CSIM MOD bit) VDD
SCK0 output RDP3 Output latch P32 RDP3
Selector
VDD
P32
SCK0 input
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Figure 6-29. P33 (Port 3) Block Diagram
WRPUOL
Pull-up resistor option register L PUOL3
RDPUOL
WRPM3
Port 3 mode register
PM33 RDPM3
WRPMC3
Port 3 mode control register
N-ch open-drain specification (CSIM MOD bit)
PMC33 RDPMC3
Internal bus
VDD
SO0 output WRP3
Output latch Selector
VDD P33
P33
RDP3
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6.5.2 I/O mode/control mode setting The port 3 input/output mode is set for each pin by means of the port 3 mode register (PM3) as shown in Figure 6-30. In addition to their input/output port function, port 3 pins also have an alternate function as various control signal pins, and the control mode is specified by setting the port 3 mode control register (PMC3) as shown in Figure 6-31. Figure 6-30. Port 3 Mode Register (PM3) Format
7 PM3 PM37 6 PM36 5 PM35 4 PM34 3 PM33 2 PM32 1 PM31 0 PM30 Address 0FF23H After reset FFH R/W R/W
PM3n 0 1
P3n Pin Input/Output Mode Specification (n = 0 to 7) Output mode (output buffer on) Intput mode (output buffer off)
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Figure 6-31. Port 3 Mode Control Register (PMC3) Format
7 PMC3 6 5 4 3 2 1 0 Address After reset 00H R/W R/W
PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 0FF43H
PMC30 0 1
P30 Pin Control Mode Specification Input/output port mode RxD/SI1 input mode
PMC31 0 1
P31 Pin Control Mode Specification Input/output port mode TxD/SO1 output mode
PMC32 0 1
P32 Pin Control Mode Specification Input/output port mode SCK0 Input/output mode
PMC33 0 1
P33 Pin Control Mode Specification Input/output port mode SO0 output mode
PMC3n 0 1
P3n Pin Control Mode Specification (n = 4 to 7) Input/output port mode TOn output mode (n = 0 to 3)
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6.5.3 Operating status Port 3 is an input/output port, with an alternate function as various control pins. (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once data has been written to the output latch, it is retained until data is next written to the output latchNote. Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction. Figure 6-32. Port Specified as Output Port
WRPORT Output latch Internal bus RDOUT
P3n n = 0 to 7
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(2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. However, since the output buffer of a bit specified as an input port is high impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. Figure 6-33. Port Specified as Input Port
WRPORT
Output latch Internal bus RDIN
P3n n = 0 to 7
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins or port mode and control mode, the contents of the output latch of pins specified as inputs and pins specified as control mode will be undefined (excluding bits manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits which are switched between input and output. Caution is also required when manipulating the port with other 8-bit arithmetic instructions.
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(3) When specified as control signal input/output By setting (to 1) bits of the port 3 mode control register (PMC3), port 3 can be used as control signal input or output bit-wise irrespective of the setting of the port 3 mode register (PM3). When a pin is used as a control signal, the control signal status can be seen by executing a port read instruction. Figure 6-34. Control Specification
Control (input)
Control (output) PM3n = 0
P3n n = 0 to 7
RD
PM3n = 1
Internal bus
(a) When port is control signal output When the port 3 mode register (PM3) is set (to 1), the control signal pin level can be read by executing a port read instruction. When PM3 is reset (to 0), the PD784938 internal control signal status can be read by executing a port read instruction. (b) When port is control signal input Only the port 3 mode register (PM3) is set (to 1), control signal pin levels can be read by executing a port read instruction.
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6.5.4 On-chip pull-up resistors Port 3 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an on-chip pull-up resistor is to be used can be specified for each pin by setting the PUOL3 bit of the pullup resistor option register L (PUOL) and the port 3 mode register (PM3). When PUOL3 is 1, the on-chip pull-up resistors of the pins for which input is specified by PM3 (PM3n = 1, n = 0 to 7) are enabled. Also, the specification for use of the pull-up resistor is also valid for pins specified as control mode pins (pull-up resistors are also connected to pins that function as output pins in the control mode). Therefore, if you do not want to connect the pull-up resistors in the control mode, the contents of the corresponding bits of PM3 should be set to 0 (output mode). Figure 6-35. Pull-Up Resistor Option Register L (PUOL) Format
7 PUOL 0 6 5 4 3 2 1 0 Address After reset 00H R/W R/W
PUOL6 PUOL5 PUOL4 PUOL3 PUOL2 PUOL1 PUOL0 0FF4EH
PUOL3 0 1
Port 3 Pull-Up Resistor Specification Not used in port 3 Used in port 3
Remark
When STOP mode is entered, setting PUOL to 00H is effective for reducing the current consumption.
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Figure 6-36. Pull-Up Specification (Port 3)
VDD
P30
P31
Input buffer Internal bus
P32
P36
P37
(PUOL) PUOL3
Port 3 mode register (PM3)
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6.6 Port 4 Port 4 is an 8-bit input/output port with an output latch. Input/output can be specified in 1-bit units by setting the port 4 mode register (PM4). Each pin incorporates a software programmable pull-up resistor. This port has direct LED drive capability. Port 4 also functions as the time division address/data bus (AD0 to AD7) by the memory expansion mode register (MM) when external memory or I/Os are expanded. When RESET is input, port 4 is set as an input port (output high-impedance state), and the output latch contents are undefined. 6.6.1 Hardware configuration The port 4 hardware configuration is shown in Figure 6-37. Figure 6-37. Port 4 Block Diagram
WRPUOL
Pull-up resistor option register L PUOL4
RDPUOL VDD MM0 to MM3 WRPM4 Port 4 mode register PM4n RDPM4
WRP4 Internal data bus RDP4
Output latch P4n
P4n n = 0 to 7
Input/ output control circuit
Internal address bus
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6.6.2 I/O mode/control mode setting The port 4 input/output mode is set for each pin by means of the port 4 mode register (PM4) as shown in Figure 6-38. When port 4 is used as the address/data bus, it is set by means of the memory expansion mode register (MM: See Figure 24-1) as shown in Table 6-6. Figure 6-38. Port 4 Mode Register (PM4) Format
7 PM4 PM47 6 PM46 5 PM45 4 PM44 3 PM43 2 PM42 1 PM41 0 PM40 Address 0FF24H After reset FFH R/W R/W
P4n 0 1
P4n Pin Input/Output Mode Specification (n = 0 to 7) Output mode (output buffer on) Intput mode (output buffer off)
Table 6-6. Port 4 Operation Modes
MM Bits MM3 0 0 0 0 0 0 1 1 MM2 0 0 1 1 1 1 0 0 MM1 0 1 0 0 1 1 0 0 MM0 0 1 0 1 0 1 0 1 Port Address/data bus (AD0 to AD7) Operation Mode
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6.6.3 Operating status Port 4 is an input/output port, with an alternate function as the address/data bus (AD0 to AD7). (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once data has been written to the output latch, it is retained until data is next written to the output latchNote. Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction. Figure 6-39. Port Specified as Output Port
WRPORT Output latch Internal bus RDOUT
P4n n = 0 to 7
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(2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. However, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a port specified as input is switched to an output port, the output latch contents are output to the port pin). Also, when specified as an input port, the output latch contents cannot be loaded into an accumulator. Figure 6-40. Port Specified as Input Port
WRPORT
Output latch
P4n n = 0 to 7
Internal bus RDIN
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits which are switched between input and output. Caution is also required when manipulating the port with other 8-bit arithmetic instructions. (3) When used as address/data bus (AD0 to AD7) Used automatically when an external access is performed. Input/output instructions should not be executed on port 4.
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6.6.4 On-chip pull-up resistors Port 4 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an on-chip pull-up resistor is to be used can be specified for each pin by setting the PUOL4 bit of the pullup resistor option register L (PUOL) and the port 4 mode register (PM4). When PUOL4 is 1, the on-chip pull-up resistors of the pins for which input is specified by the PM4 for port 4 (PM4n = 1, n = 0 to 7) are enabled . Figure 6-41. Pull-Up Resistor Option Register L (PUOL) Format
7 PUOL 0 6 5 4 3 2 1 0 Address After reset 00H R/W R/W
PUOL6 PUOL5 PUOL4 PUOL3 PUOL2 PUOL1 PUOL0 0FF4EH
PUOL4 0 1
Port 4 Pull-Up Resistor Specification Not used in port 4 Used in port 4
Caution When using the port 4 of the PD784938 as an address/data bus pin, be sure to clear PUOL4 to 0 to disconnect the on-chip pull-up resistor. Remark When STOP mode is entered, setting PUOL to 00H is effective for reducing the current consumption.
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Figure 6-42. Pull-Up Specification (Port 4)
VDD
P40
P41
P42 Input buffer Internal bus
P46
P47
(PUOL) PUOL4
Port 4 mode register (PM4)
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6.6.5 Direct LED drive In port 4, the output buffer low-level side drive capability has been reinforced, allowing active-low direct LED drive. An example of such use is shown in Figure 6-43. Figure 6-43. Example of Direct LED Drive
VDD
PD784938
P4n (n = 0 to 7)
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6.7 Port 5 Port 5 is an 8-bit input/output port with an output latch. Input/output can be specified in 1-bit units by setting the port 5 mode register (PM5). Each pin incorporates a software programmable pull-up resistor. This port has direct LED drive capability. In addition, P50 to P57 function as the address bus (A8 to A15) when external memory or I/Os are expanded. When RESET is input, port 5 is set as an input port (output high-impedance state), and the output latch contents are undefined. 6.7.1 Hardware configuration The port 5 hardware configuration is shown in Figure 6-44. Figure 6-44. Port 5 Block Diagram
WRPUOL
Pull-up resistor option register L PUOL5
RDPUOL VDD MM0 to MM3 WRPM5 Port 5 mode register PM5n RDPM5
Internal data bus RDP5
WRP5
Output latch P5n
P5n n = 0 to 7
Input/ output control circuit
Internal address bus
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6.7.2 I/O mode/control mode setting The port 5 input/output mode is set for each pin by setting the port 5 mode register (PM5) as shown in Figure 6-45. When port 5 pins can be used as port or address pins in 2-bit units, the setting is performed by means of the memory expansion mode register (MM: See Figure 24-1) as shown in Table 6-7. Figure 6-45. Port 5 Mode Register (PM5) Format
7 PM5 PM57 6 PM56 5 PM55 4 PM54 3 PM53 2 PM52 1 PM51 0 PM50 Address 0FF25H After reset FFH R/W R/W
PM5n 0 1
P5n Pin Input/Output Mode Specification (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
Table 6-7. Port 5 Operation Modes
MM Bits MM3 0 0 0 0 0 0 1 1 MM2 0 0 1 1 1 1 0 0 MM1 0 1 0 0 1 1 0 0 MM0 0 1 0 1 0 1 0 1 A8 A8 A8 A8 A9 A9 A9 A9 A10 A10 A10 A11 A11 A11 A12 A12 A13 A13 A14 Port Port Port A15 P50 P51 P52 Operation Mode P53 P54 P55 P56 P57
Port (P50 to P57)
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6.7.3 Operating status Port 5 is an input/output port, with an alternate function as the address bus (A8 to A15). (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once data has been written to the output latch, it is retained until data is next written to the output latchNote. Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction. Figure 6-46. Port Specified as Output Port
WRPORT Output latch Internal bus RDOUT
P5n n = 0 to 7
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(2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. However, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. Figure 6-47. Port Specified as Input Port
WRPORT
Output latch
P5n n = 0 to 7
Internal bus
RDIN
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits which are switched between input and output. Caution is also required when manipulating the port with other 8-bit arithmetic instructions. (3) When used as address bus (A8 to A15) Used automatically when an external address is accessed.
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6.7.4 On-chip pull-up resistors Port 5 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an on-chip pull-up resistor is to be used can be specified for each pin by setting the PUOL5 bit of the pullup resistor option register L (PUOL) and the port 5 mode register (PM5). When PUOL5 is 1, the on-chip pull-up resistors of the pins for which input is specified by the PM5 for port 5 (PM5n = 1, n = 0 to 7) are enabled . Figure 6-48. Pull-Up Resistor Option Register L (PUOL) Format
7 PUOL 0 6 5 4 3 2 1 0 Address After reset 00H R/W R/W
PUOL6 PUOL5 PUOL4 PUOL3 PUOL2 PUOL1 PUOL0 0FF4EH
PUOL5 0 1
Port 5 Pull-Up Resistor Specification Not used in port 5 Used in port 5
Caution When using the port 5 of the PD784938 as an address bus, be sure to clear PUOL5 to 0 to disconnect the on-chip pull-up resistor. Remark When STOP mode is entered, setting PUOL to 00H is effective for reducing the current consumption.
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Figure 6-49. Pull-Up Specification (Port 5)
VDD
P50
P51
P52 Input buffer Internal bus
P56
P57
(PUOL) PUOL5
Port 5 mode register (PM5)
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6.7.5 Direct LED drive In port 5, the output buffer low-level side drive capability has been reinforced, allowing active-low direct LED drive. An example of such use is shown in Figure 6-50. Figure 6-50. Example of Direct LED Drive
VDD
PD784938
P5n (n = 0 to 7)
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6.8 Port 6 Port 6 is an 8-bit input/output port with an output latch. P60 to P67 incorporate a software programmable pull-up resistor. In addition to its function as a port, port 6 also has various alternate-function control signal pin functions as shown in Table 6-8. Operations as control pins are performed by the respective function operations. When RESET is input, P60 to P67 are set as input port pins (output high-impedance state), and the output latch contents are undefined. Table 6-8. Port 6 Operation Modes
Pin Name Port Mode Control Signal Input/ Output Mode A16 to A19 outputs RD output WR output WAIT input Operation to Operate as Control Pins
P60 to P63 P64 P65 P66
Input/output ports
Specified by bits MM3 to MM0 of the MM in 2-bit units External memory expansion mode is specified by bits MM3 to MM0 of the MM Specified by bits PWn1 & PWn0 (n = 0 to 7) of the PWC1 & PWC2 or setting P66 in the input mode Bus hold enabled by the HLDE bit of the HLDM
HLDRQ input P67 HLDAK output REFRQ output
Set (to 1) the RFEN bit of the RFM
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6.8.1 Hardware configuration The port 6 hardware configuration is shown in Figures 6-51 to 6-54. Figure 6-51. P60 to P63 (Port 6) Block Diagram
WRPUOL
Pull-up resistor option register L PUOL6
RDPUOL VDD MM0 to MM3 WRPM6 Port 6 mode register PM6n RDPM6
WRP6 Internal data bus RDP6
Output latch P6n
P6n n = 0 to 3
Input/ output control circuit
Internal address bus
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Figure 6-52. P64 and P65 (Port 6) Block Diagram
WRPUOL
Pull-up resistor option register L PUOL6
RDPUOL
WRPM6
Port 6 mode register PM64 (PM65)
VDD
RDPM6
External expansion mode
Internal bus
RD signal (WR signal) WRP6 Output latch P64 (P65) RDP6
Selector
P64 (P65)
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Figure 6-53. P66 (Port 6) Block Diagram
WRPUOL Pull-up resistor option register L PUOL6 RDPUOL
WRPM6
Port 6 mode register PM66 VDD
RDPM6 Hold enabled mode External wait specification
Internal bus
WRP6
Output latch P66 P66
RDP6
Wait input
Hold request input
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Figure 6-54. P67 (Port 6) Block Diagram
WRPUOL Pull-up resistor option register L PUOL6 RDPUOL
WRPM6
Port 6 mode register PM67
VDD
RDPM6 Hold enabled mode Refresh mode Refresh signal Hold acknowledge signal WRP6 Output latch P67 RDP6 Selector P67
Internal bus
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6.8.2 I/O mode/control mode setting The port 6 input/output mode is set by setting the port 6 mode register (PM6) as shown in Figure 6-55. Operations for operating port 6 as control pins are shown in Table 6-9. Table 6-9. Port 6 Control Pin Function
Pin Name P60 P61 P62 P63 P64 P65 P66 Control Signal I/O Mode A16 A17 A18 A19 RD WR WAIT Input/output port Output port External memory expansion mode specified by bits MM3 to MM0 of the MM (see Table 6-10) External wait input is specified by bits PWn1 & PWn0 (n = 0 to 7) of the PWC1 & PWC2 Bus hold enabled by the HLDE bit of the HLDM Output port Set (to 1) the RFEN bit of the RFM Port Mode Input/output port Operation to Operate as Control Pins External memory expansion mode specified by bits MM3 to MM0 of the MM (see Table 6-10)
HLDRQ P67 HLDAK REFRQ
Table 6-10. P60 to P65 Control Pin Specification
MM Bits MM3 0 0 0 0 0 0 1 1 MM2 0 0 1 1 1 1 0 0 MM1 0 1 0 0 1 1 0 0 MM0 0 1 0 1 0 1 0 1 A16 A16 A17 A17 A18 Port A19 Port (P60 to P63) RD WR P60 P61 Operation Mode P62 P63 P64 P65
Port (P60 to P65)
(a) Port mode Each port not specified as in control mode can be specified as input/output in 1-bit units by setting the port 6 mode register (PM6). (b) Control signal input/output mode (i) A16 to A19 (Address Bus) Upper address bus output pins when the external memory space is expanded (10000H to FFFFFH). These pins operate in accordance with the memory expansion mode register (MM).
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(ii) RD (Read Strobe) The strobe signal for an external memory read operation. The operation of this pin is controlled by the memory expansion mode register (MM). (iii) WR (Write Strobe) Pin that outputs the strobe signal for an external memory write operation. The operation of this pin is controlled by the memory expansion mode register (MM). (iv) WAIT (Wait) Wait signal input pin. Operates in accordance with the programmable wait control registers (PWC1, PWC2). (v) HLDRQ (Hold Request) External bus hold request signal input pin. Operates in accordance with the hold mode register (HLDM). (vi) HLDAK (Hold Acknowledge) Bus hold acknowledge signal output pin. Operates in accordance with the hold mode register (HLDM). (vii) REFRQ (Refresh Request) This pin outputs refresh pulses to pseudo-static memory when this memory is connected to it externally. Operates in accordance with the refresh mode register (RFM). Figure 6-55. Port 6 Mode Register (PM6) Format
7 PM6 PM67 6 PM66 5 PM65 4 PM64 3 PM63 2 PM62 1 PM61 0 PM60 Address 0FF26H After reset FFH R/W R/W
PM6n 0 1
P6n Pin Input/Output Mode Specification (n = 0 to 7) Output mode (output buffer on) Intput mode (output buffer off)
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6.8.3 Operating status Port 6 is an input/output port, with an alternate function as various control pins. (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once data has been written to the output latch, it is retained until data is next written to the output latchNote. Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction. Figure 6-56. Port Specified as Output Port
WRPORT Output latch Internal bus RDOUT
P6n n = 0 to 7
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(2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. However, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. Figure 6-57. Port Specified as Input Port
WRPORT
Output latch
P6n n = 4 to 7
Internal bus RDIN
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, or port mode and control mode, the contents of the output latch of pins specified as inputs or pins specified as in the control mode will be undefined (excluding bits manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits which are switched between input and output. Caution is also required when manipulating the port with other 8-bit arithmetic instructions. (3) When used as control pins Cannot be manipulated or tested by software.
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6.8.4 On-chip pull-up resistors P60 to P67 incorporate pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an on-chip pull-up resistor is to be used can be specified for each pin by setting the PUOL6 bit of the pullup resistor option register L (PUOL) and the port 6 mode register (PM6). When PUOL6 is 1, the on-chip pull-up resistors of the pins for which input is specified by the PM6 (PM6n = 1, n = 0 to 7) are enabled . Figure 6-58. Pull-Up Resistor Option Register L (PUOL) Format
7 PUOL 0 6 5 4 3 2 1 0 Address After reset 00H R/W R/W
PUOL6 PUOL5 PUOL4 PUOL3 PUOL2 PUOL1 PUOL0 0FF4EH
PUOL6 0 1
Port 6 Pull-Up Resistor Specification Not used in port 6 Used in port 6
Remark
When STOP mode is entered, setting PUOL to 00H is effective for reducing the current consumption. Figure 6-59. Pull-Up Specification (Port 6)
VDD
P67
P66
P65 Input buffer Internal bus
P61
P60
(PUOL) PUOL6
Port 6 mode register (PM6)
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6.9 Port 7 Port 7 is an 8-bit input/output port. In addition to operating as an input/output port, it also operates as the A/D converter analog input pins (ANI0 to ANI7). Input/output can be specified in 1-bit units by setting the port 7 mode register (PM7). Pin levels can be read or tested at any time irrespective of alternate-function operations. When RESET is input, port 7 is set as an input port (output high-impedance state), and the output latch contents are undefined. 6.9.1 Hardware configuration The port 7 hardware configuration is shown in Figure 6-60. Figure 6-60. Port 7 Block Diagram
WRPM7
Port 7 mode register PM7n
RDPM7
WRP7
Output latch P7n P7n (n = 0 to 7)
Internal bus
RDP7
A/D converter
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6.9.2 I/O mode/control mode setting The port 7 input/output mode is set for each pin by setting the port 7 mode register (PM7) as shown in Figure 6-61. In addition to the operation of port 7 as an input/output port, analog signal input can be performed at any time. Mode setting is not necessary. Specification of the A/D conversion operation is performed by ADM of the A/D converter (see CHAPTER 16 A/D CONVERTER for details). Figure 6-61. Port 7 Mode Register (PM7) Format
7 PM7 PM77 6 PM76 5 PM75 4 PM74 3 PM73 2 PM72 1 PM71 0 PM70 Address 0FF27H After reset FFH R/W R/W
PM7n 0 1
P7n Pin Input/Output Mode Specification (n = 0 to 7) Output mode (output buffer on) Intput mode (output buffer off)
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6.9.3 Operating status Port 7 is an input/output port, with an alternate function as the A/D converter analog input pins (ANI0 to ANI7). (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once data has been written to the output latch, it is retained until data is next written to the output latchNote. Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction. Figure 6-62. Port Specified as Output Port
WRPORT Output latch Internal bus RDOUT
P7n n = 0 to 7
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(2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches-irrespective of the port input/output specification. However, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. Figure 6-63. Port Specified as Input Port
WRPORT
Output latch
P7n n = 0 to 7
Internal bus RDIN
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits which are switched between input and output. Caution is also required when manipulating the port with other 8-bit arithmetic instructions. 6.9.4 On-chip pull-up resistors Port 7 does not incorporate pull-up resistors. 6.9.5 Caution A voltage outside the range AVSS to AVREF must not be applied to pins for which P70 to P77 are used as ANI0 to AN17. See 16.6 Cautions in CHAPTER 16 A/D CONVERTER for details.
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6.10 Port 9 Port 9 is an 8-bit input/output port with an output latch. Input/output can be specified in 1-bit units by setting the port 9 mode register (PM9). Each pin incorporates a software programmable pull-up resistor. When RESET is input, port 9 is set as an input port (output high-impedance state), and the output latch contents are undefined. 6.10.1 Hardware configuration The port 9 hardware configuration is shown in Figure 6-64. Figure 6-64. Port 9 Block Diagram
WRPUOH Pull-up resistor option register H PUOH9 RDPUOH
WRPM9
Port 9 mode register
VDD
PM9n RDPM9
Internal bus
WRP9
Output latch
P9n n = 0 to 7
P9n RDP9
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6.10.2 I/O mode/control mode setting The port 9 input/output mode is set for each pin by setting the port 9 mode register (PM9) as shown in Figure 6-65. Figure 6-65. Port 9 Mode Register (PM9) Format
7 PM9 PM97 6 PM96 5 PM95 4 PM94 3 PM93 2 PM92 1 PM91 0 PM90 Address 0FF29H After reset FFH R/W R/W
PM9n 0 1
P9n Pin Input/Output Mode Specification (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
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6.10.3 Operating status Port 9 is an input/output port. (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once data has been written to the output latch, it is retained until data is next written to the output latchNote. Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction. Figure 6-66. Port Specified as Output Port
WRPORT Output latch Internal bus RDOUT
P9n n = 0 to 7
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(2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. However, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. Figure 6-67. Port Specified as Input Port
WRPORT
Output latch
P9n n = 0 to 7
Internal bus
RDIN
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits which are switched between input and output. Caution is also required when manipulating the port with other 8-bit arithmetic instructions.
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6.10.4 On-chip pull-up resistors Port 9 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an on-chip pull-up resistor is to be used can be specified for each pin by setting the PUOH9 bit of the pullup resistor option register H (PUOH) and the port 9 mode register (PM9). When PUOH9 is 1, the on-chip pull-up resistors of the pins for which input is specified by the PM9 for port 9 (PM9n = 1, n = 0 to 7) are enabled . Figure 6-68. Pull-Up Resistor Option Register H (PUOH) Format
7 PUOH 0 6 0 5 0 4 0 3 0 2 1 0 0 Address 0FF4FH After reset 00H R/W R/W
PUOH10 PUOH9
PUOH9 0 1
Port 9 Pull-Up Resistor Specification Not used in port 9 Used in port 9
Remark
When STOP mode is entered, setting PUOH to 00H is effective for reducing the current consumption. Figure 6-69. Pull-Up Specification (Port 9)
VDD
P97
P96
P95 Input buffer Internal bus
P91
P90
(PUOH) PUOH9
Port 9 mode register (PM9)
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6.11 Port 10 Port 10 is an 8-bit input/output port with an output latch. Input/output can be specified in 1-bit units by setting the port 10 mode register (PM10). Each pin incorporates a software programmable pull-up resistor. P105 and P107 can be set in the N-ch opendrain mode. In addition to its function as an input/output port, port 10 also has an alternate function as serial interface pin. The operation mode can be specified bit-wise by setting the port 10 mode control register (PMC10), as shown in Table 6-11. The pin level of all pins can always be read or tested regardless of the alternate-function pin operation. When RESET is input, port 10 is set as an input port (output high-impedance state), and the output latch contents are undefined. Table 6-11. Port 10 Operation Modes (n = 0 to 7)
Mode Setting Condition P100 to P104 P105 P106 P107 Port Mode PMC10n = 0 Input/output port Control Signal Input/Output Mode PMC10n = 1 -- SCK3 input/output SI3 input SO3 output
(a) Port mode Each port specified as port mode by the port 10 mode control register (PMC10) can be specified as input/output in 1bit units by setting the port 10 mode register (PM10). (b) Control signal input/output mode Pins can be set as control pins in 1-bit units by setting the port 10 mode control register (PMC10). (i) SCK3 (Serial Clock 3) SCK3 is the clocked serial interface serial clock input/output pin (in 3-wire serial I/O 3 mode). (ii) SI3 (Serial Input 3) SI3 is the serial data input pin (in 3-wire serial I/O 3 mode). (iii) SO3 (Serial Output 3) SO3 is the serial data output pin (in 3-wire serial I/O 3 mode).
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6.11.1 Hardware configuration The port 10 hardware configuration is shown in Figures 6-70 to 6-73. Figure 6-70. P100 to P104 (Port 10) Block Diagram
WRPUOH Pull-up resistor option register H PUOH10 RDPUOH
WRPM10
Port 10 mode register
VDD
PM10n RDPM10
Internal bus
WRP10
Output latch
P10n n = 0 to 4
P10n RDP10
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Figure 6-71. P105 (Port 10) Block Diagram
WRPUOH Pull-up resistor option register H PUOH10 RDPUOH
WRPM10 Port 10 mode register PM105 RDPM10 SCK3 Input WRPMC10 Internal bus Port 10 mode control register PMC105 RDPMC10 N-ch open-drain specification (CSIM3 MOD3 bit) VDD
SCK3 output RDP10 Output latch P105 RDP10
Selector
VDD
P105
SCK3 input
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Figure 6-72. P106 (Port 10) Block Diagram
WRPUOH Pull-up resistor option register H PUOH10 WRPM10
Port 10 mode register
RDPUOH
PM10n RDPM10
VDD
WRPMC10
Port 10 mode control register
PMC106 RDPMC10
Internal bus Output latch
WRP10
P106 RDP10
P106
SI3 input
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Figure 6-73. P107 (Port 10) Block Diagram
WRPUOH
Pull-up resistor option register H PUOH10
RDPUOH
WRPM10
Port 10 mode register
PM107 RDPM10
WRPMC10
Port 10 mode control register
N-ch open-drain specification (SCIM3 MOD3 bit)
PMC107 RDPMC10
Internal bus
VDD
SO3 output WRP10
Output latch Selector
VDD P107
P107
RDP10
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6.11.2 I/O mode/control mode setting The port 10 input/output mode is set for each pin by means of the port 10 mode register (PM10) as shown in Figure 6-74. In addition to their input/output port function, port 10 also have an alternate function as serial interface pin, and the control mode is specified by setting the port 10 mode control register (PMC10) as shown in Figure 6-75. Figure 6-74. Port 10 Mode Register (PM10) Format
7 PM10 6 5 4 3 2 1 0 Address After reset FFH R/W R/W
PM107 PM106 PM105 PM104 PM103 PM102 PM101 PM100 0FF2AH
PM10n P10n Pin Input/Output Mode Specification (n = 0 to 7) 0 1 Output mode (output buffer on) Intput mode (output buffer off)
Figure 6-75. Port 10 Mode Control Register (PMC10) Format
7 6 5 4 0 3 0 2 0 1 0 0 0 Address 0FF4AH After reset 00H R/W R/W
PMC10 PMC107 PMC106 PMC105
PMC105 0 1
P105 Pin Control Mode Specification Input/output port mode SCK3 input/output mode
PMC106 0 1
P106 Pin Control Mode Specification Input/output port mode SI3 input mode
PMC107 0 1
P107 Pin Control Mode Specification Input/output port mode SO3 output mode
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6.11.3 Operating status Port 10 is an input/output port, with an alternate function as various control pins. (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once data has been written to the output latch, it is retained until data is next written to the output latchNote. Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction. Figure 6-76. Port Specified as Output Port
WRPORT Output latch Internal bus RDOUT
P10n n = 0 to 7
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(2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. However, since the output buffer of a bit specified as an input port is high impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. Figure 6-77. Port Specified as Input Port
WRPORT
Output latch Internal bus RDIN
P10n n = 0 to 7
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins or port mode and control mode, the contents of the output latch of pins specified as inputs and pins specified as control mode will be undefined (excluding bits manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits which are switched between input and output. Caution is also required when manipulating the port with other 8-bit arithmetic instructions.
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(3) When specified as control signal input/output By setting (to 1) bits of the port 10 mode control register (PMC10), port 10 can be used as control signal input or output in 1-bit units irrespective of the setting of the port 10 mode register (PM10). When a pin is used as a control signal, the control signal status can be seen by executing a port read instruction. Figure 6-78. Control Specification
Control (input)
Control (output) PM10n = 0
P10n n = 0 to 7
RD
PM10n = 1
Internal bus
(a) When port is control signal output When the port 10 mode register (PM10) is set (to 1), the control signal pin level can be read by executing a port read instruction. When PM10 is reset (to 0), the PD784938 internal control signal status can be read by executing a port read instruction. (b) When port is control signal input Only the port 10 mode register (PM10) is set (to 1), control signal pin levels can be read by executing a port read instruction.
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6.11.4 On-chip pull-up resistors Port 10 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an on-chip pull-up resistor is to be used can be specified for each pin by setting the PUOH10 bit of the pullup resistor option register H (PUOH) and the port 10 mode register (PM10). When PUOH10 is 1, the on-chip pull-up resistors of the pins for which input is specified by PM10 (PM10n = 1, n = 0 to 7) are enabled. Also, the specification for use of the pull-up resistor is also valid for pins specified as control mode pins (pull-up resistors are also connected to pins that function as output pins in the control mode). Therefore, if you do not want to connect the pull-up resistors in the control mode, the contents of the corresponding bits of PM10 should be set to 0 (output mode). Figure 6-79. Pull-Up Resistor Option Register H (PUOH) Format
7 PUOH 0 6 0 5 0 4 0 3 0 2 1 0 0 Address 0FF4FH After reset 00H R/W R/W
PUOH10 PUOH9
PUOH10 0 1
Port 10 Pull-Up Resistor Specification Not used in port 10 Used in port 10
Remark
When STOP mode is entered, setting PUOH to 00H is effective for reducing the current consumption. Figure 6-80. Pull-Up Specification (Port 10)
VDD
P107
P106
Input buffer Internal bus
P105
P101
P100
(PUOH) PUOH10
Port 10 mode register (PM10)
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6.12 Port Output Check Function The PD784938 has a function for reading and testing output port pin levels in order to improve the reliability of application systems. It is therefore possible to check the output data and the actual pin status as required. If there is a mismatch, appropriate action can be taken, such as replacement with another system. Special instructions, CHKL and CHKLA, are provided to check the port status. These instructions perform a comparison by taking the exclusive OR of the pin status and the output latch contents (in port mode), or the pin status and the internal control output signal level (in control mode). Example An example of a program that checks the pin status and output latch contents using the CHKL instruction and CHKLA instruction is as follows. TEST : SET1 CHKL BNE . . . ERR1 : CHKLA BT BT . . . BT BR A.1, $BIT01 $BIT00 ; Bit 1? ; If none of the bits, bit 0 is faulty P0 A.7, $BIT07 A.6, $BIT06 ; Faulty bit check ; Bit 7? ; Bit 6? P0.3 P0 $ ERR1 ; Set bit 3 of port 0 ; Check port 0 ; Branch to error processing (ERR1) in case of mismatch with output latch contents
Cautions 1. If each port is set to input mode, a comparison of the pin status with the output latch contents (or control output level) using the CHKL or CHKLA instruction will always show a match whether the individual pins of the port are port pins or control pins. Therefore, executing these instructions on a port set to input mode is actually ineffective. 2. If the output levels of a port in which control outputs and port outputs are mixed in a single port are checked with the CHKL or CHKLA instruction, the input/output mode of control output pins should be set to input mode before executing these instructions (as the output levels of control outputs vary asynchronously, the output level cannot be checked with the CHKL or CHKLA instruction). 3. As port 2 is an input-only port, a comparison of the pin status with the output latch contents using the CHKL or CHKLA instruction will always show a match. Therefore, executing these instructions on port 2 is actually ineffective.
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6.13 Cautions (1) All port pins become high-impedance after RESET signal input (on-chip pull-up resistors are disconnected from the pins). If there is a problem with pins becoming high-impedance during RESET input, this should be handled with external circuitry. (2) Bit 7 of the pull-up resistor option register (PUO) that sets the on-chip pull-up resistor connection is fixed at 0, but if "1" is written to bit 7 of the PUO in the in-circuit emulator, "1" will be read. (3) Output latch contents are not initialized by RESET input. When a port is used as an output port, the output latch must be initialized without fail before turning on the output buffer. If the output latch is not initialized before turning on the output buffer, unexpected data will be output to the output port. Similarly, for pins used as control pins, internal peripheral hardware initialization must be performed before performing the control pin specification. (4) As P22 to P26 are not pulled up immediately after a reset, an interrupt request flag may be set depending on the function of the alternate-function pins (INTP1 to INTP5). Therefore, the interrupt request flags should be cleared after specifying pull-up in the initialization routine. (5) When P40 to P47 and P50 to P57 are used as the address/data bus and address bus respectively in the PD784938, bits PUO4 and PUO5 of the pull-up resistor option register (PUO) must be set to "0" so that on-chip pull-up resistor connection is not performed. (6) A voltage outside the range AVSS to AVREF must not be applied to pins for which P70 to P77 are used as ANI0 to ANI7. See 16.6 Cautions in CHAPTER 16 A/D CONVERTER for details. (7) A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins or port mode and control mode, the contents of the output latch of pins specified as inputs or pins specified as in control mode will be undefined (excluding bits manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits which are switched between input and output. Caution is also required when manipulating the port with other 8-bit arithmetic instructions. (8) If each port is set to input mode, a comparison of the pin status with the output latch contents (or control output level) using the CHKL or CHKLA instruction will always show a match whether the individual pins of the port are port pins or control pins. Therefore, executing these instructions on a port set to input mode is actually ineffective. (9) If the output levels of a port in which control outputs and port outputs are mixed in a single port are checked with the CHKL or CHKLA instruction, the input/output mode of control output pins should be set to input mode before executing these instructions (as the output levels of control outputs vary asynchronously, the output level cannot be checked with the CHKL or CHKLA instruction). (10) As port 2 is an input-only port, a comparison of the pin status with the output latch contents using the CHKL or CHKLA instruction will always show a match. Therefore, executing these instructions on port 2 is actually ineffective.
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CHAPTER 7 REAL-TIME OUTPUT FUNCTION
7.1 Configuration and Function The real-time output function is implemented by hardware, including primarily port 0 and the port 0 buffer registers (P0H, P0L), shown in Figure 7-1. The real-time output function refers to the transfer to the output latch by hardware of data prepared in the P0H and P0L beforehand, simultaneously with the generation of an interrupt from timer/event counter 1 or external interrupt, and its output off-chip. The pins that output the data off-chip are called real-time output ports. The following two kinds of real-time output data are handled: * 4 bits x 2 channels * 8 bits x 1 channel By combining the real-time output function with the macro service function described later, the functions of a pattern generator with programmable timing are implemented without software intermediation. This is ideally suited to stepping motor control, for example. Figure 7-1 shows the block diagram of the real-time output port.
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202
RTPC BYTE P0MH EXTR TRGP0 P0ML INTC11 P0MH INTP0 INTC10
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Figure 7-1. Real-Time Output Port Block Diagram
Internal bus
4
4
Port 0 buffer registers BYTE 4-bit real-time output (P0H) 8 Selector Selector 4-bit real-time output (P0L) 8-bit real-time output (P0) EXTR TRGP0 P0ML 4 4 P0H P0L
CHAPTER 7 REAL-TIME OUTPUT FUNCTION
Output latch P0
P07 P06 P05 P04
P03 P02 P01 P00
CHAPTER 7 REAL-TIME OUTPUT FUNCTION
7.2 Real-time Output Port Control Register (RTPC) RTPC is an 8-bit register that specifies the function of port 0. RTPC can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. Figure 7-2 shows the format of RTPC. RESET input clears RTPC to 00H. Figure 7-2. Real-Time Output Port Control Register (RTPC) Format
7 RTPC BYTE
6 0
5 0
4 P0MH
3 EXTR
2 0
1
0
Address 0FF2EH
After reset 00H
R/W R/W
TRGP0 P0ML
P0ML 0 1
P00 to P03 Function Specification Port mode Real-time output port mode
EXTR TRGP0 0 1 0 0
Enabling of Data Transfer to Output Latch from P0H, P0L by INTP0 Not enabled (data transfer by INTC10 only) Transfer by either INTP0 or INTC10 Enabled * BYTE = 0: P0L only transferred * BYTE = 1: P0L/P0H transferred
1
1
Transfer by INTP0 only
0
1
Setting prohibited
P0MH 0 1
P04 to P07 Function Specification Port mode Real-time output port mode
BYTE 0 1
Real-Time Output Port Operating Mode 4-bit separate real-time output port 8-bit real-time output port
Caution When P0ML and P0MH bits are set (to 1), the corresponding port output buffer is turned on and the port 0 output latch contents are output irrespective of the contents of the port 0 mode register (PM0). The output latch contents should therefore be initialized before making a real-time output port specification.
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7.3 Real-time Output Port Accesses The port 0 buffer registers (P0H, P0L) are mapped onto mutually independent addresses in the SFR area as shown in Figure 7-3. When the 4-bit x 2-channel real-time output function is specified, data can be set in the P0H, P0L independently of each other. When the 8-bit x 1-channel real-time output function is specified, data can be set in P0H and P0L by writing 8-bit data to either one of the P0H or P0L. Table 7-1 shows the operations when port 0, the P0H and P0L are manipulated. Figure 7-3. Port 0 Buffer Register (P0H, P0L) Configuration
High-order 4 bits Low-order 4 bits 0FF0EH 0FF0FH P0H P0L
Table 7-1. Operations when Port 0 and Port 0 Buffer Registers (P0H, P0L) are Manipulated
Operation Mode Register Read Operation High-Order 4 Bits 8-bit port mode P0 P0L P0H 8-bit real-time output port mode P0 P0L P0H 4-bit separate real-time output port mode P0 P0L P0H P00 to P03: Ports P04 to P07: Real-time output port mode P00 to P03: Real-time output port mode P04 to P07: Ports P0 P0L P0H P0 P0L P0H Output latch Buffer registerNote Buffer registerNote Low-Order 4 Bits Write Operation High-Order 4 Bits Output latch -- Buffer register -- Buffer register Buffer register -- -- Buffer register -- -- Buffer register Output latch
Note
Low-Order 4 Bits
Buffer register --
Output latch Buffer register Buffer register Output latch Buffer registerNote
Buffer register -- Output latch Buffer register -- -- Buffer register --
Buffer registerNote Output latch Buffer registerNote
Buffer registerNote Output latch Buffer register Buffer
-- Buffer register
registerNote
Note The contents of P0H are read from the high-order 4 bits, and the contents of P0L from the low-order 4 bits. Remark -- : The output latch and port 0 buffer registers are not affected.
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* 4-bit x 2-channel operation MOV P0L, #05H ; Sets 0101B in P0L ; Sets 1100B in P0H
MOV P0H, #0C0H
* 8-bit x 1-channel operation MOV P0L, or MOV P0H, #0C5H The timing for transfer to the output latch can be determined by the following three sources: * Interrupt from timer/event counter 1 (INTC10 or INTC11) * INTP0 external interrupt #0C5H ; Sets 0101B in P0L and 1100B in P0H
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7.4 Operation When the port 0 function is specified as the real-time output port, the port 0 buffer register (P0H, P0L) contents are fetched into the output latch and output to the port 0 pins in synchronization with the generation of one of the trigger conditions shown in Table 7-2. For example, the timer/event counter 1 timer counter 1 (TM1) and compare register (CR10, CR11) match signal (INTC10, INTC11) can be selected as the output trigger generation source. In this case, the port 0 pin output data can be changed to the P0H and P0L values using the value set in the CR10, CR11 beforehand as the timing interval. Combining this real-time output port function with the macro service function enables the port 0 output pin output data to be changed sequentially at any interval time (see 23.8 Macro Service Function). If the INTP0 external interrupt pin is selected as the output trigger source, port 0 output can be obtained in synchronization with an external event. Table 7-2. Real-Time Output Port Output Triggers (when P0MH = P0ML = 1)
RTPC BYTE 0 0 0 1 1 1 EXTR 0 1 1 0 1 1 TRGP0 0 0 1 0 0 1 8-bit real-time output 4-bit real-time output INTC11 INTC11 INTC11 INTC10 INTC10 or INTP0 INTP0 INTC10 INTC10 or INTP0 INTP0 Output Mode P0H P0L
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Figure 7-4. Real-Time Output Port Operation Timing
FFH
CR11 Timer/event counter 1 CR11
CR11 0H Timer start INTC11 interrupt request
CR11
CPU operation
Port 0 buffer register P0H
D01
D02
D03
D04
Output latches P07 to P04
D00
D01
D02
D03
Port 0 buffer register and compare register overwrite by software servicing or macro service (see 23.8 MACRO SERVICE FUNCTION)
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Figure 7-5. Real-Time Output Port Operation Timing (2-channel independent control example)
FFH CR10 CR11 Timer/event counter 1 CR11 CR10 CR11 0H Timer start INTC11 interrupt request INTC10 interrupt request CR11 CR10
CPU operation
Port 0 buffer register P0H
D01
D02
D03
D04
P0L
D11
D12
D13
D14
Output latches P07 to P04
D00
D01
D02
D03
P03 to P00
D10
D11
D12
D13
Port 0 buffer register and compare register overwrite by software servicing or macro service (see 23.8 MACRO SERVICE FUNCTION)
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7.5 Example of Use The case in which P00 to P03 are used as a 4-bit real-time output port is shown here. Each time the contents of timer/event counter 1 timer counter 1 (TM1) and compare register (CR10) match, the contents of port 0 buffer register (P0L) are output to P00 to P03. At this time, the next data to be output and the timing at which the output is to be changed next are set in the service routine for the simultaneously generated interrupt (see Figure 7-6). See CHAPTER 10 TIMER/EVENT COUNTER 1 for the method of using timer/event counter 1. The control register settings are shown in Figure 7-7, the setting procedure in Figure 7-8, and the processing in the interrupt service routine in Figure 7-9. Figure 7-6. Real-Time Output Port Operation Timing
FFH
CR10 Timer/event counter 1 CR10
CR10 0H
CR10
INTC10 interrupt request
Port 0 buffer register P0L
D01
D02
D03
D04
Output latches P00 to P03
D00
D01
D02
D03
Output pins Hi-Z P00 to P03
D00
D01
D02
D03
P0L and CR10 overwritten by INTC10 interrput P0L contents transferred to output latch on match of TM1 and CR10 Timer start Output buffer turned on Next data to be output is set in P0L Initial output data is set in output latches P00 to P03
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Figure 7-7. Real-Time Output Function Control Register Settings
7 RTPC 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
P00 to P03 used as real-time output port
Data transfer to output latch from P0L by INTP0 disabled P04 to P07 used as normal output port 4-bit separate real-time output ports selected
Figure 7-8. Real-Time Output Function Setting Procedure
Real-time output port
Set initial value in P0 output latch
Set next value to be output in P0L
Set real-time output port control register (RTPC)
Set timer/event counter 1
Timer start
INTC10 interrupt
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Figure 7-9. Interrupt Request Servicing when Real-Time Output Function is Used
Timer interrupt
Interval time setting
Set next value to be output in P0L
Return
7.6 Cautions (1) When P0ML and P0MH bits are set (to 1), the corresponding port output buffer is turned on and the port 0 output latch contents are output irrespective of the contents of the port 0 mode register (PM0). The output latch contents should therefore be initialized before making a real-time output port specification. (2) When the port is specified as a real-time output port, values cannot be directly written to the output latch by software. Therefore, the initial value of the output latch must be set by software before specifying use as a real-time output port. Also, if the need arises to forcibly set the output data to a fixed value while the port is being used as a real-time output port, you should change the port to a normal output port by manipulating the real-time output port control register (RTPC), then write the value to be output to the output latch.
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CHAPTER 8 OUTLINE OF TIMER
The PD784938 incorporates three timer/event counter units and one timer unit. These timer/event counter and timer units can be used as seven units of timer/event counters because the PD784938 supports seven interrupt requests. Table 8-1. Operations of Timer
Name Item Count width 8 bits 16 bits Timer/Event Counter 0 -- 2 ch -- 2 ch -- 1 input 2 Timer/Event Counter 1 2 ch -- -- -- -- -- 1 input 2 Timer/Event Counter 2 2 ch 2 ch -- -- 2 inputs 2 Timer 3 1 ch -- -- -- -- -- -- -- -- 1
Operation Interval timer mode External event counter One-shot timer Function Timer output Toggle output PWM/PPG output One-shot pulse outputNote Real-time output Pulse width measurement Number of interrupt requests
Note
In the one-shot pulse output function, the pulse output level activated by software and inactivated by hardware (an interrupt request signal). This function is different in nature from the one-shot timer function of timer/event counter 2.
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Figure 8-1. Timer Block Diagram Timer/Event Counter 0
Clear control fXX/4 Prescaler Timer counter 0 (TM0) Compare register (CR00) Compare register (CR01) INTP3 Edge detection INTP3 Capture register (CR02) Match Pulse output control Software trigger
Selector
OVF
TO0
Match
TO1
INTC00 INTC01
Timer/Event Counter 1
Clear control Timer counter 1 (TM1/TM1W) Compare register (CR10/CR10W) Match
fXX/4
Prescaler
Selector
OVF
Event input Edge detection
INTP0
INTP0
Capture/compare register Match (CR11/CR11W) Capture register (CR12/CR12W)
INTC10 To real-time output port INTC11
Timer/Event Counter 2
Clear control Timer counter 2 (TM2/TM2W) Compare register (CR20/CR20W) INTP2 Match Pulse output control
fXX/4
Prescaler
Selector
OVF
INTP2/CI
Edge detection
TO2
Capture/compare register Match (CR21/CR21W) Capture register (CR22/CR22W)
TO3
INTP1
Edge detection
INTP1
INTC20 INTC21
Timer 3
fXX/4 Prescaler Timer counter 3 (TM3/TM3W) Compare register (CR30/CR30W) Match UART, CSI Match INTC30
Remark OVF: Overflow flag
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CHAPTER 9 TIMER/EVENT COUNTER 0
9.1 Functions Timer/event counter 0 is a 16-bit timer/event counter. In addition to its basic functions of interval timer, programmable square-wave output, pulse width measurement and event counter, timer/event counter 0 can be used for the following functions. * PWM output * Cycle measurement * Soft triggered one-shot pulse output (1) Interval timer Generates internal interrupts at preset intervals. Table 9-1. Timer/Event Counter 0 Interval Time
Minimum Interval Time 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s) Maximum Interval Time 216 x 4/fXX (20.8 ms) 216 x 8/fXX (41.7 ms) 216 x 16/fXX (83.4 ms) 216 x 32/fXX (167 ms) 216 x 64/fXX (333 ms) 216 x 128/fXX (667 ms) 216 x 256/fXX (1.33 s) 216 x 512/fXX (2.67 s) 216 x 1,024/fXX (5.33 s) Resolution 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.20 s) 1,024/fXX (81.40 s)
( ): When fXX = 12.58 MHz
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(2) Programmable square-wave output Outputs square waves independently to the timer output pins (TO0, TO1). Table 9-2. Timer/Event Counter 0 Programmable Square-Wave Output Setting Range
Minimum Pulse Width 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s) Maximum Pulse Width 216 x 4/fXX (20.8 ms) 216 x 8/fXX (41.7 ms) 216 x 16/fXX (83.4 ms) 216 x 32/fXX (167 ms) 216 x 64/fXX (333 ms) 216 x 128/fXX (667 ms) 216 x 256/fXX (1.33 s) 216 x 512/fXX (2.67 s) 216 x 1,024/fXX (5.33 s)
( ): When fXX = 12.58 MHz
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(3) Pulse width measurement Detects the pulse width of the signal input to the external interrupt request input pin (INTP3). Table 9-3. Timer/Event Counter 0 Pulse Width Measurement Range
Measurable Pulse WidthNote to 4/fXX (0.32 s) 8/fXX to (0.64 s) 16/fXX to (1.27 s) 32/fXX to (2.54 s) 64/fXX to (5.09 s) 128/fXX to (10.17 s) 256/fXX (20.35 s) 512/fXX to (40.70 s) to 2 x 4/fXX (20.8 ms)
16
Resolution 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s)
216 x 8/fXX (41.7 ms) 216 x 16/fXX (83.4 ms) 216 x 32/fXX (167 ms) 216 x 64/fXX (333 ms) 216 x 128/fXX (667 ms) 216 x 256/fXX (1.33 s) 216 x 512/fXX (2.67 s)
1,024/fXX to 216 x 1,024/fXX (81.40 s) (5.33 s)
( ): When fXX = 12.58 MHz Note The minimum pulse width that can be measured differs depending on the selected value of fCLK. The minimum pulse width that can be measured is the value of 3/fCLK or the value in the above table, whichever is greater. (4) Software triggered one-shot pulse output This is a one-shot pulse output function in which the pulse output level is activated by software and inactivated by hardware (an interrupt request signal). Control can be performed for the timer output pins (TO0, TO1) independently. Caution The software triggered one-shot pulse output function is different in nature from the one-shot timer function of timer/event counter 2.
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(5) External event counter Counts the clock pulses input from the external interrupt request input pin (INTP3). The clocks that can be input to timer/event counter 0 are shown in Table 9-4. Table 9-4. Timer/Event Counter 0 Pulse Width Measurement Time
When Counting One Edge Maximum frequency Minimum pulse width (High and low levels) fCLK/6 (2.10 MHz) 3/fCLK (0.24 s) When Counting Both Edges fCLK/6 (2.10 MHz) 3/fCLK (0.24 s)
( ): When fCLK = 12.58 MHz 9.2 Configuration Timer/event counter 0 consists of the following registers: * Timer counter (TM0) x 1 * Compare register (CR00, CR01) x 2 * Capture register (CR02) x 1 The block diagram of timer/event counter 0 is shown in Figure 9-1.
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Figure 9-1. Timer/Event Counter 0 Block Diagram
Internal bus Capture/compare control register 0 (CRC0) CLR01
1/8 External interrupt mode register 1 (INTM1) P24/INTP3 ES31 ES30
8/16 Compare register (CR00) 16
8
1/8 Timer output control register (TOC)
MOD1 MOD0
ENT01 ALV1 ENT00 ALV0
Edge detection circuit
16 Match 16
PWM/PPG output control
Output control circuit
P34/TO0
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INTC00 Compare register (CR01) 16 fXX/1,024 fXX/512 fXX/256 fXX/128 fXX/64 fXX/32 fXX/16 fXX/8 fXX/4 16 16 Selector Timer counter 0 (TM0) Capture trigger 16 Prescaler mode register 0 (PRM0) PRS03 PRS02 PRS01 PRS00 8 Capture register (CR02) 16 16 Internal bus Timer control register 0 (TMC0) Clear Overflow RESET Output control circuit
P35/TO1
fXX
Prescaler
INTC01
CE0 OVF0
ST1
RT1
OS1 ST0 1/8
RT0 OS0
1/8
One-shot pulse control register (OSPC)
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(1) Timer counter 0 (TM0) TM0 is a timer counter that counts up using the count clock specified by the low-order 4 bits of prescaler mode register 0 (PRM0). The count operation is stopped or enabled by means of timer control register 0 (TMC0). TM0 can be read only with a 16-bit manipulation instruction. When RESET is input, TM0 is cleared to 0000H and the count is stopped. (2) Compare registers (CR00/CR01) CR00 and CR01 are 16-bit registers that hold the values that determine the interval timer frequency. If the CR00/CR01 contents match the contents of TM0, an interrupt request (INTC00/INTC01) and timer output control signal are generated. Also, the count value can be cleared by a content match (CR01). CR00 and CR01 can be read or written with a 16-bit manipulation instruction. The contents of these registers are undefined after RESET input. (3) Capture register (CR02) CR02 is a 16-bit register that captures the contents of TM0. The capture operation is synchronized with the input of a valid edge (capture trigger) on the external interrupt request input pin (INTP3). The contents of the CR02 are retained until the next capture trigger is generated. CR02 can be read only with a 16-bit manipulation instruction. The contents of this register are undefined after RESET input. (4) Edge detection circuit The edge detection circuit detects an external input valid edge. When the valid edge set by external interrupt mode register 1 (INTM1) is detected in the INTP3 pin input, the external interrupt request (INTP3), a capture trigger, and a external event count clock are generated (see Figure 22-2 for details of the INTM1). (5) Output control circuit It is possible to invert the timer output when the compare register (CR00, CR01) register contents and the contents of the timer counter (TM0) match. A square wave can be output from the timer output pins (TO0/TO1) in accordance with the setting of the low-order 4 bits of the timer output control register (TOC). At this time, PWM output or PPG output can be performed according to the specification of capture/compare control register 0 (CRC0). In addition, one-shot pulse output can also be performed by means of a software trigger. Timer output can be disabled/enabled by means of the TOC. When timer output is disabled, a fixed level is output to the TO0 and TO1 pins (the output level is set by the TOC). (6) Prescaler The prescaler generates the count clock from the internal system clock. The clock generated by this prescaler is selected by the selector, and is used as the count clock by the timer counter 0 (TM0) to perform count operations. (7) Selector The selector selects a signal resulting from dividing the internal clock or the edge detected by the edge detection circuit as the count clock of timer counter 0 (TM0).
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9.3 Timer/Event Counter 0 Control Registers (1) Timer control register 0 (TMC0) The timer/event counter 0 TM0 count operation is controlled by the low-order 4 bits in the TMC0 (the high-order 4 bits control the count operation of the TM3/TM3W of the timer 3). TMC0 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The format of TMC0 is shown in Figure 9-2. RESET input clears TMC0 to 00H. Figure 9-2. Timer Control Register 0 (TMC0) Format
7 TMC0 CE3
6 0
5 0
4 BW3
3 CE0
2 OVF0
1 0
0 0
Address 0FF5DH
After reset 00H
R/W R/W
OVF0 0 1
TM0 Overflow Flag No overflow Overflow (count up from FFFFH to 0000H)
CE0 0
TM0 Count Operation Control Count operation stopped with count cleared Count operation enabled
1
Countrols count operation of the TM3/TM3W of the timer 3 (see Figure 12-2).
Remark The OVF0 bit is reset by software only.
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(2) Prescaler mode register 0 (PRM0) The count clock of the timer/event counter 0 TM0 is specified by the low-order 4 bits of PRM0 (the high-order 4 bits specify the count clock of the timer 3, TM3/TM3W). PRM0 can be read/written with an 8-bit manipulation instruction. The format of PRM0 is shown in Figure 9-3. RESET input sets PRM0 to 11H. Figure 9-3. Prescaler Mode Register 0 (PRM0) Format
7 6 5 4 3 2 1 0 Address 0FF5CH After reset 11H R/W R/W
PRM0 PRS3 PRS2 PRS1 PRS0 PRS03 PRS02 PRS01 PRS00
(fXX = 12.58 MHz) PRS03 PRS02 PRS01 PRS00 Timer/Event Counter 0 TM0 Count Clock Specification Count Clock [Hz] Specification 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 Setting prohibited fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 External clock (INTP3) Setting prohibited Resolution [ s] - 0.32 0.64 1.27 2.54 5.09 10.17 20.35 40.70 81.40 -
Other than the above
Specifies count clock of the TM3/TM3W of the timer 3 (see Figure 12-3).
Remark fXX: X1 input frequency or oscillation frequency
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(3) Capture/compare control register 0 (CRC0) CRC0 specifies the enabling conditions for the TM0 clear operation by a match signal between the contents of the compare register (CR01) and the timer counter 0 (TM0) counter value, and the timer outputs (TO0/TO1) mode. CRC0 can be read/written with an 8-bit manipulation instruction. The format of CRC0 is shown in Figure 9-4. RESET input sets CRC0 to 10H. Figure 9-4. Capture/Compare Control Register 0 (CRC0) Format
7 CRC0
6
5 0
4 1
3 CLR01
2 0
1 0
0 0
Address 0FF30H
After reset 10H
R/W R/W
MOD1 MOD0
MOD1 MOD0 CLR01
Timer Output Mode Specification TO0 TO1
TM0 Clear Opration when TM0 = CR01 Disabled Enabled Disabled
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Toggle output Toggle output Toggle output Toggle output PWM output Toggle output
Setting prohibited PWM output PWM output Disabled
Setting prohibited Setting prohibited PPG output Toggle output Enabled
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(4) Timer output control register (TOC) TOC is an 8-bit register that controls the active level of timer output and output enabling/disabling. The operation of the timer output pins (TO0/TO1) by the timer/event counter 0 is controlled by the low-order 4 bits (the highorder 4 bits control the operation of the timer output pins (TO2/TO3) by the timer/event counter 2). TOC can be written to or read with an 8-bit manipulation instruction or bit manipulation instruction. The format of TOC is shown in Figure 9-5. RESET input clears TOC to 00H. Figure 9-5. Timer Output Control Register (TOC) Format
7 TOC
6
5
4
3
2
1
0
Address 0FF31H
After reset 00H
R/W R/W
ENTO3 ALV3 ENTO2 ALV2 ENTO1 ALV1 ENTO0 ALV0
ALV0
TO0 Pin Active Level Toggle output specification or one-shot pulse output specificaton PWM/PPG output specification High level Low level
0 1
Low level High level
ENTO0 0 1
TO0 Pin Operation Specification ALV0 output Pulse output enabled
ALV1
TO1 Pin Active Level Toggle output specification or one-shot pulse output specificaton PWM/PPG output specification High level Low level
0 1
Low level High level
ENTO1 0 1
TO1 Pin Operation Specification ALV1 output Pulse output enabled
Countrol timer output pins (TO2/TO3) by timer/ event counter 2 (see Figure 11-5).
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(5) One-shot pulse output control register (OSPC) OSPC is an 8-bit register that specifies enabling/disabling of one-shot pulse output by a software trigger and the output level, etc. OSPC can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The format of OSPC is shown in Figure 9-6. RESET input clears OSPC to 00H. Figure 9-6. One-Shot Pulse Output Control Register (OSPC) Format
7 OSPC ST1
6 RT1
5 0
4 OS1
3 ST0
2 RT0
1 0
0 OS0
Address 0FF7DH
After reset 00H
R/W R/W
OS0 0 1
TO0 Pulse Output Type Selection Toggle output/PWM output/PPG output selectable Software triggerd one-shot pulse selectable
ST0 0 0 1 1
RT0 0 1 0 1
TO0 Output Control Output not changed Inactive level output to TO0 Active level output to TO0 Setting prohibited
OS1 0 1
TO1 Pulse Output Type Selection Toggle output/PWM output/PPG output selectable Software triggerd one-shot pulse output
ST1 0 0 1 1
RT1 0 1 0 1
TO1 Output Control Output not changed Inactive level output to TO1 Active level output to TO1 Setting prohibited
Remarks 1. The RT0, ST0, RT1, and ST1 bits are write-only, and show a value of "0" if read. 2. Pin pulse output disabling/enabling and active level setting are performed by means of the timer output control register (TOC).
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9.4 Timer Counter 0 (TM0) Operation 9.4.1 Basic operation In the timer/event counter 0 count operation, an count-up is performed using the count clock specified by the low-order 4 bits of prescaler mode register 0 (PRM0). Count operation enabling/disabling is controlled by bit 3 (CE0) of timer control register 0 (TMC0). When the CE0 bit is set (to 1) by software, the contents of TM0 are cleared to 0000H on the first count clock, and then the count-up operation is performed. When the CE0 bit is cleared (to 0), TM0 becomes 0000H immediately, and capture operations and match signal generation are stopped. If the CE0 bit is set (to 1) again when it is already set (1), TM0 continues the count operation without being cleared. If the count clock is input when TM0 is FFFFH, TM0 becomes 0000H. In this case, OVF0 bit is set (to 1) and an overflow signal is sent to the output control circuit. OVF0 bit is cleared by software only. The count operation is continued. When RESET is input, TM0 is cleared to 0000H, and the count operation is stopped.
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Figure 9-7. Basic Operation of Timer Counter 0 (TM0) (a) Count started count stopped count started
Count clock fCLK/8
TM0
0H
0H
1H
2H
FFH
100H 101H
0H
0H
1H
CE0
Count started CE0 1
Count stopped CE0 0
Count started CE0 1
(b) When "1" is written to the CE0 bit again after the count starts
Count clock fCLK/8
TM0
0H
0H
1H
2H
3H
4H
5H
6H
CE0
Count started CE0 1
Rewrite CE0 1
(c) Operation when TM0 = FFFFH
Count clock fCLK/8
TM0
FFFEH FFFFH
0H
1H
OVF0
Cleared by software OVF0 0
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9.4.2 Clear operation (1) Clear operation after a match with the compare register The timer counter 0 (TM0) can be cleared automatically after a match with the compare register (CR01). When a clearance source arises, TM0 is cleared to 0000H on the next count clock. Therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. Figure 9-8. TM0 Clearance by Match with Compare Register (CR01)
Count clock
TM0
n-1
n
0
1
Compare register (CR01)
n
TM0 and CR01 match
Cleared here
(2) Clear operation by the CE0 bit of the timer control register 0 (TMC0) The timer counter 0 (TM0) is also cleared when the CE0 bit of TMC0 is cleared (to 0) by software. The clear operation is performed immediately after clearance (to 0) of the CE0 bit.
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Figure 9-9. Clear Operation when CE0 Bit is Cleared (0) (a) Basic operation
Count clock
TM0
n-1
n
0
CE0
(b) Restart before count clock input after clearance
Count clock
TM0
n-1
n
0
0
1
2
CE0
If the CE0 bit is set (to 1) before this count clock, the count starts from 0 on the count clock.
(c) Restart after count clock input after clearance
Count clock
TM0
n-1
n
0
0
0
1
CE0
If the CE0 bit is set (to 1) from this count clock onward, the count starts from 0 on the count clock after the CE0 bit is set (to 1).
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9.5 External Event Counter Function The timer/event counter 0 can count clock pulses input from the external interrupt request input pin (INTP3). No special selection method is needed for the external event counter operation mode. When the timer counter 0 (TM0) count clock is specified as external clock input by the setting of the low-order 4 bits of prescaler mode register 0 (PRM0), TM0 operates as an external event counter. The maximum frequency of external clock pulses that can be counted by TM0 as the external event counter is 2.10 MHz (fCLK = 12.58 MHz) irrespective of whether only one edge or both edges are counted on INTP3 input. The pulse width of the INTP3 input must be at least 3 system clocks (0.24 s: fCLK = 12.58 MHz) for both the high level and low level. If the pulse width is shorter than this, the pulse may not be counted. The timer/event counter 0 external event counter timing is shown in Figure 9-10. Figure 9-10. Timer/Event Counter 0 External Event Count Timing (1) Counting one edge (maximum frequency = fCLK/6)
3/fCLK (MIN.) 3/fCLK (MIN.)
6/fCLK (MIN.)
INTP3 2-3/fCLK
ICI
TM0
Dn
Dn+1
Dn+2
Dn+3
Remark
ICI: INTP3 input signal after passing through edge detection circuit
(2) Counting both edges (maximum frequency = fCLK/6)
3/fCLK (MIN.) INTP3
3/fCLK (MIN.)
6/fCLK (MIN.)
2-3/fCLK
ICI
TM0
Dn
Dn+1
Dn+2
Dn+3
Dn+4
Dn+5
Remark ICI: INTP3 input signal after passing through edge detection circuit
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The TM0 count operation is controlled by the CE0 bit of the timer control register 0 (TMC0) in the same way as with basic operation. When the CE0 bit is set (to 1) by software, the contents of TM0 are set to 0000H and the count-up is started on the initial count clock. When the CE0 bit is cleared (to 0) by software during a TM0 count operation, the contents of TM0 are set to 0000H immediately and the stopped state is entered. The TM0 count operation is not affected if the CE0 bit is set (to 1) by software again when it is already set (to 1). Caution When timer/event counter 0 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input, using the timer counter 0 (TM0) alone (see Figure 9-11), since the contents of TM0 are 0 in both cases. If it is necessary to make this distinction, the INTP3 interrupt request flag should be used. An example is shown in Figure 9-12. Figure 9-11. Example of the Case where the External Event Counter does Not Distinguish between One Valid Edge Input and No Valid Edge Input
INTP3
TM0
0
0
1
2
No distinction made Count start
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Figure 9-12. To Distinguish whether One or No Valid Edge has been Input with External Event Counter (a) Processing when count is started
Start count
Clear INTP3 interrupt request flag PIF3 0
; Clear PIF3 to 0
Start count CE0 1
; Set CE0 to 1
End
(b) Processing when count value is read
Count value read
Read TM0 contents AX TM0
AX = 0?
YES ; Check TM0 value If 0, check interrupt request flag YES PIF3 = 1? NO ; Check PIF3 contents If 1, there is a valid edge
NO
AX AX+1
End
; Number of input valid edges is set in AX register
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9.6 Compare Register and Capture Register Operation 9.6.1 Compare operations Timer/event counter 0 performs compare operations in which the value set in compare registers (CR00, CR01) are compared with the timer counter 0 (TM0) count value. If the count value of TM0 matches the preset CR0n (n = 0, 1) value as the result of the count operation, a match signal is sent to the output control circuit, and at the same time an interrupt request (INTC00/INTC01) is generated. After a match with the CR01 value, the TM0 count value can be cleared, and the timer functions as an interval timer that repeatedly counts up to the value set in the CR01. Figure 9-13. Compare Operation
FFFFH
FFFFH
TM0 Count value CR01 value CR01 value
CR00 value 0H Count start CE0 1 INTC00 interrupt request Match Match
CR00 value Match Match
INTC01 interrupt request
OVF0
Cleared by software
Remark CLR01 = 0
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Figure 9-14. TM0 Clearance After Match Detection
CR01
CR01
TM0 Count value
CR00
CR00
0H Count start CE0 1 Clear Clear
INTC00 interrupt request
INTC01 interrupt request
Remark CLR01 = 0
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9.6.2 Capture operations Timer/event counter 0 performs capture operations in which the timer counter 0 (TM0) count value is fetched into the capture register in synchronization with an external trigger, and retained there. A valid edge detected from the input of the external interrupt request input pin (INTP3) is used as the external trigger (capture trigger). The count value of TM0 in the process of being counted is fetched into the capture register (CR02) in synchronization with the capture trigger, and is retained there. The contents of the CR02 are retained until the next capture trigger is generated. The capture trigger valid edge is set by means of external interrupt mode register 1 (INTM1). If both rising and falling edges are set as capture triggers, the width of pulses input from off-chip can be measured. Also, if a capture trigger is generated by a single edge, the input pulse cycle can be measured. See Figure 22-2 for details of the INTM1. Figure 9-15. Capture Operation
FFFFH
TM0 count value D1
D0 0H Count start CE0 1 INTP3 pin input
D2
INTP3 interrupt request
Capture register (CR02)
D0
D1
D2
OVF0
Remark Dn: TM0 count value (n = 0, 1, 2, ...) CLR01 = 0
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9.7 Basic Operation of Output Control Circuit The output control circuit controls the timer output pin (TO0/TO1) levels by means of overflow signals or match signals from the compare registers (CR00, CR01). The operation of the output control circuit is determined by the timer output control register (TOC), capture/compare control register 0 (CRC0), and the one-shot pulse output control register (OSPC) (see Table 9-5). When TO0, TO1 signals are output to a pin, the relevant pin must be in control mode in the port 3 mode register (PMC3).
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Table 9-5. Timer Output (TO0/TO1) Operations
TOC ENTO1 0 0 0 0 0 0 1
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OSPC ALV0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 OS1 x x x x x x 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 OS0 x 0 0 0 0 1 x x x x 0 0 0 0 1 1 1 0 0 0 0 1 MOD1 x 0 0 1 1 x 0 1 1 x 0 0 1 1 0 1 1 0 0 1 1 x
CRC0 MOD0 x 0 1 0 1 x x 0 1 x 0 1 0 1 x 0 1 0 1 0 1 x CLR01 x x 0 0 1 x x 0 x x x 0 0 1 x 0 1 x 0 0 1 x
TO1
TO0
ALV1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
ENTO0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
High/low level fixed High/low level fixed High/low level fixed High/low level fixed High/low level fixed High/low level fixed Toggle output (active-low/high) PWM output (active-high/low) Toggle output (active-low/high) One-shot pulse output (active-low/high) Toggle output (active-low/high) Toggle output (active-low/high) PWM output (active-high/low) Toggle output (active-low/high) Toggle output (active-low/high) PWM output (active-high/low) Toggle output (active-low/high) One-shot pulse output (active-low/high) One-shot pulse output (active-low/high) One-shot pulse output (active-low/high) One-shot pulse output (active-low/high) One-shot pulse output (active-low/high)
High/low level fixed Toggle output (active-low/high) PWM output (active-high/low) PWM output (active-high/low) PPG output (active-high/low) One-shot pulse output (active-low/high) High/low level fixed High/low level fixed High/low level fixed High/low level fixed Toggle output (active-low/high) PWM output (active-high/low) PWM output (active-high/low) PPG output (active-high/low) One-shot pulse output (active-low/high) One-shot pulse output (active-low/high) One-shot pulse output (active-low/high) Toggle output (active-low/high) PWM output (active-high/low) PWM output (active-high/low) PPG output (active-high/low) One-shot pulse output (active-low/high) CHAPTER 9 TIMER/EVENT COUNTER 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Remarks 1. In the ALVn (n = 0, 1) columns, the figures on the left and right of the slash ("/") correspond to the items on the left and right of the slash in the TOn (n = 0, 1) columns. 2. The "x" mark indicates that the operation is the same for either 0 or 1, but some prohibited combinations are included (see Figure 9-4). 3. Use with combinations not shown in this table is prohibited.
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9.7.1 Basic operation Setting (to 1) the ENTOn (n = 0, 1) bit of the timer output control register (TOC) enables timer output (TOn: n = 0, 1) to be varied at a timing in accordance with the settings of MOD0, MOD1, and CLR01 bits of capture/compare control register 0 (CRC0) and the one-shot pulse output control register (OSPC). Clearing (to 0) ENTOn sets the TOn to a fixed level. The fixed level is determined by the ALVn (n = 0, 1) bit of the TOC. The level is high when ALVn is 0, and low when 1. 9.7.2 Toggle output Toggle output is an operation mode in which the output level is inverted each time the compare register (CR00/CR01) value coincides with the timer counter 0 (TM0) value. The output level of timer output (TO0) is inverted by a match between CR00 and TM0, and the output level of TO1 is inverted by a match between CR01 and TM0. When timer/event counter 0 is stopped by clearing (to 0) the CE0 bit of the timer control register 0 (TMC0), the inactive level (ALVn: n = 0, 1) is output. Figure 9-16. Toggle Output Operation
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
TM0 count value
CR01 value CR00 value
CR01 value CR00 value
CR01 value CR00 value
CR01 value CR00 value
0H
ENTO0 Instruction execution TO0 output (ALV0 = 1) Instruction execution Instruction execution
ENTO1
Instruction execution TO1 output (ALV1 = 0)
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Table 9-6. TO0, TO1 Toggle Output (fXX = 12.58 MHz)
Count Clock fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 Minimum Pulse Width 0.32 s 0.64 s 1.27 s 2.54 s 5.09 s 10.17 s 20.35 s 40.70 s 81.40 s Maximum Interval Time 0.02 s 0.04 s 0.08 s 0.17 s 0.33 s 0.67 s 1.33 s 2.67 s 5.33 s
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9.7.3 PWM output (1) Basic operation of PWM output In this mode, a PWM signal with the period in which timer counter 0 (TM0) reaches a full count used as one cycle is output. The timer output (TO0) pulse width is determined by the value of compare register (CR00), and the timer output (TO1) pulse width is determined by the value of compare register (CR01). When this function is used, the CLR01 bit of capture/compare control register 0 (CRC0) must be set to 0. The pulse cycle and pulse width are as shown below. * PWM cycle = 65,536 x x/fXX * PWM pulse width = CR0n x x/fXXNote; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 Note 0 cannot be set in the CR0n. PWM pulse width PWM cycle CR0n 65,536
* Duty =
=
Remark n = 0, 1 Figure 9-17. PWM Pulse Output
FFFFH CR00 Timer count Count start 0H Interrupt CR00
FFFFH CR00
FFFFH
TO0 Pulse width Pulse cycle Pulse width Pulse cycle
Remark ALV0 = 0 Table 9-7. TO0, TO1 PWM Cycle (fXX = 12.58 MHz)
Count Clock fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 Minimum Pulse Width [s] 0.32 0.64 1.27 2.54 5.09 10.17 20.35 40.70 81.40 PWM Cycle [s] 0.02 0.04 0.08 0.17 0.33 0.67 1.33 2.67 5.33 PWM Frequency [Hz] 47.6 23.8 12.0 6.0 3.0 1.5 0.7 0.4 0.2
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Figure 9-18 shows an example of 2-channel PWM output, and Figure 9-19 shows the operation of the case where FFFFH is set in the CR00. Figure 9-18. Example of PWM Output Using TM0
FFFFH
FFFFH
FFFFH CR01
CR01 TM0 count value CR00 CR00 CR00
0H INTC00
INTC01 TO0
TO1
Remark ALV0 = 0, ALV1 = 0 Figure 9-19. Example of PWM Output when CR00 = FFFFH
FFFFH FFFEH
FFFFH FFFEH
FFFFH
Count clock cycle T TM0 count value 1 0 INTC00 0 2 1 0 2
OVF flag
TO0 Pulse width T . 65,535 x 100 = 99.998 (%) Duty =. 65,536
Pulse cycle = 65,536T
Remarks 1. ALV0 = 0 2. T = x/fXX (x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024)
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(2) Rewriting compare registers (CR00, CR01) The output level of the timer output (TOn: n = 0, 1) does not change even if the CR0n (n = 0, 1) value matches the timer counter 0 (TM0) value more than once during one PWM output cycle. Figure 9-20. Example of Compare Register (CR00) Rewrite
FFFFH
FFFFH
T2 TM0 count value T1 T1
T2 T1
0H
CR00
T1
T2
TO0
CR00 rewrite
CR00 and TM0 values match, but TO0 does not change here.
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If a value smaller than that of the TM0 is set as the CR0n value, a 100% duty PWM signal will be output. CR0n rewriting should be performed by the interrupt due to a match between TM0 and the CR0n on which the rewrite is performed. Figure 9-21. Example of 100% Duty with PWM Output
FFFFH
FFFFH
FFFFH
FFFFH
n1 n1 TM0 count value n2 0H n3 n2 n2
CR00
n1
n2
TO0
When value n2 which is smaller than the TM0 value n3 is written to CR00, the duty of this period will be 100%.
Remark ALV0 = 0
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(3) Stopping PWM output If timer/event counter 0 is stopped by clearing (to 0) the CE0 bit of the timer control register 0 (TMC0) during PWM signal output, the active level is output. Figure 9-22. When Timer/Event Counter 0 is Stopped During PWM Signal Output
FFFFH FFFFH
CR00 TM0 count value
CR00
0H
TO0
Remark ALV0 = 1 Caution The output level of the TOn (n = 0, 1) pin when timer output is disabled (ENTOn = 0: n = 0, 1) is the inverse of the value set in ALVn (n = 0, 1) bit. Caution is therefore required as the active level is output when timer output is disabled when the PWM output function has been selected.
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9.7.4 PPG output (1) Basic operation of PPG output This function outputs a square-wave with the time determined by compare register CR01 value as one cycle, and the time determined by compare register CR00 value as the pulse width. The PWM cycle output by the PWM is made variable. This signal can only be output from the timer output (TO0). When this function is used, the CLR01 bit of capture/compare control register 0 (CRC0) must be set to 1. The pulse cycle and pulse width are as shown below. * PPG cycle = (CR01 + 1) x x/fXX; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 * PPG pulse width = CR00 x x/fXX where 1 CR00 CR01 * Duty = PPG pulse width PPG cycle = CR00 CR01 + 1
Figure 9-23 shows an example of PPG output using timer counter 0 (TM0), Figure 9-24 shows an example of the case where CR00 = CR01. Figure 9-23. Example of PPG Output Using TM0
CR01 TM0 count value Count start 0H INTC00 INTC01 TO0 (PPG output) TO1 (timer output) Pulse cycle Pulse width CR01 CR01
CR00
CR00
CR00
Remark
ALV0 = 0, ALV1 = 0
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Table 9-8. TO0 PPG Output (fXX = 12.58 MHz)
Count Clock fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 Minimum Pulse Width [s] 0.32 0.64 1.27 2.54 5.09 10.17 20.35 40.70 81.40 PPG Cycle 0.64 s to 20.84 ms 1.27 s to 41.68 ms 2.54 s to 83.35 ms 5.09 s to 166.71 ms 10.17 s to 333.41 ms 20.35 s to 666.82 ms 40.70 s to 1.33 s 81.40 s to 2.67 s 162.80 s to 5.33 s PPG Frequency 1572 kHz to 48.0 Hz 786 kHz to 24.0 Hz 393 kHz to 12.0 Hz 197 kHz to 6.0 Hz 98.3 kHz to 3.0 Hz 49.1 kHz to 1.5 Hz 24.6 kHz to 0.7 Hz 12.3 kHz to 0.4 Hz 6.1 kHz to 0.2 Hz
Figure 9-24. Example of PPG Output when CR00 = CR01
n n-1
n n-1
n
Count cycle T TM0 count value 1 0 INTC00 0 2 1 0 2
INTC01 TO0 Pulse width = nT Pulse cycle = (n+1) T
Remark ALV0 = 0 T = x/fXX (x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024)
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(2) Rewriting compare register (CR00) The output level of the timer output (TO0) does not change even if the CR00 value matches the timer counter 0 (TM0) value more than once during one PPG output cycle. Figure 9-25. Example of Compare Register (CR00) Rewrite
CR01
CR01
T2 TM0 count value T1 T1
T2 T1
0H
CR00
T1
T2
TO0 CR00 rewrite
CR00 and TM0 values match, but TO0 does not change here.
Remark ALV0 = 1
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If a value equal to or less than the TM0 value is written to CR00 before the compare register (CR00) and timer counter 0 (TM0) match, the duty of the PPG cycle will be 100%. CR00 rewriting should be performed by the interrupt due to a match between TM0 and CR00. Figure 9-26. Example of 100% Duty with PPG Output
CR01 CR01 CR01 CR01
n1 TM0 count value n2 0H n1 n3 n2 n2
CR00
n1
n2
TO0
When value n2 which is smaller than the TM0 value n3 is written to CR00 here, the duty of this period will be 100%.
Remark ALV0 = 0 Caution If the PPG cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of CR00 cannot be rewritten by interrupt processing that is performed on coincidence between TM0 and CR00. Use another method (for example, to poll the interrupt request flags by software with all the interrupts masked).
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(3) Rewriting compare register (CR01) If the current value of the CR01 is changed to a smaller value, and the CR01 value is made smaller than the timer counter 0 (TM0) value, the PPG cycle at that time will be extended to the time equivalent to a full-count by TM0. If CR01 is rewritten after the compare register (CR00) and TM0 match, the output level at this time will be the inactive level until TM0 overflows and becomes 0, and will then return to normal PPG output. If CR01 is rewritten before CR00 and TM0 match, the active level will be output until CR00 and TM0 match. If CR00 and TM0 match before TM0 overflows and becomes 0, the inactive level is output at that point. When TM0 overflows and becomes 0, the active level will be output, and normal PPG output will be restored. CR01 rewriting should be performed by the interrupt due to a match between TM0 and CR01, etc. Figure 9-27. Example of Extended PPG Output Cycle
Full count value
n1 n3 TM0 count value
n1 n3 n5 n2
n1
n2 n4
0H
CR00
n3
n4
CR01
n1
n2
TO0
When value n2 which is smaller than the TM0 value n5 is written to CR01 here, the PPG cycle is extended.
If CR00 and TM0 match, TO0 enters the inactive level. Otherwise, it remains at the active level.
Remark ALV0 = 1 Caution If the PPG cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of CR01 cannot be rewritten by interrupt processing that is performed on coincidence between the timer counter 0 (TM0) and compare register (CR01). Use another method (for example, to poll the interrupt request flags by software with all the interrupts masked).
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(4) Stopping PPG output If timer/event counter 0 is stopped by clearing (to 0) the CE0 bit of the timer control register 0 (TMC0) during PPG signal output, the active level is output irrespective of the output level at the time it was stopped. Figure 9-28. When Timer/Event Counter 0 is Stopped During PPG Signal Output
CR01 CR01
CR00 TM0 count value
CR00
0H
TO0
Caution The output level of the TOn (n = 0, 1) pin when timer output is disabled (ENTOn = 0: n = 0, 1) is the inverse of the value set in ALVn (n = 0, 1) bit. Caution is therefore required as the active level is output when timer output is disabled when the PPG output function has been selected.
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9.7.5 Software triggered one-shot pulse output In the software triggered one-shot pulse output mode, a one-shot pulse is output by software. When the STn (n = 0, 1) bit of the one-shot pulse output control register (OSPC) is set (1), timer output pin (TOn: n = 0, 1) is set to the active level. TOn then remains at the active level until the timer counter 0 (TM0) value and the compare register (CR0n: n = 0, 1) value match, at which point TOn changes to the inactive level. TOn then remains at the inactive level until the STn bit is set again. TOn can also be set to the inactive level by setting (to 1) the RTn bit (n = 0, 1), and in the same way, TOn remains at the inactive level until the STn bit is set again. TO0 and TO1 can be controlled independently. An example of software triggered one-shot pulse output is shown in Figure 9-29. When timer/event counter 0 is stopped by clearing (to 0) the CE0 bit of the TMC0, the level at the time was stopped is retained. Figure 9-29. Example of Software Triggered One-Shot Pulse Output
FFFFH
Software trigger Count start
0H
ST0
INTC00
ALV0 "1"
TO0
Active period
Inactive level output
Caution "1" should not be written to STn and RTn simultaneously.
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9.8 Examples of Use 9.8.1 Operation as interval timer (1) When timer counter 0 (TM0) is made free-running and a fixed value is added to the compare register (CR0n: n = 0, 1) in the interrupt service routine, TM0 operates as an interval timer with the added fixed value as the cycle (see Figure 9-30). This interval timer can count within the range shown in Table 9-1 (internal system clock fXX = 32 MHz). Since TM0 has two compare registers, two interval timers with different cycles can be constructed. The control register settings are shown in Figure 9-31, the setting procedure in Figure 9-32, and the processing in the interrupt service routine in Figure 9-33. Figure 9-30. Interval Timer Operation (1) Timing
FFFFH
FFFFH MOD (3n)
n
TM0 count value
MOD (2n)
0H Timer start Compare register (CR00) n MOD (2n) MOD (3n) MOD (4n)
INTC00 interrupt request Interval
Rewritten by interrupt program Interval
Rewritten by interrupt program Interval
Rewritten by interrupt program
Remark Interval = n x 4/fXX, 1 n FFFFH
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Figure 9-31. Control Register Settings for Interval Timer Operation (1) Capture/compare control register 0 (CRC0)
7 CRC0 0
6 0
5 0
4 1
3 0
2 0
1 0
0 0 TM0 clearing disabled TO0 & TO1 both toggle outputs
Figure 9-32. Interval Timer Operation (1) Setting Procedure
Interval timer (1)
Set count value in CR00 CR00 n
Set CRC0 CRC0 10H
Start count CE0 1
; Set 1 in bit 3 of TMC0
INTC00 interrupt
Figure 9-33. Interval Timer Operation (1) Interrupt Request Servicing
INTC00 interrupt
Calculate timer value that will generate next interrupt CR00 CR00+n
Other interrupt service program
RETI
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9.8.2 Operation as interval timer (2) TM0 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see Figure 9-34). This interval timer can count within the range shown in Table 9-1 (internal system clock fXX = 32 MHz). The control register settings are shown in Figure 9-35, and the setting procedure in Figure 9-36. Figure 9-34. Interval Timer Operation (2) Timing
n
n
TM0 count value
0H Count start Compare register (CR01) n Clear Clear
INTC01 interrupt request
Interrupt acknowledged Interval Interval
Interrupt acknowledged
Remark Interval = (n + 1) x 4/fXX, 0 n FFFFH
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Figure 9-35. Control Register Settings for Interval Timer Operation (2) Capture/compare control register 0 (CRC0)
7 CRC0 0
6 0
5 0
4 1
3 1
2 0
1 0
0 0 TM0 cleared by match of CR01 & TM0 contents TO0 & TO1 both toggle outputs
Figure 9-36. Interval Timer Operation (2) Setting Procedure
Interval timer (2)
Set count value in CR01 CR01 n
Set CRC0 CRC0 18H
Start count CE0 1
; Set 1 in bit 3 of TMC0
INTC01 interrupt
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9.8.3 Pulse width measurement operation In pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input pin (INTP3) is measured. Both the high-level and low-level widths of pulses input to the INTP3 pin must be at least 3 system clocks (0.24 s: fCLK = 12.58 MHz); if shorter than this, the valid edge will not be detected and a capture operation will not be performed. This pulse width measurement can be performed within the range shown in Table 9-3 (fCLK = 12.58 MHz). As shown in Figure 9-37, the timer counter 0 (TM0) value being counted is fetched into the capture register (CR02) in synchronization with a valid edge (specified as both rising and falling edges) in the INTP3 pin input, and held there. The pulse width is obtained from the product of the difference between the TM0 count value (Dn) fetched into and held in the CR02 on detection of the nth valid edge and the count value (Dn-1) fetched and held on detection of valid edge n-1, and the number of count clocks (x/fXX; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024). The control register settings are shown in Figure 9-38, and the setting procedure in Figure 9-39. Figure 9-37. Pulse Width Measurement Timing
FFFFH
FFFFH
TM0 count value
D1
D3
D0 0H Count start INTP3 external input signal (D1-D0) x 8/fXX INTP3 interrupt request (10000H-D1+ D2) x 8/fXX Capture Capture
D2 Capture Capture
(D3-D2) x 8/fXX
Capture register (CR02)
D0
D1
D2
D3
OVF0 Cleared by software
Remark Dn: TM0 count value (n = 0, 1, 2, ...) x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024
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Figure 9-38. Control Register Settings for Pulse Width Measurement (a) Capture/compare control register 0 (CRC0)
7 CRC0 0
6 0
5 0
4 1
3 0
2 0
1 0
0 0 TM0 clearing disabled TO0 & TO1 both toggle outputs
(b) External interrupt mode register 1 (INTM1)
7 INTM1 0 6 0 5 x 4 x 3 x 2 x 1 1 0 1
Both rising & falling edges specified as INTP3 input valid edges x: don't care
Figure 9-39. Pulse Width Measurement Setting Procedure
Pulse width measurement
Set CRC0 CRC0 10H
Set INTM1, Set MK0L
; Specify both edges as INTP3 input valid edges, release interrupt masking
Initialize capture value buffer memory X0 0
Start count CE0 1
; Set 1 in bit 3 of TMC0
Enable interrupt
INTP3 interrupt
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Figure 9-40. Interrupt Request Servicing that Calculates Pulse Width
INTP3 interrupt
Calculate pulse width Yn = CR02 - Xn
Store capture value in memory Xn+1 CR02
RETI
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9.8.4 Operation as PWM output In PWM output, pulses with the duty ratio determined by the value set in the compare register (CR0n: n = 0, 1) are output (see Figure 9-41). This PWM output duty ratio can be varied in the range 1/65,536 to 65,535/65,536 in 1/65,536 units. Since timer counter 0 (TM0) has two compare registers, two different PWM signals can be output. The control register settings are shown in Figure 9-42, the setting procedure in Figure 9-43, and the procedure for varying the duty in Figure 9-44. Figure 9-41. Example of Timer/Event Counter 0 PWM Signal Output
FFFFH
FFFFH
FFFFH
TM0 count value 0H
CR00
CR00
CR00
Timer start TO0 (When active-low)
Figure 9-42. Control Register Settings for PWM Output Operation (a) Capture/compare control register 0 (CRC0)
7 CRC0 1
6 0
5 0
4 1
3 0
2 0
1 0
0 0 TM0 clearing disabled TO0 & TO1 both PWM outputs
(b) Timer output control register (TOC)
7 TOC x
6 x
5 x
4 x
3 x
2 x
1 1
0 1 TO0 = active-low PWM signal output TO0 PWM output enabled
(c) Port 3 mode control register (PMC3)
7 PMC3 x
6 x
5 x
4 1
3 x
2 x
1 x
0 x P34 pin set as TO0 output
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Figure 9-43. PWM Output Setting Procedure
PWM output
Set CRC0 CRC0 90H
Set TOC
Set P34 pin to control mode PMC3.4 1
Set initial value in CR00, CR01
Start count CE0 1
; Set bit 3 of TMC0
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Figure 9-44. Changing PWM Output Duty
Duty change preprocessing
Clear INTC00 interrupt request flag CIF00 0
; Clear bit 4 of IF0L
Enable INTC00 interrupts CMK00 0
; Clear bit 4 of MK0L
INTC00 interrupt
Duty change processing
Set duty value in CR00
Disable INTC00 interrupts CMK00 1
; Set bit 4 of MK0L
RETI
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9.8.5 Operation as PPG output In PPG output, pulses with the cycle and duty ratio determined by the values set in the compare registers (CR0n: n = 0, 1) are output (see Figure 9-45). The control register settings are shown in Figure 9-46, the setting procedure in Figure 9-47, and the procedure for varying the duty in Figure 9-48. Figure 9-45. Example of Timer/Event Counter 0 PPG Signal Output
CR01
CR01
CR01
TM0 count value 0H
CR00
CR00
CR00
Timer start TO0 (when active-low)
Figure 9-46. Control Register Settings for PPG Output Operation (a) Capture/compare control register 0 (CRC0)
7 CRC0 1
6 1
5 0
4 1
3 1
2 0
1 0
0 0 TM0 cleared by match of TM0 & CR01 TO0 = PPG output
(b) Timer output control register (TOC)
7 TOC x
6 x
5 x
4 x
3 x
2 x
1 1
0 1 TO0 = active-low PPG signal output TO0 PPG output enabled
(c) Port 3 mode control register (PMC3)
7 PMC3 x
6 x
5 x
4 1
3 x
2 x
1 x
0 x P34 pin set as TO0 output
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Figure 9-47. PPG Output Setting Procedure
PPG output
Set CRC0 CRC0 D8H
Set TOC
Set P34 pin to control mode PMC3.4 1
Set cycle in CR01
Set duty in CR00
Start count CE0 1
; Set bit 3 of TMC0
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Figure 9-48. Changing PPG Output Duty
Duty change preprocessing
Clear INTC00 interrupt request flag CIF00 0
; Clear bit 4 of IF0L
Enable INTC00 interrupts CMK00 0
; Clear bit 4 of MK0L
INTC00 interrupt
Duty change processing
Set duty value in CR00
Disable INTC00 interrupts CMK00 1
; Set bit 4 of MK0L
RETI
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9.8.6 Example of software triggered one-shot pulse output In the software triggered one-shot pulse output mode, a one-shot pulse is output in response to a trigger activated by software (see Figure 9-49). The control register settings are shown in Figure 9-50, and the setting procedure in Figure 9-51. Figure 9-49. Example of Timer/Event Counter 0 One-Shot Pulse Output
FFFFH
FFFFH
TM0 count value CR00
0H Count start
TO0
Set trigger
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Figure 9-50. Control Register Settings for One-Shot Pulse Output (a) One-shot pulse output control register (OSPC)
7 OSPC 0
6 0
5 0
4 x
3 0
2 0
1 0
0 1 TO0 = one-shot pulse output
(b) Capture/compare control register 0 (CRC0)
7 CRC0 0
6 0
5 0
4 1
3 0
2 0
1 0
0 0 TM0 clearing disabled TO0 & TO1 both toggle outputs
(c) Timer output control register (TOC)
7 TOC x
6 x
5 x
4 x
3 x
2 x
1 1
0 1 TO0 = active-high one-shot pulse signal output TO0 one-shot pulse output enabled
(d) Port 3 mode control register (PMC3)
7 PMC3 x
6 x
5 x
4 1
3 x
2 x
1 x
0 x P34 pin set as TO0 output
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Figure 9-51. One-Shot Pulse Output Setting Procedure
One-shot pulse output
Set OSPC OS0 1
; Set to one-shot pulse output mode
Set CRC0 CRC0 10H
Set P34 pin to control mode PMC 3.4 1
Set pulse width in CR00
Start count CE0 1
; Set bit 3 of TMC0
One-shot pulse output ST0 1
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9.9 Cautions (1) While timer/event counter 0 is operating (while the CE0 bit of the timer control register 0 (TMC0) is set), malfunctioning may occur if the contents of the following registers are rewritten. This is because it is undefined which takes precedence in a contention the change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting. Therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following registers. * Prescaler mode register 0 (PRM0) * Capture/compare control register 0 (CRC0) * Timer output control register (TOC) (2) If the contents of the compare register (CR0n: n = 0, 1) coincide with those of TM0 operation when an instruction that stops timer counter 0 (TM0) operation is executed, the counting operation of TM0 stops, but an interrupt request is generated. In order not to generate the interrupt when stopping the operation of TM0, mask the interrupt in advance by using the interrupt mask register before stopping TM0. Example Program that may generate interrupt request *** Program that does not generate interrupt request *** Interrupt request from timer/event counter 0 occurs between these instructions OR CLR1 CLR1 CLR1 MK0L, #30H CE0 CIF00 CIF01 *** Disables interrupt from timer/event counter 0 Clears interrupt request flag for timer/event counter 0 Figure 9-52. Operation when Counting is Started
Count clock TM0 0 0 1
CLR1 OR
CE0 MK0L, #30H ***
(3) Up to 1 count clock is required after an operation to start timer/event counter 0 (CE0 1) has been performed before timer/ event counter 0 actually starts (refer to Figure 9-52). For example, when using timer/event counter 0 as an interval timer, the first interval time is delayed by up to 1 clock. The second and those that follow are at the specified interval.
2
3
CE0
Timing to start actual counting
Count start command (CE0 1) by software
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(4) While an instruction that writes data to the compare register (CR0n: n = 0, 1) is executed, coincidence between CR0n, to which the data is to be written, and timer counter 0 (TM0) is not detected. For example, if the contents of CR0n do not change before and after the writing, the interrupt request is not generated even if the value of TM0 coincides with the value of CR0n, nor does the timer output (TOn: n = 0, 1) change. Write data to CR0n when timer/event counter 0 is executing counting operation, in the timing that the contents of TM0 do not coincide with the value of CR0n before and after writing (e.g., immediately after an interrupt request has been generated because TM0 and CR0n have coincided). (5) Coincidence between TM0 and compare register (CR0n: n = 0, 1) is detected only when TM0 is incremented. Therefore, the interrupt request is not generated even if the same value as TM0 is written to CR0n, and the timer output (TOn: n = 0, 1) does not change. (6) If the PPG cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of the CR0n cannot be rewritten by interrupt processing that is performed on coincidence between TM0 and the compare register (CR0n: n = 0, 1). Use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). (7) The output level of the TOn (n = 0, 1) when the timer output is disabled (ENTOn = 0: n = 0, 1) is the reverse value of the value set to the ALVn (n = 0, 1) bit. Note, therefore, that an active level is output when the timer output is disabled with the PWM output function or PPG output function selected. (8) When timer/event counter 0 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input, using the timer counter 0 (TM0) alone (refer to Figure 9-53), since the contents of TM0 are 0 in both cases. If it is necessary to make this distinction, the INTP3 interrupt request flag should be used. To make a distinction, use the interrupt request flag of INTP3, as shown in Figure 9-54. Figure 9-53. Example of the Case where the External Event Counter does Not Distinguish between One Valid Edge Input and No Valid Edge Input
INTP3
TM0
0
0
1
2
Cannot be distinguished Count start
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Figure 9-54. To Distinguish whether One or No Valid Edge has been Input with External Event Counter (a) Processing on starting counting
Start count
Clear INTP3 interrupt request flag PIF3 0
; Clear PIF3 to 0
Start count CE3 1
; Set CE3 to 1
End
(b) Processing on reading count value
Count value read
Read TM0 contents AX TM0
AX = 0? NO AX AX+1
YES YES
; Check TM0 value. If 0, check interrupt request flag. PIF3 = 1? NO ; Check PIF3 contents. If 1, valid edge is input.
End
Number of input valid edges is set to AX register
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10.1 Functions Timer/event counter 1 is 16-bit or 8-bit timer/event counter. In addition to its basic functions of interval timer, pulse width measurement, and event counter, timer/event counter 1 can be used as a real-time output port output trigger generation timer. (1) Interval timer Generates internal interrupts at preset intervals. Table 10-1. Timer/Event Counter 1 Intervals
Minimum Interval 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s) Maximum Interval 216 x 4/fXX (20.8 ms) 216 x 8/fXX (41.7 ms) 216 x 16/fXX (83.4 ms) 216 x 32/fXX (167 ms) 216 x 64/fXX (333 ms) 216 x 128/fXX (667 ms) 216 x 256/fXX (1.33 s) 216 x 512/fXX (2.67 s) 216 x 1,024/fXX (5.33 s) Resolution 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s)
( ): When fXX = 12.58 MHz
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(2) Pulse width measurement Detects the pulse width of the signal input to the external interrupt request input pin INTP0. Table 10-2. Timer/Event Counter 1 Pulse Width Measurement Range
Measurable Pulse WidthNote 4/fXX to (0.32 s) 8/fXX to (0.64 s) 16/fXX to (1.27 s) 32/fXX to (2.54 s) 64/fXX to (5.09 s) 2 x 4/fXX (20.8 ms)
16
Resolution 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s)
216 x 8/fXX (41.7 ms) 216 x 16/fXX (83.4 ms) 216 x 32/fXX (167 ms) 216 x 64/fXX (333 ms)
128/fXX to 216 x 128/fXX (10.17 s) (667 ms) 256/fXX to 216 x 256/fXX (20.35 s) (1.33 s) 512/fXX to 216 x 512/fXX (40.70 s) (2.67 s) 1,024/fXX to 216 x 1,024/fXX (81.40 s) (5.33 s)
( ): When fXX = 12.58 MHz Note The minimum pulse width that can be measured changes depending on the sampling clock selected by the sampling clock select register (SCS0). The minimum pulse width that can be measured is the value in the table below or above, whichever is greater. at fXX = 12.58 MHz operation
Sampling Clock fCLK fCLK = fXX fCLK = fXX/2 fCLK = fXX/4 fCLK = fXX/8 fXX/32 fXX/64 fXX/128 Minimum Pulse Width 3/fCLK = 3/fXX (0.24 s) 3/fCLK = 6/fXX (0.48 s) 3/fCLK = 12/fXX (0.95 s) 3/fCLK = 24/fXX (1.19 s) 96/fXX (7.63 s) 192/fXX (15.26 s) 384/fXX (30.52 s)
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(3) External event counter Counts the clock pulses input from the external interrupt request input pin (INTP0). The clocks that can be input to timer/event counter 1 are shown in Table 10-3. Table 10-3. Timer/Event Counter 1 Pulse Width Measurement Time
( ): When fCLK = 12.58 MHz and fXX = 12.58 MHz Sampling ClockNote fCLK Maximum frequency Minimum pulse width (High and low levels) fXX/32 Maximum frequency Minimum pulse width (High and low levels) fXX/64 Maximum frequency Minimum pulse width (High and low levels) fXX/128 Maximum frequency Minimum pulse width (High and low levels) When Counting One Edge fCLK/6 (2.10 MHz) 3/fCLK (0.24 s) When Counting Both Edges fCLK/6 (2.10 MHz) 3/fCLK (0.24 s)
fXX/192 (65.52 kHz) 96/fXX (7.63 s)
fXX/192 (65.52 kHz) 96/fXX (7.63 s)
fXX/384 (32.76 kHz) 192/fXX (15.26 s)
fXX/384 (32.76 kHz) 192/fXX (15.26 s)
fXX/768 (16.38 kHz) 384/fXX (30.52 s)
fXX/768 (16.38 kHz) 384/fXX (30.52 s)
Note Selected by means of the sampling clock selection register (SCS0) 10.2 Configuration Timer/event counter 1 consists of the following registers: * Timer counter (TM1/TM1W) x 1 * Compare register (CR10/CR10W) x 1 * Capture/Compare register (CR11/CR11W) x 1 * Capture register (CR12/CR12W) x 1 The block diagram of timer/event counter 1 is shown in Figure 10-1.
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1/8 External interrupt mode register 0 (INTM0) P21/INTP0 ES31 ES30 8 Edge detection circuit 8 INTP0 16 Match 16
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Figure 10-1. Timer/Event Counter 1 Block Diagram
Internal bus
8/16 Compare register (CR10/CR10W) 8/16 Match Selector CLR11
8 Capture/compare CM CLR10 control register 1 (CRC1)
INTC10
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Capture/compare register (CR11/CR11W) 8 fXX/1,024 fXX/512 fXX/256 fXX/128 fXX/64 fXX/32 fXX/16 fXX/8 fXX/4 16 Prescaler mode register 1 PRS23 PRS22 PRS21 PRS20 (PRM1) 8 Capture register (CR12/CR12W) 8/16 8/16 Capture trigger Selector 8 Match 16 Match 16 16
Clear RESET
Real-time output port
Selector
INTC11
fXX
Prescaler
CM Timer counter 1 (TM1/TM1W) Capture trigger Timer control register 1 (TMC1) Overflow
CE1 OVF1 BW1
1/8 Internal bus
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(1) Timer counter 1 (TM1/TM1W) TM1/TM1W is a timer counter that counts up using the count clock specified by the low-order 4 bits of prescaler mode register 1 (PRM1). The count operation can be specified to stop or enable, and an 8-bit operation mode (TM1)/16-bit operation mode (TM1W) can be selected, by means of timer control register 1 (TMC1). TM1/TM1W can be read only with an 8/16-bit manipulation instruction. When RESET is input, TM1/TM1W is cleared to 00H and the count is stopped. (2) Compare register (CR10/CR10W) CR10/CR10W is an 8/16-bit register that holds the value that determines the interval timer operation cycle. If the contents of the CR10/CR10W match the values of TM1/TM1W, an interrupt request (INTC10) is generated. This match signal is also a real-time output port trigger signal. Also, the count value can be cleared by a match. This compare register operates as CR10 in the 8-bit operation mode, and CR10W in the 16-bit operation mode. CR10/CR10W can be read or written to with an 8/16-bit manipulation instruction. The contents of this register are undefined after RESET input. (3) Capture/compare register (CR11/CR11W) CR11/CR11W is an 8/16-bit register that can be specified as a compare register for detecting a match with the TM1/TM1W count value or a capture register for capturing the TM1/TM1W count value according to the setting of capture/compare control register 1 (CRC1). This capture/compare register operates as CR11 in the 8-bit operation mode, and CR11W in the 16-bit operation mode. CR11/CR11W can be read or written to with an 8/16-bit manipulation instruction. The contents of this register are undefined after RESET input. (a) When specified as compare register CR11/CR11W functions as an 8/16-bit register that holds the value that determines the interval timer operation cycle. An interrupt request (INTC11) is generated by a match between the contents of CR11/CR11W and the contents of TM1/TM1W. Also, the count value can be cleared by a match. This match signal is also a real-time output port trigger signal. (b) When specified as capture register CR11/CR11W functions as an 8/16-bit register that captures the contents of TM1/TM1W in synchronization with the input of a valid edge (capture trigger) on the external interrupt request input pin (INTP0). The contents of the CR11/CR11W are retained until the next capture trigger is generated. TM1/TM1W can be cleared after a capture operation. (4) Capture register (CR12/CR12W) CR12/CR12W is an 8/16-bit register that captures the contents of TM1/TM1W. The capture operation is synchronized with the input of a valid edge (capture trigger) on the external interrupt request input pin (INTP0). The contents of the CR12/CR12W are retained until the next capture trigger is generated. This capture/compare register operates as CR12 in the 8-bit operation mode, and CR12W in the 16-bit operation mode. CR12/CR12W can be read only with an 8/16-bit manipulation instruction. The contents of this register are undefined after RESET input.
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(5) Edge detection circuit The edge detection circuit detects an external input valid edge. When the valid edge set by external interrupt mode register 0 (INTM0) is detected in the INTP0 pin input, the external interrupt request (INTP0), a capture trigger and a count clock of the external event are generated (see Figure 22-1 for details of the INTM0). (6) Prescaler The prescaler generates the count clock from the internal system clock. The clock generated by this prescaler is selected by the selector, and is used as the count clock by the timer counter 1 (TM1/TM1W) to perform count operations. (7) Selector The selector selects a signal resulting from dividing the internal clock or the edge detected by the edge detection circuit as the count clock of timer counter 1 (TM1/TM1W).
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10.3 Timer/Event Counter 1 Control Registers (1) Timer control register 1 (TMC1) TMC1 controls the timer/event counter 1, TM1/TM1W, count operation by the low-order 4 bits (the high-order 4 bits control the count operation of timer/event counter 2 TM2/TM2W). TMC1 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The format of TMC1 is shown in Figure 10-2. RESET input clears TMC1 to 00H. Figure 10-2. Timer Control Register 1 (TMC1) Format
7 TMC1 CE2
6
5
4 BW2
3 CE1
2 OVF1
1 0
0 BW1
Address 0FF5FH
After reset 00H
R/W R/W
OVF2 CMD2
BW1 0 1
Timer/Event Counter 1 Bit Length Specification 8-bit operating mode 16-bit operating mode
OVF1 0 1
TM1/TM1W Overflow Flag No overflow OverflowNote
Note In 8-bit operating mode: count up from FFH to 00H In 16-bit operating mode: count up from FFFFH to 0000H
CE1 0 1
TM1/TM1W Count Operation Control Count operation stopped with count cleared Count operation enabled
Countrols count operation of timer/event counter 2 (TM2/TM2W) (see Figure 11-2).
Remark The OVF1 bit is reset by software only.
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(2) Prescaler mode register 1 (PRM1) In PRM1, the count clock to timer/event counter 1 TM1/TM1W is specified by the low-order 4 bits (the high-order 4 bits specify the count clock to timer/event counter 2 TM2/TM2W). PRM1 can be read or written to with an 8-bit manipulation instruction. The format of PRM1 is shown in Figure 10-3. RESET input sets PRM1 to 11H. Figure 10-3. Prescaler Mode Register 1 (PRM1) Format
7 6 5 4 3 2 1 0 Address 0FF5EH After reset 11H R/W R/W
PRM1 PRS23 PRS22 PRS21 PRS20 PRS13 PRS12 PRS11 PRS10
(fXX = 12.58 MHz) PRS13 PRS12 PRS11 PRS10 Timer/Event Counter 1 (TM1/ TM1W) Count Clock Specification Count Clock [Hz] Specification 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 Setting prohibited fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 External clock (INTP0) Setting prohibited Resolution [ s] - 0.64 1.27 2.54 5.09 10.17 20.35 40.70 81.40 162.80 -
Other than the above
Specifies count clock to TM2/TM2W of timer/event counter 2 (see Figure 11-3).
Remark fXX: X1 input frequency or oscillation frequency
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(3) Capture/compare control register 1 (CRC1) CRC1 specifies the operation of the capture/compare register (CR11/CR11W) and the enabling condition for a timer counter 1 (TM1/TM1W) clear operation. CRC1 can be read or written to with an 8-bit manipulation instruction. The format of CRC1 is shown in Figure 10-4. RESET input clears CRC1 to 00H. Figure 10-4. Capture/Compare Control Register 1 (CRC1) Format
7 CRC1 0
6 0
5 0
4 0
3 CLR11
2 CM
1 CLR10
0 0
Address 0FF32H
After reset 00H
R/W R/W
CLR10 TM1 Clear Operation when TM1 = CR10 TM1W Clear Operation when TM1W = CR10W 0 1 Disabled Enabled CR11/CR11W Operation Specificaton Compare operation TM1/TM1W Clearance Operation Disabled Enabled (when TM1 & CR11 or TM1W & CR11W contents match) Disabled Enabled (when TM1 contents are captured in CR11 or when TM1W contents are captured in CR11W)
CLR11 CM
0 1
0 0
0 1
1 1
Capture operation
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10.4 Timer Counter 1 (TM1) Operation 10.4.1 Basic operation 8-bit operation mode/16-bit operation mode control can be performed for timer/event counter 1 by means of bit 0 (BW1) of timer control register 1 (TMC1)Note. In the timer/event counter 1 count operation, the count-up is performed using the count clock specified by the low-order 4 bits of prescaler mode register 1 (PRM1). Count operation enabling/disabling is controlled by bit 3 (CE1) of TMC1 (timer/event counter 1 operation control is performed by the low-order 4 bits of the TMC1). When the CE1 bit is set (to 1) by software, the contents of TM1 are cleared to 0H on the first count clock, and then the count-up operation is performed. When the CE1 bit is cleared (to 0), TM1 becomes 0H immediately, and capture operations and match signal generation are stopped. If the CE1 bit is set (to 1) again when it is already set (to 1), TM1 continues the count operation without being cleared. If the count clock is input when TM1 is FFH in 8-bit operation mode and when TM1W is FFFFH in 16-bit operation mode, TM1/ TM1W becomes 0H. In this case, OVF1 bit is set. OVF1 bit is cleared by software only. The count operation is continued. When RESET is input, TM1 is cleared to 0H, and the count operation is stopped. Note Unless otherwise specified, the functions of timer counter 1 in the 8-bit operation mode are described hereafter. In the 16-bit operation mode, TM1, CR10, and CR11 operate as TM1W, CR10W, and CR11W respectively.
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Figure 10-5. Basic Operation in 8-Bit Operation Mode (BW1 = 0) (a) Count started count disabled count started
Count clock
TM1
0H
0H
1H
2H
0FH
10H 11H
0H
0H
1H
CE1
Count started CE1 1
Count stopped CE1 0
Count started CE1 1
(b) When "1" is written to the CE1 bit again after the count starts
Count clock
TM1
0H
0H
1H
2H
3H
4H
5H
6H
CE1
Count started CE1 1
Rewrite CE1 1
(c) Operation when TM1 = FFH
Count clock
TM1
FEH
FFH
0H
1H
OVF1
Cleared by software OVF1 0
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Figure 10-6. Basic Operation in 16-Bit Operation Mode (BW1 = 1) (a) Count started count disabled count started
Count clock
TM1W
0H
0H
1H
2H
FFH 100H 101H
0H
0H
1H
CE1
Count started CE1 1
Count stopped CE1 0
Count started CE1 1
(b) When "1" is written to the CE1 bit again after the count starts
Count clock
TM1W
0H
0H
1H
2H
3H
4H
5H
6H
CE1
Count started CE1 1
Rewrite CE1 1
(c) Operation when TM1W = FFFFH
Count clock
TM1W
FFFEH FFFFH
0H
1H
OVF1
Cleared by software OVF1 0
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10.4.2 Clear operation (1) Clear operation after match with compare register and after capture operation Timer counter 1 (TM1) can be cleared automatically after a match with the compare register (CR1n: n = 0, 1) and a capture operation. When a clearance source arises, TM1 is cleared to 0H on the next count clock. Therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. Figure 10-7. TM1 Clearance by Match with Compare Register (CR10, CR11)
Count clock
TM1
n-1
n
0
1
Compare register (CR1n)
n
TM1 and CR1n match
Cleared here
Figure 10-8. TM1 Clearance after Capture Operation
Count clock
TM1
n-1
n
0
1
2
INTP0
TM1 is captured in CR11 here Cleared here
(2) Clear operation by CE1 bit of timer control register 1 (TMC1) Timer counter 1 (TM1) is also cleared when the CE1 bit of TMC1 is cleared (to 0) by software. The clear operation is performed immediately after the clearance (to 0) of the CE1 bit.
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Figure 10-9. Clear Operation when CE1 Bit is Cleared (to 0) (a) Basic operation
Count clock
TM1
n-1
n
0
CE1
(b) Restart before count clock is input after clearance
Count clock
TM1
n-1
n
0
0
1
2
CE1
If the CE1 bit is set (to 1) before this count clock, this count clock starts counting from 0.
(c) Restart after count clock is input after clearance
Count clock
TM1
n-1
n
0
0
0
1
CE1
If the CE1 bit is set (to 1) from this count clock onward, the count clock starts counting from 0 after the CE1 bit is set (to 1).
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10.5 External Event Counter Function Timer/event counter 1 can count clock pulses input from the external interrupt request input pin (INTP0) pin. No special selection method is needed for the external event counter operation mode. When the timer counter 1 (TM1) count clock is specified as external clock input by the setting of the low-order 4 bits of prescaler mode register 1 (PRM1), TM1 operates as an external event counter. The maximum frequency of the external clock pulse that can be counted by the external event counter is determined by the sampling clock select register (SCS0) as shown in Table 10-4. The maximum frequency is the same when both the edges of the INTP0 input are counted and when only one edge is counted. The pulse width of the INTP0 input must be three or more sampling clocks selected by SCS0, regardless of whether the level is high or low. If the width is shorter than this, the pulse may not be counted. Figure 10-10 shows the timing of the external event count by timer/event counter 1. Table 10-4. Maximum Input Frequency and Minimum Input Pulse Width that can be Counted as Events
( ): fXX = 12.58 MHz, fCLK = 12.58 MHz Sampling Clock Selected by SCS0 fCLK fXX/32 fXX/64 fXX/128 Maximum Input Frequency fCLK/6 (2.10 MHz) fXX/192 (65.52 kHz) fXX/384 (32.76 kHz) fXX/768 (16.38 kHz) Minimum Pulse Width 3/fCLK (0.24 s) 96/fXX (7.63 s) 192/fXX (15.26 s) 384/fXX (30.52 s)
Figure 10-10. Timer/Event Counter 1 External Event Count Timing (1/2) (1) Counting one edge (maximum frequency = fCLK/6)
3/fSMP (MIN.) 3/fSMP (MIN.)
6/fSMP (MIN.)
INTP0 2-3/fSMP ICI
TM1
Dn
Dn+1
Dn+2
Dn+3
Remarks 1. ICI: INTP0 input signal after passing through edge detection circuit 2. fSMP is selected by the sampling clock selection register (SCS0).
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Figure 10-10. Timer/Event Counter 1 External Event Count Timing (2/2) (2) Counting both edges (maximum frequency = fCLK/6)
3/fSMP (MIN.) INTP0
3/fSMP (MIN.)
6/fSMP (MIN.)
2-3/fSMP
ICI
TM1
Dn
Dn+1
Dn+2
Dn+3
Dn+4
Dn+5
Remarks 1. ICI: INTP0 input signal after passing through edge detection circuit 2. fSMP is selected by the sampling clock selection register (SCS0). The TM1 count operation is controlled by the CE1 bit of the timer control register 1 (TMC1) in the same way as with the basic operation. When the CE1 bit is set (to 1) by software, the contents of TM1 are set to 0H and the count-up operation is started on the initial count clock. When the CE1 bit is cleared (to 0) by software during a TM1 count operation, the contents of TM1 are set to 0H immediately and the stopped state is entered. The TM1 count operation is not affected if the CE1 bit is set (to 1) by software again when it is already set (to 1). Caution When timer/event counter 1 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input using the timer counter 1 (TM1) alone (see Figure 10-11), since the contents of TM1 are 0 in both cases. If it is necessary to make this distinction, the INTP0 interrupt request flag should be used. An example is shown in Figure 10-12. Figure 10-11. Example of the Case where the External Event Counter does Not Distinguish between One Valid Edge Input and No Valid Edge Input
INTP0
TM1
0
0
1
2
No distinction made
Count start
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Figure 10-12. To distinguish whether One or No Valid Edge has been Input with External Event Counter (a) Processing when count is started
Start count
Clear INTP0 interrupt request flag PIF0 0
; Clear PIF0 to 0
Start count CE1 1
; Set CE1 to 1
End
(b) Processing when count value is read
Count value read
Read TM1 contents A TM1
A = 0?
YES ; Check TM1 value If 0, check interrupt request flag YES PIF0 = 1? NO ; Check PIF0 contents If 1, there is a valid edge
NO
A A+1
End
; Number of input valid edges is set in A register
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10.6 Compare Register and Capture/Compare Register Operation 10.6.1 Compare operations Timer/event counter 1 performs compare operations in which the value set in a compare register (CR10), capture/compare register (CR11), specified for compare operation is compared with the timer counter 1 (TM1) count value. If the count value of TM1 matches the preset value of the CR10, or the CR11 as the result of the count operation, an interrupt request signal (INTC10 or INTC11) is generated. After a match with the CR10 or CR11 value, the TM1 contents can be cleared, and the timer functions as an interval timer that repeatedly counts up to the value set in the CR10 or CR11. Figure 10-13. Compare Operation in 8-Bit Operation Mode
FFH
TM1 count value CR11 value 0H Count start CE1 1 Match
CR10 value
Match
INTC10 interrupt request INTC11 interrupt request
OVF1
Remark CLR10 = 0, CLR11 = 0, CM = 0, BW1 = 0
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Figure 10-14. Compare Operation in 16-Bit Operation Mode
FFFFH
FFFFH
TM1W count value CR11W value CR11W value
CR10W value 0H Count start CE1 1 INTC10 interrupt request Match Match
CR10W value Match Match
INTC11 interrupt request
OVF1
Cleared by software
Remark CLR10 = 0, CLR11 = 0, BW1 = 1 Figure 10-15. TM1 Clearance after Match Detection
CR11
CR10 TM1 count value
CR10
CR10
0H Count start CE 1 CLR10 0 CLR11 1 INTC10 interrupt request Clear Count start CE1 0 Count disabled CLR10 1 CE1 0 CLR11 0 Clear Clear
INTC11 interrupt request
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10.6.2 Capture operations Timer/event counter 1 performs capture operations in which the timer counter 1 (TM1) count value is fetched into the capture register in synchronization with an external trigger, and retained there. A valid edge detected from the input of the external interrupt request input pin (INTP0) is used as the external trigger (capture trigger). The count value of TM1 in the process of being counted is fetched into the capture register (CR12), or the capture/ compare register (CR11) when a capture operation is specified, in synchronization with the capture trigger, and is retained there. The contents of the CR11 and CR12 are retained until the next capture trigger is generated. The capture trigger valid edge is set by means of external interrupt mode register 0 (INTM0). If both rising and falling edges are set as capture triggers, the width of pulses input from off-chip can be measured, and if a capture trigger is generated by a single edge, the input pulse cycle can be measured. See Figure 22-1 for details of the INTM0 format. When CR11 is used as a capture register, TM1 can be cleared as soon as the contents of TM1 have been captured to CR11 by capture trigger. Figure 10-16. Capture Operation in 8-Bit Operation Mode
FFH
TM1 count value D1
D0 0H Count start INTP0 pin input
D2
INTP0 interrupt request
Capture/compare register (CR11)
D0
D1
D2
OVF1
Remark Dn: TM1 count value (n = 0, 1, 2, ...) CLR10 = 0, CLR11 = 0, CM = 1, BW1 = 0
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Figure 10-17. Capture Operation in 16-Bit Operation Mode
FFFFH
TM1W count value D1
D0 0H Count start CE1 1
D2
INTP0 pin input
INTP0 interrupt request
Capture register (CR12W)
D0
D1
D2
OVF1
Remark Dn: TM1W count value (n = 0, 1, 2, ...) CLR10 = 0, CLR11 = 0, CM = 1, BW1 = 1
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Figure 10-18. TM1 Clearance after Capture Operation
N1
N4
TM1 count value
N2
N3
N5
0H Capture Capture Capture Capture Capture
INTP0 pin input
INTP0 interrupt request
Capture/compare register (CR11)
N1
N2
N3
N4
Remark NI: TM1 count value (n = 0, 1, 2, ...) CLR10 = 0, CLR11 = 1, CM = 1
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10.7 Examples of Use 10.7.1 Operation as interval timer (1) When timer counter 1 (TM1) is made free-running and a fixed value is added to the compare register (CR1n: n = 0, 1) in the interrupt service routine, TM1 operates as an interval timer with the added fixed value as the cycle (see Figure 10-19). Since TM1 has two compare registers, two interval timers with different intervals can be constructed. The control register settings are shown in Figure 10-20, the setting procedure in Figure 10-21, and the processing in the interrupt service routine in Figure 10-22. Figure 10-19. Interval Timer Operation (1) Timing
FFH MOD (3n)
FFH
n TM1 count value MOD (2n)
0H Timer start Compare register (CR10) n MOD (2n) MOD (3n) MOD (4n)
INTC10 interrupt request Interval
Rewritten by interrupt program Interval
Rewritten by interrupt program Interval
Rewritten by interrupt program
Remark Interval = n x x/fXX, 1 n FFH x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024
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Figure 10-20. Control Register Settings for Interval Timer Operation (1) (a) Prescaler mode register 1 (PRM1)
7 PRM1 x
6 x
5 x
4 x
3
2
1
0
PRS13 PRS12 PRS11 PRS10
Count clock specification (x/fXX ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024)
(b) Capture/compare control register 1 (CRC1)
7 CRC1 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0 TM1 clearing by match of CR10 & TM1 contents disabled CR11 specified as compare register
TM1 clearing by match of CR11 & TM1 contents disabled
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Figure 10-21. Interval Timer Operation (1) Setting Procedure
Interval timer (1)
Set PRM1
Set count value in CR10 CR10 n
Set CRC1 CRC1 00H
Start count CE1 1
; Set 1 in bit 3 of TMC1
INTC10 interrupt
Figure 10-22. Interval Timer Operation (1) Interrupt Request Servicing
INTC10 interrupt
Calculate timer value that will generate next interrupt CR10 CR10+n Other interrupt service program
RETI
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10.7.2 Operation as interval timer (2) TM1 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see Figure 10-23). The control register settings are shown in Figure 10-24, and the setting procedure in Figure 10-25. Figure 10-23. Interval Timer Operation (2) Timing (when CR11 is used as Compare Register)
n
n
TM1 count value
0H Count start Compare register (CR11) Match INTC11 interrupt request Clear n Match Clear
Interrupt acknowledge Interval Interval
Interrupt acknowledge
Remark Interval = (n+1) x x/fXX 0 n FFH x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024
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Figure 10-24. Control Register Settings for Interval Timer Operation (2) (a) Prescaler mode register 1 (PRM1)
7 PRM1 x
6 x
5 x
4 x
3
2
1
0
PRS13 PRS12 PRS11 PRS10
Count clock specification (x/fXX ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024)
(b) Capture/compare control register 1 (CRC1)
7 CRC1 0
6 0
5 0
4 0
3 1
2 0
1 0
0 0 TM1 clearing by match of CR10 & TM1 contents disabled CR11 specified as compare operation
TM1 clearing by match of CR11 & TM1 contents enabled
Figure 10-25. Interval Timer Operation (2) Setting Procedure
Interval timer (2)
Set PRM1
Set count value in CR11 CR11 n
Set CRC1 CRC1 08H
Start count CE1 1
; Set 1 in bit 3 of TMC1
INTC11 interrupt
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10.7.3 Pulse width measurement operation In pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input pin (INTP0) is measured. Both the high-level and low-level widths of pulses input to the INTP0 pin must be at least 3 sampling clocks selected by SCS0; if shorter than this, the valid edge will not be detected and a capture operation will not be performed. As shown in Figure 10-26, the timer counter 1 (TM1) value being counted is fetched into the capture/compare register (CR11) set as a capture register in synchronization with a valid edge (set as both rising and falling edges) in the INTP0 pin input, and held there. The pulse width is obtained from the product of the difference between the TM1 count value (Dn) fetched into and held in the CR11 on detection of the nth valid edge and the count value (Dn-1) fetched and held on detection of valid edge n-1, and the number of count clocks (x/fXX; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024). The control register settings are shown in Figure 10-27, and the setting procedure in Figure 10-28. Figure 10-26. Pulse Width Measurement Timing (when CR11 is used as Capture Register)
FFH
FFH
TM1 count value
D1
D3
D0 0H Capture Count start CE1 1 INTP0 external input signal (D1-D0) x x/fXX INTP0 interrupt request (100H-D1+ D2) x x/fXX Capture
D2 Capture Capture
(D3-D2) x x /fXX
Capture/compare register (CR11)
D0
D1
D2
D3
OVF1 Cleard by software
Remark Dn: TM1 count value (n = 0, 1, 2, ...) x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024
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Figure 10-27. Control Register Settings for Pulse Width Measurement (a) Prescaler mode register 1 (PRM1)
7 PRM1 x
6 x
5 x
4 x
3
2
1
0
PRS13 PRS12 PRS11 PRS10
Count clock specification (x/fXX ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024)
(b) Capture/compare control register 1 (CRC1)
7 CRC1 0
6 0
5 0
4 0
3 0
2 1
1 0
0 0 TM1 clearing by match of TM1 & CR10 contents disabled CR11 specified as capture operation TM1 clearing upon capture of CR11 in TM1 disabled
(c) External interrupt mode register 0 (INTM0)
7 INTM0 x
6 x
5 x
4 x
3 1
2 1
1 0
0 x
Both rising & falling edges specified as INTP0 input valid edges
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Figure 10-28. Pulse Width Measurement Setting Procedure
Pulse width measurement
Set PRM1
Set CRC1 CRC1 04H
Set INTM0 Set MK0L
; Specify both edges as INTP0 input valid edges, release interrupt masking
Initialize capture value buffer memory X0 0
Start count CE1 1
; Set 1 in bit 3 of TMC1
Enable interrupts
INTP0 interrupt
Figure 10-29. Interrupt Request Servicing that Calculates Pulse Width
INTP0 interrupt
Calculate pulse width Yn = CR11 - Xn
Store capture value in memory Xn+1 CR11
RETI
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10.8 Cautions (1) While timer/event counter 1 is operating (while the CE1 bit of the timer control register 1 (TMC1) is set), malfunctioning may occur if the contents of the following registers are rewritten. This is because it is undefined which takes precedence in a contention, the change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting. Therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following registers. * Prescaler mode register 1 (PRM1) * Capture/compare control register 1 (CRC1) * CMD2 bit of timer control register 1 (TMC1) (2) If the contents of the compare register (CR1n: n = 0 or 1) coincide with those of TM1 when an instruction that stops timer counter 1 (TM1) operation is executed, the counting operation of TM1 stops, but an interrupt request is generated. In order not to generate the interrupt when stopping the operation of TM1, mask the interrupt in advance by using the interrupt mask register before stopping TM1. Example Program that may generate interrupt request Program that does not generate interrupt request . . . MK0L, #C0H CE1 CIF10 CIF11 . . .
CLR1 OR
CE1 MK0L, #C0H
Interrupt request from timer/event counter 1 occurs between these instructions
OR CLR1 CLR1 CLR1
Disables interrupt from timer/ event counter 1 Clears interrupt request flag from timer/event counter 1
(3) Up to 1 count clock is required after an operation to start timer/event counter 1 (CE1 1) has been performed before timer/ event counter 1 actually starts (refer to Figure 10-30). For example, when using timer/event counter 1 as an interval timer, the first interval time is delayed by up to 1 clock. The second and those that follow are at the specified interval. Figure 10-30. Operation when Counting is Started
Count clock
TM1
0
0
1
2
3
CE1
Timing to start actual counting
Count start command (CE1 1) by software
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(4) While an instruction that writes data to the compare register (CR1n: n = 0, 1) is executed, coincidence between CR1n, to which the data is to be written, and timer counter 1 (TM1) is not detected. Write data to CR1n when timer/event counter 1 is executing counting operation in the timing that the contents of TM1 do not coincide with the value of CR1n before and after writing (e.g., immediately after an interrupt request has been generated because TM1 and CR1n have coincided). (5) Coincidence between TM1 and compare register (CR1n: n = 0, 1) is detected only when TM1 is incremented. Therefore, the interrupt request is not generated even if the same value as TM1 is written to CR1n. (6) When timer/event counter 1 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input, using the timer counter 1 (TM1) alone (refer to Figure 10-31), since the contents of TM1 are 0 in both cases. If it is necessary to make this distinction, the INTP3 interrupt request flag should be used. To make a distinction, use the interrupt request flag of INTP0, as shown in Figure 10-32. Figure 10-31. Example of the Case where the External Event Counter does Not Distinguish between One Valid Edge Input and No Valid Edge Input
INTP0
TM1
0
0
1
2
Cannot be distinguished Count start
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Figure 10-32. To Distinguish whether One or No Valid Edge has been Input with External Event Counter (a) Processing when count is started
Start count
Clear INTP0 interrupt request flag PIF0 0
; Clear PIF0 to 0
Start count CE1 1
; Set CE1 to 1
End
(b) Processing when count value is read
Count value read
Read TM1 contents A TM1
A = 0? NO A A+1
YES YES
; Check TM1 value. If 0, check interrupt request flag. PIF0 = 1? NO ; Check PIF0 contents. If 1, valid edge is input.
End
; Number of input valid edges is set to A register
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[MEMO]
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11.1
Functions
Timer/event counter 2 is 16-bit or 8-bit timer/event counter, and has the following function which the other three timer/ counters do not have: * One-shot timerNote Note The one-shot timer function is a count operation of timer/event counter 2 (TM2/TM2W), and is thus different in nature from the one-shot pulse output function of timer/event counter 0. In this section, the following four basic functions are described in order: * Interval timer * Programmable square-wave output * Pulse width measurement * External event counter (1) Interval timer Generates internal interrupts at preset intervals. Table 11-1. Timer/Event Counter 2 Intervals
Minimum Interval 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s) Maximum Interval 216 x 4/fXX (20.8 ms) Resolution 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s)
216 x 8/fXX (41.7 ms) 216 x 16/fXX (83.4 ms) 216 x 32/fXX (167 ms) 216 x 64/fXX (333 ms) 216 x 128/fXX (667 ms) 216 x 256/fXX (1.33 s) 216 x 512/fXX (2.67 s) 216 x 1,024/fXX (5.33 s)
( ): When fXX = 12.58 MHz
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(2) Programmable square-wave output Outputs square waves independently to the timer output pins (TO2 and TO3). Table 11-2. Timer/Event Counter 2 Programmable Square-Wave Output Setting Range
Minimum Pulse Width 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s) Maximum Pulse Width 216 x 4/fXX (20.8 ms) 216 x 8/fXX (41.7 ms) 216 x 16/fXX (83.4 ms) 216 x 32/fXX (167 ms) 216 x 64/fXX (333 ms) 216 x 128/fXX (667 ms) 216 x 256/fXX (1.33 s) 216 x 512/fXX (2.67 s) 216 x 1,024/fXX (5.33 s)
( ): When fXX = 12.58 MHz Caution The above table is applicable to use of an internal clock.
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(3) Pulse width measurement Detects the pulse width of the signal input to an external interrupt request input pins (INTP1 and INTP2). Table 11-3. Timer/Event Counter 2 Pulse Width Measurement Range
Measurable Pulse WidthNote 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s) to to 216 x 4/fXX (20.8 ms) Resolution 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s)
to
216 x 8/fXX (41.7 ms) 216 x 16/fXX (83.4 ms) 216 x 32/fXX (167 ms) 216 x 64/fXX (333 ms) 216 x 128/fXX (667 ms) 216 x 256/fXX (1.33 s) 216 x 512/fXX (2.67 s)
to
to
to
to
to
to 216 x 1,024/fXX (5.33 s)
( ): When fXX = 12.58 MHz Note The minimum pulse width that can be measured differs depending on the selected value of fCLK. The minimum pulse width that can be measured is the value of 3/fCLK or the value in the above table, whichever greater. (4) External event counter Counts the clock pulses input from the external interrupt request input pin (INTP2) (CI pin input pulses). The clocks that can be input to timer/event counter 2 are shown in Table 11-4. Table 11-4. Clocks Enabled to be Input to Timer/Event Counter 2
When Counting One Edge Maximum frequency Minimum pulse width (High and low levels) fCLK/6 (2.10 MHz) 3/fCLK (0.24 s) When Counting Both Edges fCLK/6 (2.10 MHz) 3/fCLK (0.24 s)
( ): When fCLK = 12.58 MHz and fXX = 12.58 MHz
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11.2
Configuration
Timer/event counter 2 consists of the following registers. * Timer counter (TM2/TM2W) x 1 * Compare register (CR20/CR20W) x 1 * Capture/compare register (CR21/CR21W) x 1 * Capture register (CR22/CR22W) x 1 The block diagram of timer/event counter 2 is shown in Figure 11-1.
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Figure 11-1. Timer/Event Counter 2 Block Diagram
Internal bus
1/8 External interrupt mode register 0 (INTM0) P22/INTP1 ES21 ES20 ES11 ES10
8/16 Compare register (CR20/CR20W) 8 Match 8 INTP1 16 8/16 16 Match Selector
8 MOD1 MOD0
Capture/compare control register 2 (CRC2) CLR22 CLR21 CM21
8
Timer output ENT03 ALV3 ENT02 ALV2 control register (TOC)
Edge detection circuit
PWM/PPG output control
Output control circuit
P36/TO2
CHAPTER 11
INTC20 Capture/compare register (CR21/CR21W) 8 Match 16 Match 16 RESET Timer counter 2 (TM2/TM2W) Overflow 16 Selector Output control circuit P37/TO3
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P23/INTP2/CI
Edge detection circuit
INTP2
INTP2 Selector
TIMER/EVENT COUNTER 2
fXX/1,024 fXX/512 fXX/256 fXX/128 fXX/64 fXX/32 fXX/16 fXX/8 fXX/4 Capture trigger Selector
8
INTC21
fXX
Prescaler
Capture trigger 16
Prescaler mode register 1 PRS23 PRS22 PRS21 PRS20 (PRM1) 8
Capture register (CR22/CR22W) 8/16 8/16
Timer control register 1 (TMC1)
CE2 OVF2 CMD2 BW2
1/8 Internal bus
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(1) Timer counter 2 (TM2/TM2W) TM2/TM2W is a timer counter that counts up the count clock specified by the high-order 4 bits of prescaler mode register 1 (PRM1). An internal clock or external clock can be selected as the count clock. The count operation can be stopped or enabled by means of timer control register 1 (TMC1). The timer counter can select to operate in an 8-bit (TM2) or 16-bit (TM2W) mode. TM2/TM2W can be read only with an 8/16-bit manipulation instruction. When RESET is input, TM2/TM2W is cleared to 00H and the count is stopped. (2) Compare register (CR20/CR20W) CR20/CR20W is an 8/16-bit register that holds the value that determines the interval timer operation cycle. If the contents of the CR20/CR20W register match the contents of TM2/TM2W, an interrupt request (INTC20) and a timer output control signal are generated. This compare register operates as CR20 in the 8-bit mode, and CR20W in the 16-bit mode. CR20/CR20W can be read or written to with an 8/16-bit manipulation instruction. The contents of this register are undefined after RESET input. (3) Capture/compare register (CR21/CR21W) CR21/CR21W is an 8/16-bit register that can be specified as a compare register for detecting a match with the TM2/ TM2W count value or a capture register for capturing the TM2/TM2W count value according to the setting of the capture/ compare control register 2 (CRC2). This capture/compare register operates as CR21 in the 8-bit mode, and CR21W in the 16-bit mode. CR21/CR21W can be read or written to with an 8/16-bit manipulation instruction. The contents of this register are undefined after RESET input. (a) When specified as compare register CR21/CR21W functions as an 8/16-bit register that holds the value that determines the interval timer operation cycle. An interrupt request (INTC21) and a timer output control signal are generated by a match between the contents of the CR21/CR21W register and the contents of TM2/TM2W. Also, the count value can be cleared by a match of the contents. (b) When specified as capture register CR21/CR21W functions as an 8/16-bit register that captures the contents of TM2/TM2W in synchronization with the input of a valid edge on the external interrupt input pin (INTP2) (capture trigger). The contents of the CR21/CR21W register are retained until the next capture trigger is generated. (4) Capture register (CR22/CR22W) CR22/CR22W is an 8/16-bit register that captures the contents of TM2/TM2W. The capture operation is synchronized with the input of a valid edge to the external interrupt request input pin (INTP1) (capture trigger). The contents of the CR22/CR22W register are retained until the next capture trigger is generated. Also, TM2/TM2W can be cleared after a capture operation. This capture register operates as CR22 in the 8-bit mode, and CR22W in the 16-bit mode. CR22/CR22W can be read only with an 8/16-bit manipulation instruction. The contents of this register are undefined after RESET input.
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(5) Edge detection circuit The edge detection circuit detects an external input valid edge. This circuit generates an external interrupt request (INTP1) and capture trigger by detecting the valid edge of the INTP1 pin input specified by the external interrupt mode register 0 (INTM0). It also generates a capture trigger, the count clock of an external event, and external interrupt request (INTP2) by detecting the valid edge from an external interrupt request input pin (INTP2). (6) Output control circuit It is possible to invert the timer output when the CR20/CR21 register contents and the contents of TM2 match or the CR20W/CR21W contents and the contents of TM2W match. A square wave can be output from the timer output pins (TO2/TO3) in accordance with the setting of the high-order 4 bits of the timer output control register (TOC). At this time, PWM output or PPG output can be performed according to the specification of the capture/compare control register 2 (CRC2). Timer output can be disabled/enabled by means of the TOC register. When timer output is disabled, a fixed level is output to the TO2 and TO3 pins (the output level is set by the TOC register). (7) Prescaler The prescaler generates the count clock from the internal system clock. The clock generated by the prescaler is selected by the selector, and is used as the count clock by the timer counter 2 (TM2/TM2W) to perform count operations. (8) Selector The selector selects a signal resulting from dividing the internal clock or the edge detected by the edge detection circuit as the count clock of timer counter 2 (TM2/TM2W).
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11.3
Timer/Event Counter 2 Control Registers
(1) Timer control register 1 (TMC1) In TMC1 the timer/event counter 2 TM2/TM2W count operation is controlled by the high-order 4 bits (the low-order 4 bits control the count operation of timer/event counter 1, TM1/TM1W). TMC1 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The format of TMC1 is shown in Figure 11-2. RESET input clears TMC1 to 00H. Figure 11-2. Timer Control Register 1 (TMC1) Format
7 TMC1 CE2 6 5 4 BW2 3 CE1 2 OVF1 1 0 0 BW1 Address 0FF5FH After reset 00H R/W R/W
OVF2 CMD2
Controls count operation of timer/event counter 1 TM1/TM1W (see Figure 10-2).
BW2
Timer/Event Counter 2 Bit Length Specification 8-bit operation mode 16-bit operation mode
0 1
CMD2 0 1
TM2/TM2W Operation Mode Specificaton Normal mode One-shot mode
OVF2 0 1
TM2/TM2W Overflow Flag No overflow Overflow Note
Note 8-bit operating mode: count up from FFH to 00H In 16-bit operating mode: count up from FFFFH to 0000H CE2 0 1 TM2/TM2W Count Operation Control Count operation stopped with count cleared Count operation enabled
Remark The OVF2 bit is reset by software only.
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(2) Prescaler mode register 1 (PRM1) In PRM1, the count clock to timer/event counter 2 TM2/TM2W is specified by the high-order 4 bits (the low-order 4 bits specify the count clock to timer/event counter 1 TM1/TM1W). PRM1 can be read or written with an 8-bit manipulation instruction. Figure 11-3. RESET input sets PRM1 to 11H. Figure 11-3. Prescaler Mode Register 1 (PRM1) Format
7 6 5 4 3 2 1 0 Address 0FF5EH After reset 11H R/W R/W
The format of PRM1 is shown in
PRM1 PRS23 PRS22 PRS21 PRS20 PRS13 PRS12 PRS11 PRS10
Specifies count clock to timer/event counter 1 (TM1/TM1W) (see Figure 10-3).
(fXX = 12.58 MHz) PRS23 PRS22 PRS21 PRS20 Timer/Event Counter 2 TM2/ TM2W Count Clock Specification Count Clock [Hz] Specification 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 Setting prohibited fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 External clock (CI/INTP2) Setting prohibited Resolution [ s] - 0.32 0.64 1.27 2.54 5.09 10.17 20.35 40.70 81.40 -
Other than the above
Remark fXX: X1 input frequency or oscillation frequency
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(3) Capture/compare control register 2 (CRC2) CRC2 specifies the enabling condition for a timer counter 2 (TM2/TM2W) clear operation by the capture/compare register (CR21/CR21W) or the capture register (CR22/CR22W) and the timer output (TO2/TO3) mode. CRC2 can be read or written with an 8-bit manipulation instruction. The format of CRC2 is shown in Figure 11-4. RESET input sets CRC2 to 10H. Figure 11-4. Capture/Compare Control Register 2 (CRC2) Format
7 CRC2
6
5
4 1
3
2
1 0
0 0
Address 0FF33H
After reset 10H
R/W R/W
MOD1 MOD0 CLR22
CLR21 CM21
MOD1 MOD0 CLR22 CLR21 CM21
CR21 Operation Specification
Timer Output Mode Specification TO2 TO3
TM2 Clear Operation
0 0 0
0 0 0
0 0 1
0 1 0
0 0 0
Compare operations
Toggle output Toggle output Not cleared Toggle output Toggle output Cleared if TM2 and CR21 match Toggle output Toggle output Cleared after TM2 contents are captured in CR22 by INTP1 Toggle output Toggle output Cleared by match of TM2 and CR21 or after TM2 contents are captured in CR22 by INTP1 PWM output PWM output PPG output Toggle output Not cleared PWM output Not cleared
0
0
1
1
0
0 1 1 0 0 0
1 0 1 0 0 1
0 0 0 0 0 0
0 0 1 0 1 0
0 0 0 1 1 1 Capture operations
Toggle output Cleared if TM2 and CR21 match Not cleared Cleared after TM2 contents are captured in CR21 by INTP2 Not cleared
Toggle output Toggle output PWM output
Other than the above
Setting prohibited
Remark The register names in the 8-bit operation mode are shown in this figure. In the 16-bit operation mode, the register names TM2, CR20, CR21, and CR22 are TM2W, CR20W, CR21W, and CR22W, respectively.
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(4) Timer output control register (TOC) TOC is an 8-bit register that controls output enabling/disabling of the active level of timer output. The operation of the timer output pins (TO2/TO3) by timer/event counter 2 is controlled by the high-order 4 bits (the low-order 4 bits control the operation of the timer output pins (TO0/TO1) by timer/event counter 0). TOC can be read or written with an 8-bit manipulation instruction or bit manipulation instruction. The format of TOC is shown in Figure 11-5. RESET input clears TOC to 00H. Figure 11-5. Timer Output Control Register (TOC) Format
7 TOC
6
5
4
3
2
1
0
Address 0FF31H
After reset 0000H
R/W R/W
ENTO3 ALV3 ENTO2 ALV2 ENTO1 ALV1 ENTO0 ALV0
Control operation of timer output pins (TO0 & TO1) by timer/event counter 0 (see Figure 9-5). ALV2 TO2 Pin Active Level Toggle Output Specification 0 1 Low level High level PWM/PPG Output Specification High level Low level
ENTO2 0 1
TO2 Pin Operation Specification ALV2 output Pulse output enabled
ALV3
TO3 Pin Active Level Toggle Output Specification PWM/PPG Output Specification High level Low level
0 1
Low level High level
ENTO3 0 1
TO3 Pin Operation Specification ALV3 output Pulse output enabled
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11.4 11.4.1
Timer Counter 2 (TM2) Operation Basic operation
8-bit operation mode/16-bit operation mode control can be performed for timer/event counter 2 by means of bit 0 (BW2) of timer control register 2 (TMC2)Note. In the timer/event counter 2 count operation, a count-up is performed using the count clock specified by the high-order 4 bits of prescaler mode register 1 (PRM1). Count operation enabling/disabling is controlled by bit 3 (CE2) of TMC2 (timer/event counter 2 operation control is performed by the high-order 4 bits of the timer control register 1 (TMC1). When the CE2 bit is set (to 1) by software, the contents of TM2 are cleared to 0H on the first count clock, and then the count-up operation is performed. When the CE2 bit is cleared (to 0) by software, TM2 becomes 0H immediately, and capture operations and match signal generation are stopped. If the CE2 bit is set (to 1) again when it is already set (to 1), the TM2 count operation is not affected (see Figure 116 (b)). TM2/TM2W is cleared to 0H when the count clock is input while the value of TM2 is FFH in the 8-bit operation mode or while the value of TM2W is FFFFH in the 16-bit operation mode. At this time, OVF2 bit is set and the overflow signal is sent to the output control circuit. OVF2 bit is cleared by software only. The count operation is continued. When RESET is input, TM2 is cleared to 0H, and the count operation is stopped. Note Unless otherwise specified, the functions of timer counter 2 in the 8-bit operation mode are described hereafter. In the 16-bit operation mode, TM2, CR20, CR21, and CR22 operate as TM2W, CR20W, CR21W, and CR22W, respectively.
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Figure 11-6. Basic Operation in 8-Bit Operation Mode (BW2 = 0) (a) Count started count disabled count started
Count clock
TM2
0H
0H
1H
2H
0FH
10H 11H
0H
0H
1H
CE2
Count started CE2 1
Count stopped CE2 0
Count started CE2 1
(b) When "1" is written to the CE2 bit again after the count starts
Count clock
TM2
0H
0H
1H
2H
3H
4H
5H
6H
CE2
Count started CE2 1
Rewrite CE2 1
(c) Operation when TM2 = FFH
Count clock fCLK/8
TM2
FEH
FFH
0H
1H
OVF2
Cleared by software OVF2 0
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Figure 11-7. Basic Operation in 16-Bit Operation Mode (BW2 = 1) (a) Count started count disabled count started
Count clock
TM2W
0H
0H
1H
2H
FFH 100H 101H
0H
0H
1H
CE2
Count started CE2 1
Count stopped CE2 0
Count started CE2 1
(b) When "1" is written to the CE2 bit again after the count starts
Count clock
TM2W
0H
0H
1H
2H
3H
4H
5H
6H
CE2
Count started CE2 1
Rewrite CE2 1
(c) Operation when TM2W = FFFFH
Count clock fCLK/8
TM2W
FFFEH FFFFH
0H
1H
OVF2
Cleared by software OVF2 0
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11.4.2
Clear operation
(1) Clear operation after match with compare register and capture operation Timer counter 2 (TM2) can be cleared automatically after a match with the compare register (CR2n: n = 0, 1) and a capture operation. When a clearance source arises, TM2 is cleared to 0H on the next count clock. Therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. Figure 11-8. TM2 Clearance by Match with Compare Register (CR20/CR21)
Count clock
TM2
n-1
n
0
1
Compare register (CR2n)
n
TM2 and CR2n match
Cleared here
Figure 11-9. TM2 Clearance after Capture Operation
Count clock
TM2
n-1
n
0
1
2
INTP1
TM2 is captured in CR22 here Cleared here
(2) Clear operation by CE2 bit of timer control register 1 (TMC1) TM2 is also cleared when the CE2 bit of the TMC1 is cleared (to 0) by software. The clear operation is performed immediately after clearance (to 0) of the CE2 bit.
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Figure 11-10. Clear Operation when CE2 Bit is Cleared (0) (a) Basic operation
Count clock
TM2
n-1
n
0
CE2
(b) Restart before count clock is input after clearance
Count clock
TM2
n-1
n
0
0
1
2
CE2
If the CE2 bit is set (to 1) before this count clock, this count clock starts counting from 0.
(c) Restart after count clock is input after clearance
Count clock
TM2
n-1
n
0
0
0
1
CE2
If the CE2 bit is set (to 1) from this count clock onward, the count starts from 0 on the count clock after the CE2 bit is set (to 1).
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11.5
External Event Counter Function
Timer/event counter 2 can count clock pulses input from external interrupt request input pin (INTP2/CI). No special selection method is needed for the external event counter operation mode. When the timer counter 2 (TM2) count clock is specified as external clock input by the setting of the high-order 4 bits of prescaler mode register 1 (PRM1), TM2 operates as an external event counter. The maximum frequency of external clock pulses that can be counted by TM2 as the external event counter is 2.10 MHz (fCLK = 12.58 MHz) irrespective of whether only one edge or both edges are counted on INTP2/CI input. The pulse width of INTP2/CI input must be at least 3 system clocks (0.24 s: fCLK = 12.58 MHz) for both the high level and low level. If the pulse width is shorter than this, the pulse may not be counted. The timer/event counter 2 external event count timing is shown in Figure 11-11. Figure 11-11. Timer/Event Counter 2 External Event Count Timing (1) Counting one edge (maximum frequency = fCLK/6)
3/fCLK (MIN.) 3/fCLK (MIN.) 6/fCLK (MIN.) CI 2-3/fCLK
ICI
TM2
Dn
Dn+1
Dn+2
Dn+3
Remark ICI: CI input signal after passing through edge detection circuit (2) Counting both edges (maximum frequency = fCLK/6)
3/fCLK (MIN.) 3/fCLK (MIN.) CI
6/fCLK (MIN.)
2-3/fCLK ICI
TM2
Dn
Dn+1
Dn+2
Dn+3
Dn+4
Dn+5
Remark ICI: CI input signal after passing through edge detection circuit
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The TM2 count operation is controlled by the CE2 bit of the timer control register 1 (TMC1) in the same way as with the basic operation. When the CE2 bit is set (to 1) by software, the contents of TM2 are set to 0H and the count-up operation is started on the initial count clock. When the CE2 bit is cleared (to 0) by software during a TM2 count operation, the contents of TM2 are set to 0H immediately and the stopped state is entered. The TM2 count operation is not affected if the CE2 bit is set (to 1) by software again when it is already set (to 1). Caution When timer/event counter 2 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input using timer counter 2 (TM2) alone (see Figure 11-12), since the contents of TM2 are 0 in both cases. If it is necessary to make this distinction, the INTP2 interrupt request flag should be used (the INTP2 pin and CI pin have a dual function, and both functions can be used at the same time). An example is shown in Figure 11-13. Figure 11-12. Example of the Case where the External Event Counter does Not Distinguish between One Valid Edge Input and No Valid Edge Input
INTP2/CI
TM2
0
0
1
2
No distinction made
Count start
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Figure 11-13. To Distinguish whether One or No Valid Edge has been Input with External Event Counter (a) Processing when count is started
Start count
Clear INTP2 interrupt request flag PIF2 0
; Clear PIF2 to 0
Start count CE2 1
; Set CE2 to 1
End
(b) Processing when count value is read
Count value read
Read TM2 contents A TM2
A = 0?
YES ; Check TM2 value If 0, check interrupt request flag YES PIF2 = 1? NO ; Check PIF2 contents If 1, there is a valid edge
NO
A A+1
End
; Number of input valid edges is set in A register
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11.6
One-Shot Timer Function
Timer/event counter 2 has an operation mode in which it stops automatically when a full count value is reached (FFH/ FFFFH) as a result of counting by timer counter 2 (TM2/TM2W). Figure 11-14. One-Shot Timer Operation
FFH or FFFFH
TM2/TM2W count value CR21/CR21W value
0H Count start CE2 1 INTC21 interrupt request Clear OVF2 0
OVF2
As shown in Figure 11-14, the respective one-shot interrupt is generated when the value (0H to FFH/FFFFH) set beforehand in the CR20, CR21/CR21W, or CR21W and TM2/TM2W value match. The one-shot timer operation mode is specified by setting (to 1) bit 5 (CMD2) of timer control register 1 (TMC1) by software. The TM2/TM2W count operation is controlled by the CE2 bit of the TMC1 as with the basic operation. When the CE2 bit is set (to 1) by software, the contents of TM2/TM2W are set to 0H and the count-up operation is started on the initial count clock. When the contents of TM2/TM2W reach FFH/FFFFH (full count) as a result of the count-up operation, bit 6 (OVF2) of the TMC1 are set (to 1), and TM2/TM2W stops with the count at FFH/FFFFH. The one-shot timer operation is started again from the count-stopped state by clearing (to 0) the OVF2 bit by software. When the OVF2 bit is cleared (to 0), the contents of TM2/TM2W become 0H and the count-up operation is restarted on the next count clock. If the CE2 bit is cleared (to 0) by software during a TM2/TM2W count operation, the contents of TM2/TM2W are set to 0H immediately and the stopped state is entered. The TM2/TM2W count operation is not affected if the CE2 bit is set (to 1) by software again when it is already set (to 1).
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11.7 11.7.1
Compare Register, Capture/Compare Register, and Capture Register Operation Compare operations
Timer/event counter 2 performs compare operations in which the value set in the compare register (CR20) and the capture/compare register (CR21) specified for compare operation is compared with the timer counter 2 (TM2) count value. If the count value of TM2 matches the preset value of the CR20, and CR21 when a compare operation is performed, as the result of the count operation, a match signal is sent to the output control circuit, and an interrupt request signal (INTC20/INTC21) is generated at the same time. After a match with the CR20 or CR21 value, the TM2 contents can be cleared, and the timer functions as an interval timer that repeatedly counts up to the value set in the CR20 or CR21. Figure 11-15. Compare Operation in 8-Bit Operation Mode
FFH
FFH
TM2 count value CR21 value CR21 value
CR20 value 0H Count start CE2 1 INTC20 interrupt request Match Match
CR20 value Match Match
INTC21 interrupt request
TO2 pin output ENTO2 = 1 ALV2 = 1 Inactive level
TO3 pin output ENTO2 = 1 Inactive level ALV3 = 0
OVF2
Cleared by software
Remark CLR21 = 0, CLR22 = 0, BW2 = 0
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Figure 11-16. Compare Operation in 16-Bit Operation Mode
FFFFH
FFFFH
TM2W count value CR21W value CR21W value
CR20W value 0H Count start CE2 1 Match Match
CR20W value Match Match
INTC20 interrupt request
INTC21 interrupt request
TO2 pin output ENTO2 = 1 ALV2 = 1 Inactive level TO3 pin output Inactive level ENTO2 = 1 ALV3 = 0
OVF2
Cleared by software
Remark CLR21 = 0, CLR22 = 0, BW2 = 1
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Figure 11-17. TM2 Clearance after Match Detection
FFH CR20 TM2 count value
CR21
CR21
CR21
0H Count start CE2 1 CLR21 0 Count disabled CE2 0 Count start CE2 1 CLR21 1 Clear Clear
INTC20 interrupt request INTC21 interrupt request TO2 pin output ENTO2 1 ALV2 1 TO3 pin output ENTO3 1 ALV3 1 OVF2
Inactive level
Inactive level
Cleared by software
Remark CLR22 = 0 11.7.2 Capture operations
Timer/event counter 2 performs capture operations in which the timer counter 2 (TM2) count value is fetched into the capture register in synchronization with an external trigger, and retained there. A valid edge detected from the input of the external interrupt request input pins (INTP1/INTP2) is used as the external trigger (capture trigger). The count value of TM2 in the process of being counted in synchronization with the capture trigger is fetched into the capture register (CR22) in synchronization with INTP1, or into the capture/compare register (CR21) when a capture operation is specified in synchronization with INTP2, and is retained there. The contents of CR21 and CR22 are retained until the next capture triggers corresponding to CR21 and CR22 are generated. The capture trigger valid edge is set by means of external interrupt mode register 0 (INTM0). If both rising and falling edges are set as capture triggers, the width of pulses input from off-chip can be measured, and if a capture trigger is generated by a single edge, the input pulse cycle can be measured. See Figure 22-1 for details of the INTM0 format. When CR21 is used as a capture register, TM2 can be cleared as soon as the contents of TM2 have been captured by capture trigger to CR21 or CR22.
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Figure 11-18. Capture Operation in 8-Bit Operation Mode
FFH
TM2 count value D1 D0
D4 D3 D2 D7 D6 D5
0H Count start CE 1 INTP2 pin input
INTP2 interrupt request
Capture register (CR21)
D1
D2
D4
D5
D7
INTP1 pin input
INTP1 interrupt request
Capture register (CR22)
D0
D3
D6
OVF2
Remark Dn: TM2 count value (n = 0, 1, 2, ...) CM21 = 1, CLR21 = 0, CLR22 = 0, BW2 = 0
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Figure 11-19. Capture Operation in 16-Bit Operation Mode
FFFFH
TM2W count value D1 D0
D4 D3 D2 D7 D6 D5
0H Count start CE 1 INTP2 pin input
INTP2 interrupt request
Capture register (CR21W)
D1
D2
D4
D5
D7
INTP1 pin input
INTP1 interrupt request
Capture register (CR22W)
D0
D3
D6
OVF2
Remark Dn: TM2W count value (n = 0, 1, 2, ...) CM21 = 1, CLR21 = 0, CLR22 = 0, BW2 = 0
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Figure 11-20. TM2 Clearance after Capture Operation
N1
N4
TM2 count value
N2
N3
N5
0H Capture Capture Capture Capture Capture
INTP1 pin input
INTP1 interrupt request
Capture/compare register (CR22)
N1
N2
N3
N4
Remark CLR21 = 0, CLR22 = 1 11.8 Basic Operation of Output Control Circuit
The output control circuit controls the timer output pins (TO2/TO3) level by means of match signals from the compare register (CR22). The operation of the output control circuit is determined by the timer output control register (TOC) and capture/compare control register 2 (CRC2) (see Table 11-5). When TO2/TO3 signal is output to a pin, the relevant pin must be in control mode in the port 3 mode register (PMC3).
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Table 11-5. Timer Output (TO2/TO3) Operations
TOC ENTO3 0 0 1 1 0 1 1
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CRC2 ALV2 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 MOD1 x 0 0 0 0 0 0 1 1 1 1 1 1 MOD0 x 0 0 0 1 1 1 0 0 0 1 1 1 CLR22 x xNote xNote xNote 0 0 0 0 0 0 0 0 0 CLR21 x x x x 0 0 0 0 0 0 1 1 1
TMC1 CMD2 x x x x 0 0 0 0 0 0 0 0 0
TO3
TO2
ALV3 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
ENTO2 0 1 0 1 1 0 1 1 0 1 1 0 1
High/low level fixed High/low level fixed Toggle output (active-low/high) Toggle output (active-low/high) High/low level fixed Toggle output (active-low/high) Toggle output (active-low/high) High/low level fixed PWM output (active-high/low) PWM output (active-high/low) High/low level fixed Toggle output (active-low/high) Toggle output (active-low/high)
High/low level fixed Toggle output (active-low/high) High/low level fixed Toggle output (active-low/high) PWM output (active-high/low) High/low level fixed CHAPTER 11 PWM output (active-high/low) PWM output (active-high/low) High/low level fixed PWM output (active-high/low) PPG output (active-high/low) High/low level fixed PPG output (active-high/low)
0 1 1 0 1 1
TIMER/EVENT COUNTER 2
Note
CLR22 is normally set to 0 in this case.
Remarks 1. 0/1 in the ALVn (n = 2, 3) columns correspond to the items on the left and right of the slash ("/") in the TOn (n = 2, 3) columns respectively. 2. "x" indicates 0 or 1. 3. Combinations not shown in this table are prohibited to use in that combination.
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11.8.1
Basic operation
Setting (to 1) the ENTOn (n = 2, 3) bit of the timer output control register (TOC) enables timer output (TOn: n = 2, 3) to be varied at a timing in accordance with the settings of MOD0, MOD1, and CLR21 bits of capture/compare control register 2 (CRC2). Clearing (to 0) ENTOn sets the TOn to a fixed level. The fixed level is determined by the ALVn (n = 2, 3) bit of the TOC. The level is high when ALVn is 0, and low when 1. 11.8.2 Toggle output
Toggle output is an operation mode in which the output level is inverted each time the compare register (CR20/CR21) value coincides with the timer counter 2 (TM2) value. The output level of timer output (TO2) is inverted by a match between CR20 and TM2, and the output level of timer output (TO3) is inverted by a match between CR21 and TM2. When timer/event counter 2 is stopped by clearing (to 0) the CE2 bit of the timer control register 1 (TMC1), the inactive level (ALVn: n = 0, 1) is output. Figure 11-21. Toggle Output Operation
FFH
FFH
FFH
FFH
FFH
TM2 count value
CR21 value CR20 value
CR21 value CR20 value
CR21 value CR20 value
CR21 value CR20 value
0H
ENTO0 Instruction execution TO2 output (ALV2 = 1) Instruction execution Instruction execution
ENTO3
Instruction execution TO3 output (ALV3 = 0)
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Table 11-6. TO2/TO3 Toggle Output (fXX = 12.58 MHz)
Count Clock fXX/4 (0.32 s) fXX/8 (0.64 s) fXX/16 (1.27 s) fXX/32 (2.54 s) fXX/64 (5.09 s) fXX/128 (10.17 s) fXX/256 (20.35 s) fXX/512 (40.70 s) fXX/1,024 (81.40 s) Minimum Pulse Width 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s) Maximum Pulse Width 216 x 4/fXX (20.8 ms) 216 x 8/fXX (41.7 ms) 216 x 16/fXX (83.4 ms) 216 x 32/fXX (167 ms) 216 x 64/fXX (333 ms) 216 x 128/fXX (667 ms) 216 x 256/fXX (1.33 s) 216 x 512/fXX (2.67 s) 216 x 1,024/fXX (5.33 s)
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11.8.3
PWM output
(1) Basic operation of PWM output In this mode, a PWM signal with the period in which timer counter 2 (TM2) reaches a full count used as one cycle is output. The timer output (TO2) pulse width is determined by the value of compare register (CR20), and the timer output (TO3) pulse width is determined by the value of compare register (CR21). When this function is used, the CLR21 bit and CLR22 bit of capture/compare control register 2 (CRC2) and the CMD2 bit of timer control register 1 (TMC1) must be set to 0. The pulse cycle and pulse width are as shown below. (a) BW2 = 0 * PWM cycle = 256 x x/fXX * PWM pulse width = CR2n x x/fXXNote; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 Note 0 cannot be set in the CR2n. PWM pulse width PWM CR2n 256
*
Duty =
=
(b) BW2 = 1 * PWM cycle = 65,536 x x/fXX * PWM pulse width = CR2n x x/fXXNote; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 Note 0 cannot be set in the CR2n. PWM pulse width PWM cycle CR2n 65,536
*
Duty =
=
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Figure 11-22. PWM Pulse Output (BW2 = 0)
FFH CR20 TM2 count value Count start 0H Interrupt CR20
FFH CR20
FFH
TO2 Pulse width Pulse cycle Pulse width Pulse cycle
Remark ALV2 = 0 Table 11-7. TO2/TO3 PWM Cycle (fXX = 12.58 MHz, BW2 = 0)
Count Clock fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 Minimum Pulse Width [s] 0.32 0.64 1.27 2.54 5.09 10.17 20.35 40.70 81.40 PWM Cycle [ms] 0.08 0.16 0.33 0.65 1.30 2.60 5.21 10.42 20.84 PWM Frequency [Hz] 12,286 6,143 3,071 1,536 768 384 192 96 48
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Figure 11-23. PWM Pulse Output (BW2 = 1)
FFFFH CR20 TM2 count value Count start 0H Interrupt CR20
FFFFH CR20
FFFFH
TO2 Pulse width Pulse cycle Pulse width Pulse cycle
Remark ALV2 = 0 Table 11-8. TO2/TO3 PWM Cycle (fXX = 12.58 MHz, BW2 = 1)
Count Clock fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 Minimum Pulse Width [s] 0.32 0.64 1.27 2.54 5.09 10.17 20.35 40.70 81.40 PWM Cycle [s] 0.02 0.04 0.08 0.17 0.33 0.67 1.33 2.67 5.33 PWM Frequency [Hz] 47.6 23.8 12.0 6.0 3.0 1.5 0.7 0.4 0.2
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Figure 11-24 shows an example of 2-channel PWM output, and Figure 11-25 shows the case where FFFFH is set in the CR20W. Figure 11-24. Example of PWM Output Using TM2W
FFFFH
FFFFH CR21W CR21W
FFFFH
TM2W count value
CR20W CR20W CR20W
0H INTC20
INTC21 TO2
TO3
Remark ALV2 = 0, ALV3 = 0 Figure 11-25. Example of PWM Output when CR20W = FFFFH
FFFFH FFFEH
FFFFH FFFEH
FFFFH
Count clock cycle T TM2W count value 1 0 INTC20 0 2 1 0 2
OVF2
TO2 Pulse width Pulse cycle = 256T T . Duty =. 255 x 100 = 99.6 (%) 256
Remarks 1. ALV2 = 0 2. T = x/fXX (x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024)
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(2) Rewriting compare registers (CR20, CR21) The output level of the timer output (TOn + 2: n + 2 = 2, 3) is not inverted even if the CR2n (n = 0, 1) value matches the timer counter 2 (TM2) value more than once during one PWM output cycle. Figure 11-26. Example of Compare Register (CR20W) Rewrite
FFFFH FFFFH
T2 TM2W count value T1 T1
T2
0H CR20W T1 T2
TO2 CR20W rewrite CR20W and TM2W values match, but TO2 does not change here.
Remark ALV2 = 1 If a value smaller than that of the TM2 is set as the CR2n value, a 100% duty PWM signal will be output. CR2n rewriting should be performed by the interrupt due to a match between TM2 and the CR2n on which the rewrite is performed. Figure 11-27. Example of 100% Duty with PWM Output
FFH FFH FFH FFH
n1 n1 TM2 count value n2 0H n3 n2 n2
CR20
n1
n2
TO2
When value n2 which is smaller than the TM2 value n3 is written to CR20 here, the duty of this period will be 100%.
Remark
ALV2 = 0
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(3) Stopping PWM output If timer/event counter 2 is stopped by clearing (to 0) the CE2 bit of the timer control register 1 (TMC1) during PWM signal output, the active level is output. Figure 11-28. When Timer/Event Counter 2 is Stopped During PWM Signal Output
FFFFH
FFFFH
CR20W TM2W count value
CR20W
0H
TO2
Remark ALV2 = 1 Caution The output level of the TOn (n = 2, 3) pin when timer output is disabled (ENTOn = 0: n = 2, 3) is the inverse of the value set in ALVn (n = 2, 3) bits. Caution is therefore required as the active level is output when timer output is disabled when the PWM output function has been selected.
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11.8.4
PPG output
(1) Basic operation of PPG output This function outputs a square-wave with the time determined by compare register CR21 value as one cycle, and the time determined by compare register CR20 value as the pulse width. The PWM output PWM cycle is made variable. This signal can only be output from timer output (TO2). When this function is used, it is necessary to set the CLR21 bit of capture/compare control register 2 (CRC2) to 1 and the CLR22 bit to 0, and to set the CMD2 bit of timer control register 1 (TMC1) to 0. The pulse cycle and pulse width are as shown below. * PPG cycle = (CR21 + 1) x x/fXX; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 * PPG pulse width = CR20 x x/fXX where 1 CR20 CR21
CR20 PPG pluse width = CR21 + 1 PPG cycle
* Duty =
Figure 11-29 shows an example of PPG output using timer counter 2 (TM2), Figure 11-30 shows an example of the case where CR20 = CR21.
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Figure 11-29. Example of PPG Output Using TM2
CR21
CR21
CR21
TM2 count value Count start 0H INTC20
CR20
CR20
CR20
INTC21 TO2 (PPG output)
Pulse width
TO3 (timer output)
Pulse cycle
Remark ALV2 = 0, ALV3 = 0 Table 11-9. TO2 PPG Output (fXX = 12.58 MHz)
Count Clock fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 Minimum Pulse Width [s] 0.32 0.64 1.27 2.54 5.09 10.17 20.35 40.70 81.40 PPG Cycle [s] 0.64 s to 20.84 ms 1.27 s to 41.68 ms 2.54 s to 83.35 ms 5.09 s to 166.71 ms 10.17 s to 333.41 ms 20.35 s to 666.82 ms 40.70 s to 1.33 s 81.40 s to 2.67 s 162.80 s to 5.38 s PPG Frequency [Hz] 1,572 kHz to 48.0 Hz 786 kHz to 24.0 Hz 393 kHz to 12.0 Hz 197 kHz to 6.0 Hz 98.3 kHz to 3.0 Hz 49.1 kHz to 1.5 Hz 24.6 kHz to 0.7 Hz 12.3 kHz to 0.4 Hz 6.1 kHz to 0.2 Hz
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Figure 11-30. Example of PPG Output when CR20 = CR21
n n-1
n n-1
n
Count cycle T TM2 count value 1 0 INTC20 INTC21 0 2 1 0 2
TO2 Pulse width = nT Pulse cycle = (n+1) T
Remark ALV2 = 0 T = x/fXX (x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024)
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(2) Rewriting compare register (CR20) The output level of the timer output (TO2) is not changed even if the CR20 value matches the timer counter 2 (TM2) value more than once during one PPG output cycle. Figure 11-31. Example of Compare Register Rewrite
CR21
CR21
CR21
T2 TM2 count value T1 T1
T2 T1
0H CR20 T1 T2
TO2 CR20 rewrite CR20 and TM2 values match, but TO2 does not change here.
Remark ALV2 = 1
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If a value equal to or less than the TM2 value is written to CR20 before the CR20 and TM2 match, the duty of that PPG cycle will be 100%. CR20 rewriting should be performed by the interrupt due to a match between TM2 and CR20. Figure 11-32. Example of 100% Duty with PPG Output
CR21
CR21
CR21
CR21
n1 n1 TM2 count value n2 0H n3 n2 n2
CR20
n1
n2
TO2
When value n2 which is smaller than the TM2 value n3 is written to CR20 here, the duty of this period will be 100%.
Remark ALV2 = 0 Caution If the PPG cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of CR20 cannot be rewritten by interrupt processing that is performed on match between TM2 and CR20. Use another method (for example, to poll the interrupt request flags by software with all the interrupts masked).
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(3) Rewriting compare register (CR21) If the current value of the CR21 is changed to a smaller value, and the CR21 value is made smaller than the timer counter 2 (TM2) value, the PPG cycle at that time will be extended to the time equivalent to a full-count by TM2. If CR21 is rewritten after the compare register (CR20) and TM2 match, the output level at this time will be the inactive level until TM2 overflows and becomes 0, and will then return to normal PPG output. If CR21 is rewritten before CR20 and TM2 match, the active level will be output until CR20 and TM2 match. If CR20 and TM2 match before TM2 overflows and becomes 0, the inactive level is output at that point. When TM2 overflows and becomes 0, the active level will be output, and normal PPG output will be restored. CR21 rewriting should be performed by the interrupt due to a match between TM2 and CR21, etc. Figure 11-33. Example of Extended PPG Output Cycle
Full count value
n1 n3 TM2 count value
n1 n3 n5 n2
n1
n2 n4
0H
CR20
n3
n4
CR21
n1
n2
TO2
When value n2 smaller than the TM2 value n5 is written to CR21 here, the PPG cycle is extended.
TO2 becomes inactive level when CR20 and TM2 match, otherwise it remains at the active level.
Remark ALV2 = 1 Caution If the PPG cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of CR2n cannot be rewritten by interrupt processing that is performed on match between timer counter 2 (TM2) and compare register (CR2n: n = 0, 1). Use another method (for example, to poll the interrupt request flags by software with all the interrupts masked).
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(4) Stopping PPG output If timer/event counter 2 is stopped by clearing (to 0) the CE2 bit of the timer control register 1 (TMC1) during PPG signal output, the active level is output irrespective of the output level at the time timer/event counter 2 was stopped. Figure 11-34. When Timer/Event Counter 2 is Stopped During PPG Signal Output
CR21
CR21
CR20 TM2 count value
CR20
0H
TO2
Caution The output level of the TOn (n = 2, 3) pin when timer output is disabled (ENTOn = 0: n = 2, 3) is the inverse value of the value set in ALVn (n = 2, 3) bits. Caution is therefore required as the active level is output when timer output is disabled when the PPG output function has been selected.
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11.9 11.9.1
Examples of Use Operation as interval timer (1)
When timer counter 2 (TM2) is made free-running and a fixed value is added to the compare register (CR2n: n = 0, 1) in the interrupt service routine, TM2 operates as an interval timer with the added fixed value as the cycle (see Figure 11-35). The control register settings are shown in Figure 11-36, the setting procedure in Figure 11-37, and the processing in the interrupt service routine in Figure 11-38. Figure 11-35. Interval Timer Operation (1) Timing
FFH MOD (3n)
FFH
n TM2 count value MOD (2n)
0H Timer start Compare register (CR20) n MOD (2n) MOD (3n) MOD (4n)
INTC20 interrupt request Interval
Rewritten by interrupt program Interval
Rewritten by interrupt program Interval
Rewritten by interrupt program
Remark Interval = n x x/fXX 1 n FFH, x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024
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Figure 11-36. Control Register Settings for Interval Timer Operation (1) (a) Prescaler mode register 1 (PRM1)
7 PRM1
6
5
4
3 0
2 x
1 x
0 x Count clock specification (x/fXX ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024, or external clock)
PRS23 PRS22 PRS21 PRS20
(b) Capture/compare control register 2 (CRC2)
7 CRC2 0
6 0
5 0
4 1
3 0
2 0
1 0
0 0 TM2 clearing disabled
TO2 & TO3 both toggle outputs
(c) Timer control register 1 (TMC1)
7 TMC1 1
6 0
5 0
4 0
3 x
2 x
1 0
0 0 Normal mode Overflow flag Count operation enabled
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Figure 11-37. Interval Timer Operation (1) Setting Procedure
Interval timer (1)
Set PRM1
Set count value in CR20 CR20 n
Set CRC2 CRC2 10H
Set TMC1 CE2 1 CMD2 0
; Set 1 in bit 7 of TMC1 Set normal mode (CMD2 = 0)
INTC20 interrupt
Figure 11-38. Interval Timer Operation (1) Interrupt Request Servicing
INTC20 interrupt
Calculate timer value that will generate next interrupt CR20 CR20+n
Other interrupt service program
RETI
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11.9.2
Operation as interval timer (2)
TM2 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see Figure 11-39). The control register settings are shown in Figure 11-40, and the setting procedure in Figure 11-41. Figure 11-39. Interval Timer Operation (2) Timing
n
n
TM2 count value
0H Count start Compare register (CR21) Clear n Clear
INTC21 interrupt request
Interrupt acknowledged Interval Interval
Interrupt acknowledged
Remark Interval = (n+1) x x/fXX 0 n FFH, x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024
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Figure 11-40. Control Register Settings for Interval Timer Operation (2) (a) Prescaler mode register 1 (PRM1)
7 PRM1 6 5 4 3 0 2 x 1 x 0 x
PRS23 PRS22 PRS21 PRS20
Count clock specification (x/fXX ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024, or external clock)
(b) Capture/compare control register 2 (CRC2)
7 CRC2 0 6 0 5 0 4 1 3 1 2 0 1 0 0 0 TM2 clearing by match of CR21 & TM2 contents enabled TM2 clearing by capture operation disabled TO2 & TO3 both toggle outputs
(c) Timer control register 1 (TMC1)
7 TMC1 1
6 0
5 0
4 0
3 x
2 x
1 0
0 0 Normal mode Overflow flag Count operation enabled
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Figure 11-41. Interval Timer Operation (2) Setting Procedure
Interval timer
Set PRM1
Set count value in CR21 CR21 n
Set CRC2 CRC2 18H
Set TMC1 CE2 1 CMD2 0
; Set 1 in bit 7 of TMC1 Set normal mode (CMD2 = 0)
INTC21 interrupt
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11.9.3
Pulse width measurement operation
In pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input pin (INTP1) are measured. Both the high-level and low-level widths of pulses input to the INTP1 pin must be at least 3 system clocks (0.24 s: fCLK = 12.58 MHz); if shorter than this, the valid edge will not be detected and a capture operation will not be performed. As shown in Figure 11-42, the timer counter 2 (TM2) value being counted is fetched into the capture register (CR22) in synchronization with a valid edge (specified as both rising and falling edges) in the INTP1 pin input, and held there. The pulse width is obtained from the product of the difference value between the TM2 count value (Dn) fetched into and held in the CR22 on detection of the nth valid edge and the count value (Dn-1) fetched and held on detection of n-1th valid edge, and the number of n-1th count clocks (x/fXX; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024). The control register settings are shown in Figure 11-43, and the setting procedure in Figure 11-44. Figure 11-42. Pulse Width Measurement Timing
FFH
FFH
TM2 count value
D1
D3
D0 0H Capture Count start Capture
D2 Capture Capture
INTP1 external input signal (D1-D0) x x/fXX INTP1 interrupt request (100H-D1+ D2) x x/fXX (D3-D2) x x/fXX
Capture register (CR22)
D0
D1
D2
D3
OVF2
Cleared by software
Remark Dn: TM2 count value (n = 0, 1, 2, ...) x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024
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Figure 11-43. Control Register Settings for Pulse Width Measurement (a) Prescaler mode register 1 (PRM1)
7 PRM1
6
5
4
3 0
2 x
1 x
0 x
PRS23 PRS22 PRS21 PRS20
Count clock specification (x/fXX ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024, or external clock)
(b) Capture/compare control register 2 (CRC2)
7 CRC2 0
6 0
5 0
4 1
3 0
2 0
1 0
0 0 TM2 clearing disabled
(c) Timer control register 1 (TMC1)
7 TMC1 1
6 0
5 0
4 0
3 x
2 x
1 0
0 0 Normal mode Overflow flag Count operation enabled
(d) External interrupt mode register 0 (INTM0)
7 INTM0 x
6 x
5 1
4 1
3 x
2 x
1 0
0 x Both rising and falling edges specified as INTP1 input valid edges
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Figure 11-44. Pulse Width Measurement Setting Procedure
Pulse width measurement
Set CRC2 CRC2 10H
Set INTM0 Set MK0L
; Specify both edges as INTP1 input valid edges, release interrupt masking
Initialize capture value buffer memory X0 0
Set TMC1 CE2 1 CMD2 0
; Set 1 in bit 7 of TMC1 Set normal mode (CMD2 = 0)
Enable interrupts
INTP1 interrupt
Figure 11-45. Interrupt Request Servicing that Calculates Pulse Width
INTP1 interrupt
Store capture value in memory Xn+1 CR22
Calculate pulse width Yn = Xn+1 - Xn
RETI
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11.9.4
Operation as PWM output
In PWM output, pulses with the duty ratio determined by the value set in the compare register (CR2n: n = 0, 1) are output (see Figure 11-46). This PWM output duty ratio can be varied in the range 1/256 to 255/256 in 1/256 units. The control register settings are shown in Figure 11-47, the setting procedure in Figure 11-48, and the procedure for varying the duty in Figure 11-49. Figure 11-46. Example of Timer/Event Counter 2 PWM Signal Output
FFH or FFFFH FFH or FFFFH FFH or FFFFH
TM2 count value 0H Timer start TO3 (when active-high)
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Figure 11-47. Control Register Settings for PWM Output Operation (a) Timer control register 1 (TMC1)
7 TMC1 1 6 0 5 0 4 0 3 x 2 x 1 0 0 0 Normal mode Overflow flag TM2 count enabled
(b) Prescaler mode register 1 (PRM1)
7 PRM1 6 5 4 3 x 2 x 1 x 0 x Count clock specification (x/fXX ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024)
PRS23 PRS22 PRS21 PRS20
(c) Capture/compare control register 2 (CRC2)
7 CRC2 1 6 0 5 0 4 1 3 0 2 0 1 0 0 0 TM2 clearing disabled TO2 & TO3 both PWM outputs
(d) Timer output control register (TOC)
7 TOC 1 6 0 5 x 4 x 3 x 2 x 1 x 0 x TO3 = active-high PMW signal output TO3 PMW output enabled
(e) Port 3 mode control register (PMC3)
7 PMC3 1 6 x 5 x 4 x 3 x 2 x 1 x 0 x P37 pin set as TO3 output
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Figure 11-48. PWM Output Setting Procedure
PWM output
Set CRC2 CRC2 90H
Set TOC
Set P34 pin to control mode PMC3.4 1
Set count clock in PRM1
Set initial value in CR20
Start count CE2 1
; Set bit 7 of TMC1
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Figure 11-49. Changing PWM Output Duty
Duty change preprocessing
Clear INTC21 interrupt request flag CIF21 0
; Clear bit 0 of IF0H
Enable INTC21 interrupts CMK21 0
; Clear bit 0 of MK0H
INTC21 interrupt
Duty change processing
Set duty value in CR21
Disable INTC21 interrupts CMK21 1
; Set bit 0 of MK0H
RETI
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11.9.5
Operation as PPG output
In PPG output, pulses with the cycle and duty ratio determined by the value set in the compare register (CR2n: n = 0, 1) are output (see Figure 11-50). The control register settings are shown in Figure 11-51, the setting procedure in Figure 11-52, and the procedure for varying the duty in Figure 11-53. Figure 11-50. Example of Timer/Event Counter 2 PPG Signal Output
CR21 CR21 CR21
TM2 count value 0H
CR20
CR20
CR20
Timer start TO2 (when active-high)
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Figure 11-51. Control Register Settings for PPG Output Operation (a) Timer control register 1 (TMC1)
7 TMC1 1 6 0 5 0 4 0 3 x 2 x 1 0 0 0 Normal mode Overflow flag TM2 count enabled
(b) Prescaler mode register 1 (PRM1)
7 PRM1 6 5 4 3 x 2 x 1 x 0 x Count clock specification (x/fXX ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024)
PRS23 PRS22 PRS21 PRS20
(c) Capture/compare control register 2 (CRC2)
7 CRC2 1
6 1
5 0
4 1
3 1
2 0
1 0
0 0 Cleared by match of TM2 & CR21 Clearing when TM2 is captured in CR22 disabled TO2 = PPG output
(d) Timer output control register (TOC)
7 TOC x 6 x 5 1 4 0 3 x 2 x 1 x 0 x TO2 = active-high PPG signal output TO2 PPG output enabled
(e) Port 3 mode control register (PMC3)
7 PMC3 x 6 1 5 x 4 x 3 x 2 x 1 x 0 x P36 pin set as TO2 output
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Figure 11-52. PPG Output Setting Procedure
PPG output
Set CRC2 CRC2 D8H
Set TOC
Set P34 pin to control mode PMC3.6 1
Set count clock in PRM1
Set cycle in CR21
Set duty in CR21
Start count CE2 1
; Set bit 7 of TMC1
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Figure 11-53. Changing PPG Output Duty
Duty change preprocessing
Clear INTC20 interrupt request flag CIF20 0
; Clear bit 3 of IF0H
Enable INTC20 interrupts CMK20 0
; Clear bit 3 of MK0H
INTC20 interrupt
Duty change processing
Set duty value in CR20
Disable INTC20 interrupts CMK20 1
; Set bit 3 of MK0H
RETI
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11.9.6
Operation as external event counter
An external event counter counts clock pulses (CI pin input pulses) input from off-chip. As shown in Figure 11-54, the value of timer counter 2 (TM2) is incremented in synchronization with a CI pin input valid edge (specified as rising edge only). Figure 11-54. External Event Counter Operation (single edge)
CI pin input
TM2
n
n+1
n+2
Remark The TM2 value is one less than the number of input clock pulses. The control register settings when TM2 operates as an external event counter are shown in Figure 11-55, and the setting procedure in Figure 11-56.
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Figure 11-55. Control Register Settings for External Event Counter Operation (a) Prescaler mode register 1 (PRM1)
7 PRM1 1
6 1
5 1
4 1
3 0
2 x
1 x
0 x
External clock input (C1) specified
(b) External interrupt mode register 0 (INTM0)
7 INTM0 0
6 1
5 x
4 x
3 x
2 x
1 x
0 x Rising edge specified as CI input valid edge
(c) Timer control register 1 (TMC1)
7 TMC1 1
6 0
5 0
4 0
3 x
2 x
1 0
0 0 Normal mode Overflow flag Count operation enabled
Figure 11-56. External Event Counter Operation Setting Procedure
Event counter
Specify CI pin input valid edge
Set PRM1 PRM1 0FxH
Start count CE2 1
; Set 1 in bit 7 of TMC1
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11.9.7
Operation as one-shot timer
After timer counter 2 (TM2) is started, it operates as a one-shot pulse that generates a single interrupt after the preset count time (see Figure 11-57). The second and subsequent one-shot timer operations can be started by clearing the OVF2 bit of timer control register 1 (TMC1). The control register settings are shown in Figure 11-58, the setting procedure in Figure 11-59, and the procedure for starting the one-shot timer from the second time onward in Figure 11-60. Figure 11-57. One-Shot Timer Operation
FFH or FFFFH
TM2 count value CR21 value
0H Count start CE2 1 INTC21 Clear OVF2 0
OVF2
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Figure 11-58. Control Register Settings for One-Shot Timer Operation (a) Timer control register 1 (TMC1)
7 TMC1 CE2
6 OVF2
5 1
4 0
3 x
2 x
1 x
0 x One-shot timer mode
(b) Prescaler mode register 1 (PRM1)
7 PRM1
6
5
4
3 0
2 x
1 x
0 x
PRS23 PRS22 PRS21 PRS20
Count clock specification (x/fXX ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024, or external clock)
(c) Capture/compare control register 2 (CRC2)
7 CRC2 0
6 0
5 0
4 1
3 0
2 0
1 0
0 0 TM2 clearing disabled
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Figure 11-59. One-Shot Timer Operation Setting Procedure
One-shot timer
Set one-shot timer mode CMD2 1
; Set 1 in bit 5 of TMC1
Set PRM1
Set count value in CR21 CR21 n
Set CRC2 CRC2 10H
Start count CE2 1
; Set 1 in bit 7 of TMC1
INTC21 interrupt
Figure 11-60. One-Shot Timer Operation Start Procedure from Second Time Onward
One-shot timer restart
Set count value in CR21 CR21 n
Restart count OVF2 0
; Clear bit 6 of TMC1
INTC21 interrupt
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11.10
Cautions
(1) While timer/event counter 2 is operating (while the CE2 bit of the timer control register 1 (TMC1) is set), malfunctioning may occur if the contents of the following registers are rewritten. This is because it is undefined which takes precedence, change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting. Therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following registers. * Prescaler mode register 1 (PRM1) * Capture/compare control register 2 (CRC2) * Timer output control register (TOC) * CMD2 bit of timer control register 1 (TMC1) (2) If the contents of the compare register (CR2n: n = 0, 1) match with those of TM2 when an instruction that stops timer counter 2 (TM2) operation is executed, the counting operation of TM2 stops, but an interrupt request is generated. In order not to generate the interrupt when stopping the operation of TM2, mask the interrupt in advance by using the interrupt mask register before stopping TM2. Example Program that may generate interrupt request ... CLR1 CE2 Interrupt request from OR MK0H, #03H timer/event counter 2 occurs between these instructions ... OR CLR1 CLR1 CLR1 timer/event counter 2 actually starts (refer to Figure 11-61). For example, when using timer/event counter 2 as an interval timer, the first interval time is delayed by up to 1 clock. The second and those that follow are at the specified interval. Figure 11-61. Operation when Counting is Started
Count clock TM2 0 0 CE2
Program that does not generate interrupt request ... MK0H, #03H CE2 CIF20 CIF21 ...
1 2 3 Timing to start actual counting
Disables interrupt from timer/event counter 2 Clears interrupt request flag for timer/ event counter 2
(3) Up to 1 count clock is required after an operation to start timer/event counter 2 (CE2 1) has been performed before
Count start command (CE2 1) by software
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(4) While an instruction that writes data to the compare register (CR2n: n = 0, 1) is executed, coincidence between CR2n, to which the data is to be written, and timer counter 2 (TM2) is not detected. For example, if the contents of CR2n do not change before and after the writing, the interrupt request is not generated even if the value of TM2 coincides with the value of CR2n, nor does the timer output (TOn + 2: n + 2 = 2, 3) change. Write data to CR2n when timer/event counter 2 is executing count operation in the manner that the contents of TM2 do not match the value of CR2n before and after writing (e.g., immediately after an interrupt request has been generated because TM2 and CR2n have matched). (5) Match between TM2 and compare register (CR2n: n = 0, 1) is detected only when TM2 is incremented. Therefore, the interrupt request is not generated and timer output (TOn + 2 : n + 2 = 2, 3) does not change even if the same value as TM2 is written to CR2n. (6) During PPG output, if the PPG cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of the compare register (CR2n: n = 0, 1) cannot be rewritten by interrupt processing that is performed on match between timer counter 2 (TM2) and compare register (CR2n). Use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). (7) The output level of the TOn (n = 2, 3) when the timer output is disabled (ENTOn = 0: n = 2, 3) is the inverse value of the value set to the ALVn (n = 2, 3) bits. Note, therefore, that an active level is output when the timer output is disabled with the PWM output function or PPG output function selected. (8) When using timer/event counter 2 as an external event counter, the status where no valid edge is input cannot be distinguished from the status where only one valid edge has been input, by using TM2 alone (refer to Figure 11-62), because the contents of TM2 are 0 in both the cases. To make a distinction, use the interrupt request flag of INTP2, as shown in Figure 11-63 (the INTP2 pin is multiplexed with the CI pin and both the functions can be used at the same time). Figure 11-62. Example of the Case where External Event Counter does Not Distinguish between One Valid Edge Input and No Valid Edge Input
CI
TM2
0
0
1
2
Cannot be distinguished Count start
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Figure 11-63. To Distinguish whether One or No Valid Edge has been Input with External Event Counter (a) Processing when count is started
Start count
Clear INTP2 interrupt request flag PIF2 0
; Clear PIF2 to 0
Start count CE2 1
; Set CE2 to 1
End
(b) Processing when count value is read
Count value read
Read TM2 contents A TM2
A = 0? NO A A+1
YES YES
; Check TM2 value. If 0, check interrupt request flag. PIF2 = 1? NO ; Check PIF2 contents. If 1, valid edge is input.
End
; Number of input valid edges is set to A register
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[MEMO]
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CHAPTER 12 TIMER 3
12.1 Function Timer 3 is a 16- or 8-bit timer. In addition to its function as an interval timer, it can be used as a counter for clocked serial interface (CSI) clock generation. The interval timer generates internal interrupts at preset intervals. The interval setting range is shown in Table 12-1. Table 12-1. Timer 3 Intervals
Minimum Interval 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s) Maximum Interval 216 x 4/fXX (20.8 ms) Resolution 4/fXX (0.32 s) 8/fXX (0.64 s) 16/fXX (1.27 s) 32/fXX (2.54 s) 64/fXX (5.09 s) 128/fXX (10.17 s) 256/fXX (20.35 s) 512/fXX (40.70 s) 1,024/fXX (81.40 s)
216 x 8/fXX (41.7 ms) 216 x 16/fXX (83.4 ms) 216 x 32/fXX (167 ms) 216 x 64/fXX (333 ms) 216 x 128/fXX (667 ms) 216 x 256/fXX (1.33 s) 216 x 512/fXX (2.67 s) 216 x 1,024/fXX (5.33 s)
( ): When fXX = 12.58 MHz
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12.2 Configuration Timer 3 consists of the following registers: * Timer counter (TM3/TM3W) x 1 * Compare register (CR30/CR30W) x 1 The block diagram of timer 3 is shown in Figure 12-1. Figure 12-1. Timer 3 Block Diagram
Internal bus
8/16
8/16
Compare register (CR30/CR30W) 16 Match 16 Clear
Selector
INTC30
Serial interface RESET
fXX
fXX/1,024 fXX/512 fXX/256 fXX/128 fXX/64 fXX/32 fXX/16 fXX/8 fXX/4
Prescaler
Timer counter 3 (TM3/TM3W)
Prescaler mode register 0 (PRM0)
PRS3 PRS2 PRS1 PRS0 8 Internal bus
CE3 BW3 1/8
Timer control register 0 (TMC0)
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(1) Timer counter 3 (TM3/TM3W) TM3/TM3W is a timer counter that count up using the count clock specified by the high-order 4 bits of prescaler mode register 0 (PRM0). The count operation is stopped or enabled by the timer control register 0 (TMC0). In addition, an 8-bit mode (TM3) or 16-bit mode (TM3W) can be selected. TM3 can be read only with an 8/16-bit manipulation instruction. When RESET is input, TM3 is cleared to 00H and the count is stopped. (2) Compare register (CR30/CR30W) CR30/CR30W is an 8/16-bit register that hold the value that determines the interval timer frequency. If the CR30/CR30W contents match the contents of TM3/TM3W, the contents of TM3/TM3W is cleared automatically and an interrupt request (INTC30) is generated. This compare register operates as CR30 in the 8-bit mode and CR30W in the 16-bit mode. CR30 can be read or written to with an 8/16-bit manipulation instruction. The contents of CR30 are undefined after RESET input. (3) Prescaler The prescaler generates the count clock from the internal system clock. The clock generated by the prescaler is selected by the selector, and is used as the count clock by TM3/TN3W to perform count operations. (4) Selector The selector selects a signal resulting from dividing the internal clock or the edge detected by the edge detection circuit as the count clock of TM3/TM3W.
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12.3 Timer 3 Control Registers (1) Timer control register 0 (TMC0) TMC0 controls the timer 3 timer counter 3 (TM3/TM3W) count operation by the high-order 4 bits (the low-order 4 bits control the count operation of timer/event counter 0 TM0). TMC0 can be read or written to with an 8-bit manipulation instruction. Figure 12-2. RESET input clears TMC0 to 00H. Figure 12-2. Timer Control Register 0 (TMC0) Format
7 TMC0 CE3 6 0 5 0 4 BW3 3 CE0 2 OVF0 1 0 0 0 Address 0FF5DH After reset 00H R/W R/W
The format of TMC0 is shown in
Countrols count operation of timer/event counter 0 TM0 (see Figure 9-2).
BW3 0 1
Timer 3 Bit Length Specification 8-bit operating mode 16-bit operating mode
CE3 0 1
TM3/TM3W Count Operation Control Count operation stopped with count cleared Count operation enabled
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(2) Prescaler mode register 0 (PRM0) PRM0 specifies the count clock to timer 3 timer counter 3 (TM3/TM3W) by the high-order 4 bits (the low-order 4 bits specify the count clock to timer/event counter 0 TM0). PRM0 can be read and written with an 8-bit manipulation instruction. Figure 12-3. RESET input sets PRM0 to 11H. Figure 12-3. Prescaler Mode Register 0 (PRM0) Format
7 6 5 4 3 2 1 0 Address 0FF5CH After reset 11H R/W R/W
The format of the PRM0 is shown in
PRM0 PRS3 PRS2 PRS1 PRS0 PRS03 PRS02 PRS01 PRS00
Specifies count clock to timer/event counter 0 TM0 (see Figure 9-3).
(fXX = 12.58 MHz) PRS3 PRS2 PRS1 PRS0 Timer 3 TM3/TM3W Count Clock Specification Count Clock [Hz] Specification 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 Setting prohibited fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 Setting prohibited Resolution [ s] - 0.32 0.64 1.27 2.54 5.09 10.17 20.35 40.70 81.40
Other than the above
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12.4 Timer Counter 3 (TM3) Operation 12.4.1 Basic operation Timer 3 can operate in an 8-bit or 16-bit mode. These operation modes are selected by bit 4 (BW3) of timer control register 0 (TMC0)Note. In the timer 3 count operation, the count-up is performed using the count clock specified by the high-order 4 bits of prescaler mode register 0 (PRM0). When RESET is input, timer counter 3 (TM3) is cleared to 0000H, and the count operation is stopped. Count operation enabling/disabling is controlled by bit 7 (CE3) of timer control register 0 (TMC0) (the high-order 4 bits of TMC0 control timer 3 operation). When the CE3 bit is set (to 1) by software, the contents of TM3 are immediately cleared on the first count clock, and then the count-up operation is performed. When the CE3 bit is cleared (to 0), TM3 becomes 0H immediately, and match signal generation is stopped. If the CE3 bit is set (to 1) again when it is already set (to 1), TM3 continues the count operation without being cleared. Note Unless there functional differences are found, the register names in the 8-bit mode are used. In the 16-bit mode, the register names TM3 and CR30 are TM3W and CR30W, respectively. Figure 12-4. Basic Operation in 8-Bit Operation Mode (BW3 = 0) (a) Count started count stopped count started
Count clock
TM3
0H
0H
1H
2H
0FH 10H 11H
0H
0H
1H
CE3
Count started CE3 1
Count stopped CE3 0
Count started CE3 1
(b) When "1" is written to the CE3 bit again after the count starts
Count clock
TM3
0H
0H
1H
2H
3H
4H
5H
6H
CE3
Count started CE3 1
Rewrite CE3 1
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Figure 12-5. Basic Operation in 16-Bit Operation Mode (BW3 = 1) (a) Count started count stopped count started
Count clock
TM3W
0H
0H
1H
2H
FFH 100H 101H
0H
0H
1H
CE3
Count started CE3 1
Count stopped CE3 0
Count started CE3 1
(b) When "1" is written to the CE3 bit again after the count starts
Count clock
TM3W
0H
0H
1H
2H
3H
4H
5H
6H
CE3
Count started CE3 1
Rewrite CE3 1
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12.4.2 Clear operation (1) Clear operation by match with compare register (CR30) Timer counter 3 (TM3) is cleared automatically after a match with the compare register (CR30). When a clearance source arises, TM3 is cleared to 0H on the next count clock. Therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. Figure 12-6. TM3 Clearance by Match with Compare Register (CR30)
Count clock
TM3
n-1
n
0
1
Compare register (CR30)
n
TM3 and CR30 match
Cleared here
(2) Clear operation by CE3 bit of timer control register 0 (TMC0) TM3 is also cleared when the CE3 bit of TMC0 is cleared (to 0) by software. The clear operation is performed following clearance (to 0) of the CE3 bit in the same way.
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Figure 12-7. Clear Operation when CE3 Bit is Cleared (0) (a) Basic operation
Count clock
TM3
n-1
n
0
CE3
(b) Restart before count clock is input after clearance
Count clock
TM3
n-1
n
0
0
1
2
CE3
If the CE3 bit is set (to 1) before this count clock, the count starts from 0 on this count clock
(c) Restart when count clock is input after clearance
Count clock
TM3
n-1
n
0
0
0
1
CE3
If the CE3 bit is set (to 1) from this count clock onward, the count starts from 0 on the count clock after the CE3 bit is set (to 1).
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12.5 Compare Register Operation Timer 3 performs compare operations in which the value set in the compare register (CR30) is compared with the timer counter 3 (TM3) count value. If the count value of TM3 matches the preset CR30 value as the result of the count operation, an interrupt request (INTC30) is generated. After a match, the TM3 contents are cleared automatically, and therefore TM3 functions as an interval timer that repeatedly counts up to the value set in the CR30. Figure 12-8. Compare Operation
CR30 CR30
TM3 count value
0H Count start CE 1 Clear (match) Clear (match)
INTC30 interrupt request
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12.6 Example of Use Operation as interval timer: TM3 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see Figure 12-9). TM3 can also be used for baud rate generation. This interval timer can count up to a maximum of 20.85 ms at the minimum resolution of 0.32 s, and up to 5.33 s at the maximum resolution of 81.40 s (internal system clock fXX = 12.58 MHz). The control register settings are shown in Figure 12-10, and the setting procedure in Figure 12-11. Figure 12-9. Interval Timer Operation Timing
n n
TM3 count value
0H Count start Compare register (CR30) Clear n Clear
INTC30 interrupt request
Interrupt acknowledgment Interval Interval
Interrupt acknowledgment
Remark Interval = (n+1) x x/fXX 0 n FFH, x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024
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Figure 12-10. Control Register Settings for Interval Timer Operation Prescaler mode register 0 (PRM0)
7 PRM0 PRS3 6 PRS2 5 PRS1 4 PRS0 3 0 2 0 1 0 0 0
Count clock specification (x/fXX ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024)
Figure 12-11. Interval Timer Operation Setting Procedure
Interval timer
Set PRM0
Set count value in CR30 CR30 n
Start count CE 1
; Set 1 in bit 7 of TMC0
INTC30 interrupt
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12.7 Cautions (1) There is a possibility of malfunction if the next register contents are rewritten while the timer 3 is operating (when the CE3 bit of the timer control register 0 (TMC0) is set). The malfunction occurs as there is no defined order of priority in the event of contention between the timings at which the hardware function changes due to a register rewrite and the status changes in the function prior to the rewrite. When the contents of the following register are rewritten, counter operations must be stopped first to ensure stability. * Prescaler mode register 0 (PRM0) (2) If the compare register (CR30) and timer counter 3 (TM3) contents match when an instruction that stops TM3 operation is executed, the TM3 count operation stops, but an interrupt request is generated. If you do not want an interrupt to be generated when TM3 operation is stopped, interrupts should be masked by means of interrupt the mask register before stopping the TM3. Example Program in which an interrupt request may be generated ... CLR1 CE3 Interrupt request generated by timer 3 here SET1 CMK30 ... CLR1 CIF30 ... (3) There is a delay of up to one count clock between the operation that starts a timer 3 (CE3 1) and the actual start of the timer 3 (see Figure 12-12). For example, if a timer 3 is used as an interval timer, the first interval will be extended by up to one clock. The second and subsequent intervals will be as specified. Figure 12-12. Operation when Counting is Started
Count clock TM3 0 0 1 CE3
Program in which an interrupt request is not generated ... SET1 CMK30 Disables interrupts from timer 3 CLR1 CE3 Clears timer 3 interrupt request flag
2 3 Timing at which count actually starts
Software count start command (CE3 1)
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(4) While an instruction that writes data to the compare register (CR30) is executed, match between CR30, to which the data is to be written, and timer counter 3 (TM3) is not detected. Write data to CR30 when timer 3 is executing count operation so that the contents of TM3 do not match the value of CR30 before and after writing (e.g., immediately after an interrupt request has been generated because TM3 and CR30 have matched). (5) Match between TM3 and compare register (CR30) is detected only when TM3 is incremented. Therefore, the interrupt request is not generated even if the same value as TM3 is written to CR30.
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CHAPTER 13 WATCHDOG TIMER
The watchdog timer is a timer that detects inadvertent program loops. Watchdog timer interrupts are used to detect system or program errors. For this purpose, instructions that clear the watchdog timer (start the count) within a given period are inserted at various places in a program. If an instruction that clears the watchdog timer is not executed within the set time and the watchdog timer overflows, a watchdog timer interrupt (INTWDT) is generated and a program error is reported. 13.1 Configuration The watchdog timer block diagram is shown in Figure 13-1. Figure 13-1. Watchdog Timer Block Diagram
fCLK
Watchdog timer fCLK/221 fCLK/220 Selector fCLK/219 fCLK/217 INTWDT
Clear signal
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13.2 Watchdog Timer Mode Register (WDM) WDM is an 8-bit register that controls the watchdog timer operation. To prevent erroneous clearing of the watchdog timer by an inadvertent program loop, writing can only be performed by a dedicated instruction. This dedicated instruction, MOV WDM, #byte, has a special code configuration (4 bytes), and a write is not performed unless the 3rd and 4th bytes of the operation code are mutual complements of 1. If the 3rd and 4th bytes of the operation code are not mutual complements of 1, a write is not performed and an operand error interrupt is generated. In this case, the return address saved in the stack area is the address of the instruction that was the source of the error, and thus the address that was the source of the error can be identified from the return address saved in the stack area. If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result. As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC assembler, RA78K4, only the correct dedicated instruction is generated when MOV WDM, #byte is written), system initialization should be performed by the program. Other write instructions (MOV WDM, A, AND WDM, #byte, SET1 WDM.7, etc.) are ignored and do not perform any operation. That is, a write is not performed to the WDM, and an interrupt such as an operand error interrupt is not generated. After a system reset (RESET input), once the watchdog timer has been started (by setting (to 1) the RUN bit), the WDM contents cannot be changed. The watchdog timer can only be stopped by a reset, but can be cleared at any time with a dedicated instruction. WDM can be read at any time by a data transfer instruction. RESET input clears WDM to 00H. The WDM format is shown in Figure 13-2.
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Figure 13-2. Watchdog Timer Mode Register (WDM) Format
7 WDM RUN 6 0 5 0 4 PRC 3 0 2 WDI2 1 WDI1 0 0 Address FFC2H After reset 00H R/W R/W
WDI2 0 0 1 1
WDI1 0 1 0 1
Overflow Time [ms] fCLK = 12.58 MHz 217/fCLK (10.4) 219/fCLK (41.7) 220/fCLK (83.4) 221/fCLK (166.7)
Remark fCLK: Internal System Clock Frequency
PRC 0
Watchdog Timer Interrupt Request Priority Specification Watchdog timer interrupt request < NMI pin input interrupt request Watchdog timer interrupt request > NMI pin input interrupt request Watchdog Timer Operation Specification Watchdog timer stopped Clear watchdog timer and start count
1
RUN 0 1
Cautions 1. The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV WDM, #byte). 2. The same value should be written each time in writes to the WDM to set (to 1) the RUN bit. The contents written at the first time cannot be changed even if a different value is written. 3. Once the RUN bit has been set (to 1), it cannot be reset (to 0) by software.
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13.3 Operation 13.3.1 Count operation The watchdog timer is cleared, and the count started, by setting (to 1) the RUN bit of the watchdog timer mode register (WDM). When overflow time specified by the WDM2 and WDM1 bits of WDM has elapsed after the RUN bit has been set (to 1), a non-maskable interrupt (INTWDT) is generated. If the RUN bit is set (to 1) again before the overflow time elapses, the watchdog timer is cleared and the count operation is started again. 13.3.2 Interrupt priorities The watchdog timer interrupt (INTWDT) is a non-maskable interrupt. Other non-maskable interrupts are interrupts from the NMI pin (NMI). The order of acknowledgment when an INTWDT interrupt and NMI interrupt are generated simultaneously can be specified by the setting of bit 4 of the watchdog timer mode register (WDM). Even if INTWDT is generated while the NMI processing program is executed when NMI acknowledgement is specified to take precedence, INTWDT is not acknowledged until completion of execution of the NMI processing program.
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13.4 Cautions 13.4.1 General cautions on use of watchdog timer (1) The watchdog timer is one means of detecting inadvertent program loops, but it cannot detect all inadvertent program loops. Therefore, in equipment that requires a high level of reliability, you should not rely on the on-chip watchdog timer alone, but should use external circuitry for early detection of inadvertent program loops, to enable processing to be performed that will restore the normal state or establish a stable state and then stop the operation. (2) The watchdog timer cannot detect inadvertent program loops in the following cases. <1> If watchdog timer clearance is performed in the timer interrupt service program <2> If cases where an interrupt request or macro service is held pending (see 23.9) occur consecutively <3> If the watchdog timer is cleared periodically when inadvertent program looping is due to an error in the program logic (if each module of the program functions normally but the overall program does not) <4> If the watchdog timer is periodically cleared by a group of instructions executed when an inadvertent program loop occurs <5> If the STOP mode or IDLE mode is entered as the result of an inadvertent program loop <6> If watchdog timer inadvertent program loop also occurs in the event of CPU inadvertent program loop due to external noise In cases <1>, <2>, and <3> the program can be amended to allow detection to be performed. In case <4>, the watchdog timer can only be cleared by a 4-byte dedicated instruction. Similarly, in case <5>, the STOP mode or IDLE mode cannot be set unless a 4-byte dedicated instruction is used. For state <2> to be entered as the result of an inadvertent program loop, 3 or more consecutive bytes of data must comprise a specific pattern (e.g. BT PSWL.bit, $$, etc.). Therefore, the establishment of state <2> as the result of <4>, <5> or an inadvertent program loop is likely to be extremely rare.
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13.4.2 Cautions on PD784938 Subseries watchdog timer (1) The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV WDM, #byte). (2) The same value should be written each time in writes to the watchdog timer mode register (WDM) to set (to 1) the RUN bit. The contents written at the first time cannot be changed even if a different value is written. (3) Once the RUN bit has been set (to 1), it cannot be reset (to 0) by software.
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CHAPTER 14 WATCH TIMER
Two types of count clocks can be input to the watch timer: main clock (12.58 MHz (MAX.)) and watch clock (32.768 kHz). These count clocks can be selected by the control register. The watch clock is input only to the watch timer, and not to the CPU and other peripheral circuits. Therefore, the operating speed of the CPU cannot be slowed down by using the watch clock. The watch timer generates an interrupt signal with a 0.5-second interval (INTW) by dividing the count clock. At the same time, it also sets an interrupt request flag (WIF: bit 7 of interrupt control register (WIC)). The INTW generation interval can be changed to about 1 ms by changing the mode (fast forward mode: 512 times faster than the normal mode). Also, the INTW generation interval can be set to 15.6 ms. When the main clock is selected as the count clock, the watch timer stops at standby in STOP mode. However, it continues operating in the IDLE and HALT modes. When the watch clock is selected as the count clock, the watch timer can continue operating in any standby mode (it means any of STOP, IDLE, and HALT modes). The operation of the watch clock oscillator is controlled by the watch timer mode register (WM). Figure 14-1 shows the format of WM. Figure 14-1. Watch Timer Mode Register (WM) Format
7 WM WM7 6 WM6 5 0 4 WM4 3 WM3 2 WM2 1 0 0 0 Address 0FF6FH After reset 00H R/W R/W
WM4 0 1
WM2 0 0
Watch Timer Operation Mode Normal watch mode (generates INTW at 0.5 s intervals) Medium-fast forward mode (32 times faster than normal mode, generates INTW at 15.6 ms intervals) Fast forward mode (512 times faster than normal mode, generates INTW at 0.98 ms intervals) Watch Timer Operation Control
0 1 WM3 0 1
1 1
Clears division counter and stops counting Starts operation of division counter
WM6 Watch Timer Operation Clock Specification 0 1 WM7 0 1 Main clock Watch clock Watch Clock Oscillator Operation Control Stops watch clock oscillator Operation watch clock oscillator
Caution The time from when the watch timer is started up until the first INTW occurs is less than 0.5 seconds. This time becomes 0.5 seconds from the second and subsequent INTW occurrences.
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The watch timer of the PD784938 does not have a buzzer output function. Table 14-1. Relation between Count Clock and Watch Timer Operation
Count Clock Selection Normal Operation Mode HALT mode Main clock Watch clock Operable Operable Operable Operable Type of Standby Mode STOP mode Stopped Operable IDLE mode OperableNote Operable
Note When bit 3 (WM3) of the watch timer mode register (WM) is set to "1" and bit 6 (WM6) of the same register is set to "0", main clock operation in the IDLE mode is enabled. The watch timer consists of a divider circuit that divides the count clock by three, and a counter that divides the output signal of the divider circuit by 214. As the count clock, select the signal obtained by dividing the internal system clock by 128, or the signal from the watch clock oscillator. Figure 14-2. Block Diagram of Watch Timer
WM.3 reset
Main clock fXX/128
12345
1/3 divider
6789
10 11 12 13
14
Counter
0S E L 0 Watch clock oscillator SEL 1
Counter
Counter
0 WM.4 1 WM.2 SEL
1 SEL 0 INTW
ON/OFF WM.7 WM.6 STBC.7 (Set by instruction when main clock is 12.58 MHz)
Caution The interval until the first INTW is generated is not 0.5 second after the operation has been enabled.
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CHAPTER 15 PWM OUTPUT UNIT
The PD784938 incorporates two 12-bit resolution PWM (pulse width modulation) output circuit channels. The active level of the PWM output pulses can be selected as high or low. The PWM output ports consist of dedicated pins. 15.1 PWM Output Unit Configuration The PWM output unit configuration is shown in Figure 15-1. Figure 15-1. PWM Output Unit Configuration
Internal bus 8 PWMn 15 16 8 7 4 3 0
PWPR
8
PWMC
8 Reload
4 Reload Reload control
fCLK
Prescaler
fPWMC
8-bit down counter
PWM pulse generator 4-bit counter
Output control circuit
PWMn
1/256
Remark n = 0, 1
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(1) 8-bit down counter Generates the basic PWM signal timing. (2) PWM pulse generator (including 4-bit counter) Controls addition of extra pulses and generates the PWM pulses to be output. (3) Reload control Controls 8-bit down counter and 4-bit count modulo value reloading. (4) Output control circuit Controls the active level of the PWM signal. (5) Prescaler Scales fCLK, and generates the reference clock.
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15.2 PWM Output Unit Control Registers 15.2.1 PWM control register (PWMC) PWMC is an 8-bit register that controls the operating status of the PWM output pins (PWMn: n = 0, 1). PWMC can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. Its format is shown in Figure 15-2. When RESET is input, PWMC is set to 05H, the PWMn pin is disabled from outputting signals. Figure 15-2. PWM Control Register (PWMC) Format
7 PWMC SYN1 6 0 5 SYN0 4 0 3 EN1 2 ALV1 1 EN0 0 ALV0 Address 0FF70H After reset 05H R/W R/W
(n = 0, 1) ALVn 0 1 PWMn Pin PWM Active Level Specification Active-low Active-high
ENn 0 1
PWMn Pin PWM Output Control Output disabled PWM output enabled
SYNn 0 1
PWM Pulse Width Rewrite Cycle Specification Rewritten every 16 PWM cycles (212/fPWMC)
8 Rewritten every PWM cycle (2 /fPWMC)
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15.2.2 PWM prescaler register (PWPR) PWPR is an 8-bit register that selects the PWM output circuit operating clock (fPWMC). PWPR can be read or written to with an 8-bit manipulation instruction. Its format is shown in Figure 15-3. When RESET is input, PWPR is cleared to 00H, and fCLK is selected as fPWMC for both channels. Figure 15-3. PWM Prescaler Register (PWPR) Format
7 PWPR 0 6 5 4 3 0 2 1 0 Address 0FF71H After reset 00H R/W R/W (n = 0, 1) PWPn2 PWPn1 PWPn0 PWMn Operating PWMn Repetition Frequency Clock (fPWMC) (fCLK = 12.58 MHz) 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 fCLK/2 fCLK/3 fCLK/4 fCLK/512 (24.58 kHz) fCLK/768 (16.38 kHz) fCLK/1,028 (12.28 kHz) fCLK fCLK/256 (49.14 kHz)
PWP12 PWP11 PWP10
PWP02 PWP01 PWP00
Other than the above Setting prohibited
15.2.3 PWM modulo registers (PWM0, PWM1) The PWM modulo register (PWMn: n = 0, 1) is a 16-bit register that determines the PWM pulse width. Reads/writes by a 16-bit manipulation instruction are possible for data setting. The contents of bits 4 to 15 of the PWMn determines the 12-bit PWM pulse width (12-bit resolution). Bits 3 to 0 have no meaning, and PWM output is not affected whether 1 or 0 is written to these bits. When RESET is input, the PWMn content are undefined, and therefore data must be set by the program before PWM output is enabled. Caution A value between 0000H and 00FFH should not be set in the PWM modulo registers (PWMn: n = 0, 1). A value between 0100H and FFFFH should be set in the PWMn registers. The PWM signal duty values that can be output are 17/4,096 to 4,096/4,096.
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15.3 PWM Output Unit Operation 15.3.1 Basic PWM output operation The PWM pulse output duty is determined by the value set in bits 4 to 15 of the PWM modulo register (PWMn: n = 0, 1) as shown below. PWM pulse output duty = (Value of PWMn bits 4 to 15)Note + 1 4,096 Note 16 (Value of PWMn bits 4 to 15) 4095 The PWM pulse output repetition frequency is the frequency obtained by division-by-256 of the PWM clock fCLK/1 to fCLK/4 set by the PWM prescaler register (PWPR) (=fPWMC/256), and the minimum pulse width is 1/fPWMC. In PWM pulse output, 12-bit resolution is achieved by repeating output of a fPWMC/256 repetition frequency 8-bit resolution PWM signal 16 times. The addition of extra pulses (1/fPWMC) to the 8-bit resolution PWM pulses determined by bits 8 to 15 of the PWMn every cycle is controlled in accordance with the value of bits 4 to 7 of the PWMn to implement a PWM pulse signal once every 16 cycles. Figure 15-4. Basic PWM Output Operation
PWM signal
Note
One 12-bit PWM signal cycle
Note 8-bit resolution per PWM pulse cycle
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15.3.2 PWM pulse output enabling/disabling When PWM pulses are output, the ENn (n = 0, 1) bits of the PMC register are set (to 1) after data is set in the PWM prescaler register (PWPR) and PWM modulo register (PWMn: n = 0, 1). As a result, PWM pulses with the active level specified by ALVn (n = 0, 1) bit of the PWM control register (PWMC) are output from the PWM output pin. When the ENn bits of the PWMC are cleared (to 0), the PWM output unit immediately stops the PWM output operation. 15.3.3 PWM pulse active level specification The ALVn (n = 0, 1) bit of the PWM control register (PWMC) specify the active level of PWM pulses output from the PWM output pins. When ALVn bit is set (to 1), active-high level pulses are output, and when cleared (to 0), active-low level pulses are output. When ALVn bit is rewritten, the PWM active level changes immediately. PWM output active level setting and pin states are shown in Figure 15-5. Figure 15-5 shows the case where ALVn bit is switched when the ENn (n = 0, 1) bit of the PWMC is set (to 1) and PWM output is enabled. The pin state does not change if ALVn is rewritten when ENn bit is in the cleared (to 0) state. Figure 15-5. PWM Output Active Level Setting
ALVn
(Active-high)
(Active-low)
PWMn
(ALVn bit rewrite)
Remark ENn = 1 (n = 0, 1)
400
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15.3.4 PWM pulse width rewrite cycle specification The start of PWM output and pulse width changes are performed in synchronization either with every 16 PWM pulse cycles (212/fPWMC) or with every PWM pulse cycle (28/fPWMC). This PWM pulse width rewrite cycle specification is performed by means of the SYNn bits of the PWM control register (PWMC). When the SYNn bit is cleared (to 0), a pulse width change is performed every 16 PWM pulse cycles (212/fPWMC). It therefore takes a maximum of 212 clocks (326 s when fPWMC = 12.58 MHz) until a pulse of a width corresponding to the data written in the PWM modulo register (PWMn: n = 0, 1) is output. An example of the PWM output timing at this time is shown in Figure 15-6. When the SYNn bit is set (to 1), on the other hand, a pulse width change is performed every PWM pulse cycle (28/fPWMC). In this case, it takes a maximum of 28 clocks (20.4 s when fPWMC = 12.58 MHz) until a pulse of a width corresponding to the data written in the PWMn is output. However, caution is required since, if the PWM pulse rewrite cycle is specified as every 28/fPWMC, (if the SYNn bit is set (to 1)), the obtained PWM pulse precision is between 8 bits and 12 bits, and is lower than when the PWM pulse rewrite cycle is specified as 212/fPWMC. An example of the PWM output timing when the rewrite timing is 28/fPWMC is shown in Figure 15-7. Figure 15-6. PWM Output Timing Example 1 (PWM pulse width rewrite cycle = 212/fPWMC)
16 PWM pulse cycles 16 PWM pulse cycles
PWM output pin
PWMn contents PWM output enabled PWM pulse width switching timing
n
m
PWMn rewrite
PWM pulse width switching timing
PWM pulse width switching timing
Cautions 1. Pulse width rewriting is performed every PWM pulse cycle. 2. The PWM pulse precision is 12 bits.
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Figure 15-7. PWM Output Timing Example 2 (PWM pulse width rewrite cycle = 28/fPWMC)
1 PWM pulse cycle
PWM output pin
PWMn contents
n
I
m
n
PWM output enabled
PWMn rewrite
PWMn rewrite
PWMn rewrite
PWM pulse width switching timing
Cautions 1. Pulse width rewriting is performed every PWM pulse cycle. 2. The PWM pulse precision is between 8 and 12 bits. Remark l, m, and n mean the PWMn contents. 15.4 Caution A value between 0000H and 00FFH should not be set in the PWM modulo registers (PWMn: n = 0, 1). A value between 0100H and FFFFH should be set in the PWMn. The PWM signal duty values that can be output are 17/4,096 to 4,096/ 4,096.
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The PD784938 incorporates an analog/digital (A/D) converter with 8 multiplexed analog inputs (ANI0 to ANI7). The successive approximation conversion method is used, and the conversion result is held in the 8-bit A/D conversion result register (ADCR). This allows fast, high-precision conversion to be performed. There are two modes for starting A/D conversion, as follows: * Hardware start: Conversion started by trigger input (INTP5). * Software start: Conversion started in accordance with A/D converter mode register (ADM) bit setting.
After start-up, there are two operation modes, as follows: * Scan mode: Multiple analog inputs are selected in order, and conversion data is obtained from all pins.
* Select mode: One pin is used as the analog input, and conversion values are obtained in succession. Stoppage of all the above modes and conversion operations is specified by the ADM register. When the conversion result is transferred to the ADCR, an INTAD interrupt request is generated. This allows conversion values to be transferred to memory in succession by means of macro service. Cautions 1. Apply a voltage same as the supply voltage (AVDD) to the reference voltage input pin (AVREF1) of this product. 2. When port 7 is used for both output port and A/D input, do not write to output port during A/D conversion operations. 16.1 Configuration The A/D converter configuration is shown in Figure 16-1.
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ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Input selector
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Figure 16-1. A/D Converter Block Diagram
Series resistor string Sample & hold circuit
Connection control
AVDD A/D current cut select register (IEAD) AVREF1
R/2 Voltage comparator R Tap selector Successive approximation register (SAR)
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INTP5
Edge detection circuit
Conversion trigger Control circuit INTAD R/2 AVSS
A/D CONVERTER
Trigger enable
8
A/D converter mode register (ADM)
RESET
A/D conversion result register (ADCR)
8
8
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Cautions 1. A capacitor should be connected between the analog input pins (ANI0 to ANI7) and AVSS, and between the reference voltage input pin (AVREF1) and AVSS to prevent malfunction due to noise. Be sure to connect the capacitor as closely to ANI0 through ANI7 and AVREF1 as possible. Figure 16-2. Example of Capacitor Connection on A/D Converter Pins
PD784938
Analog input 100 to 500 pF Reference voltage input AVREF1 ANI0 to ANI7
AVSS
2. A voltage outside the range AVSS to AVREF1 should not be applied to pins used as A/D converter input pins. See 16.6 Cautions for details. (1) Input circuit The input circuit selects the analog input in accordance with the specification of the A/D converter mode register (ADM), and sends the analog input to the sample & hold circuit according to the operation mode, (2) Sample & hold circuit The sample & hold circuit samples the analog inputs arriving sequentially one by one and holds the analog input in the process of A/D conversion. (3) Voltage comparator The voltage comparator determines the voltage difference between the analog input and the series resistor string value tap. (4) Series resistor string The series resistor string is used to generate voltages that match the analog inputs. The series resistor string is connected between the A/D converter reference voltage pin (AVREF1) and the A/D converter GND pin (AVSS). To provide 256 equal voltage steps between the two pins, it is made up of 255 equal resistors and two resistors with half that resistance value. The series resistor string voltage tap is selected by a tap selector controlled by the SAR successive approximation register.
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(5) SAR: Successive Approximation Register SAR is an 8-bit register in which the data for which the series resistor string voltage tap value matches the analog input voltage value is set bit by bit starting from the most significant bit (MSB). When data has been set up to the least significant bit (LSB) of the SAR (when A/D conversion is completed), the SAR contents (conversion result) are stored in the A/D conversion result register (ADCR). (6) ADCR: A/D Conversion Result Register ADCR is an 8-bit register that holds the A/D conversion result. The conversion result is loaded into this register from the successive approximation register (SAR) each time A/D conversion finishes. The contents of this register approximation are undefined when RESET is input. (7) Edge detection circuit The edge detection circuit detects a valid edge from the interrupt request input pin (INTP5) input, and generates an external interrupt request signal (INTP5) and A/D conversion operation external trigger. The INTP5 pin input valid edge is specified by external interrupt mode register 1 (INTM1) (see Figure 22-2). External trigger enabling/disabling is set by means of the A/D converter mode register (ADM) (see 16.2 A/D Converter Mode Register (ADM)).
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16.2 A/D Converter Mode Register (ADM) ADM is an 8-bit register that controls A/D converter operations. ADM register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. Its format is shown in Figure 16-3. Bit 0 (MS) controls the operation mode. Bits 1, 2, and 3 (ANI0, 1, 2) select the analog inputs for A/D conversion. Bit 5 (SCMD) controls the A/D conversion operation in scan mode. Bit 6 (TRG) enables external synchronization of the A/D conversion operation. If the TRG bit is set (to 1) when the CS bit is set (to 1), the conversion operation is initialized with each input of a valid edge as an external trigger to the INTP5 pin. When the TRG bit is cleared (to 0), the conversion operation is performed without regard to the INTP5 pin. Bit 7 (CS) controls the A/D conversion operation. When the CS bit is set (to 1) the conversion operation is started, and when cleared (to 0), all conversion operations are stopped even if conversion is in progress. In this case, the A/D conversion result register (ADCR) is not updated and an INTAD interrupt request is not generated. Also, the power supply to the voltage comparator is stopped, and the A/D converter consumption current is reduced. RESET input clears ADM to 00H. Caution When the STOP mode or IDLE mode is used, the consumption current should be reduced by clearing (to 0) the CS bit before entering the STOP or IDLE mode. If the CS bit remains set (to 1), the conversion operation will be stopped by entering the STOP or IDLE mode, but the power supply to the voltage comparator will not be stopped, and therefore the A/D converter consumption current will not be reduced.
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Figure 16-3. A/D Converter Mode Register (ADM) Format
7 ADM CS 6 TRG 5 SCMD 4 FR 3 2 1 0 MS Address 0FF68H After reset 00H R/W R/W
ANIS2 ANIS1 ANIS0
ANIS2 ANIS1 ANIS0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FR 0 1 SCMD 0 1 0 1 TRG 0 1 CS 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
MS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A/D Conversion Operating Mode Setting Scan mode (0/1) ANI0 input scanned Input ANI0 & ANI1 scanned Input ANI0 to ANI2 scanned Input ANI0 to ANI3 scanned Input ANI0 to ANI4 scanned Input ANI0 to ANI5 scanned Input ANI0 to ANI6 scanned Input ANI0 to ANI7 scanned Select ANI0 input selected mode ANI1 input selected ANI2 input selected ANI3 input selected ANI4 input selected ANI5 input selected ANI6 input selected ANI7 input selected
Conversion Speed Control (fCLK = 12.58 MHz) 180/fCLK (19.1 s) 120/fCLK (9.6 s) MS 0 0 1 1 Low-speed conversion High-speed conversion Scan Mode Selection Scan mode 0 (no delay control) Scan mode 1 (delay control) Select mode Setting prohibited External Trigger Control External trigger disabled External trigger enabled A/D Conversion Operation Control Stop A/D conversion operation Start A/D conversion operation
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Caution Once the A/D converter starts operating, conversion operations are performed repeatedly until the CS bit of the A/D converter mode register (ADM) is cleared (to 0). Therefore, a superfluous interrupt may be generated if ADM setting is performed after interrupt-related registers, etc., when A/D converter mode conversion, etc., is performed. The result of this superfluous interrupt is that the conversion result storage address appears to have been shifted when the scan mode is used. Also, when the select mode is used, the first conversion result appears to have been an abnormal value, such as the conversion result for the other channel. It is therefore recommended that A/D converter mode conversion be carried out using the following procedure. <1> Write to the ADM (CS bit must be set (to 1)) <2> Interrupt request flag (ADIF) clearance (to 0) <3> Interrupt mask flag or interrupt service mode flag setting Operations <1> to <3> should not be divided by an interrupt or macro service. When scan mode 0 (no delay control) is used, in particular, you should ensure that the time between <1> and <2> is less than the time taken by one A/D conversion operation. Alternatively, the following procedure is recommended. <1> Stop the A/D conversion operation by clearing (to 0) the CS bit of the ADM. <2> Interrupt request flag (ADIF) clearance (to 0). <3> Interrupt mask flag or interrupt service mode flag setting <4> Write to the ADM
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16.3 A/D Current Cut Select Register (IEAD) IEAD is a register that selects whether AVDD and AVREF1 are connected. . In a system where AVDD =. AVREF1 and a high accuracy is not required, open the AVREF1 pin. In the normal mode, connect AVDD and AVREF1. In the standby mode, the connection between these pins is disconnected to lower the power consumption. IEAD is set with an 8-bit or 1-bit manipulation instruction. RESET input clears IEAD to 00H. Figure 16-4. A/D Current Cut Select Register (IEAD) Format
Symbol IEAD 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Address After reset R/W 00H R/W
IEAD0 0FF6CH
IEAD0 Controls Connection between AVDD and AVREF1 0 1 Disconnects AVDD and AVREF1 Connects AVDD and AVREF1
Figure 16-5. A/D Current Cut Select Register Function
AVDD
Connection control
AVDD
Power consumption can be lowered by controlling connection between AVDD and AVREF1 with IEAD0.
AVREF1
AVREF1 (open)
AVSS
AVSS
AVDD AVREF1 or when high accuracy is required
AVDD = AVREF1 and when high accuracy is not required
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16.4 Operation 16.4.1 Basic A/D converter operation (1) A/D conversion operation procedure A/D conversion is performed by means of the following procedure: (a) Analog pin selection and operation mode specification are set with the A/D converter mode register (ADM). (b) Bit 7 (CS) of the ADM is set (to 1), and A/D conversion is started. (c) When conversion starts, the MSB (bit 7) of the successive approximation register (SAR) is set (to 1) automatically. (d) When bit 7 of the SAR is set (to 1), the tap selector sets the series resistor string voltage tap to
225 . AVREF1 (= 1/2 AVREF1). . 512
(e) The voltage difference between the series resistor string voltage tap and the analog input is determined by the voltage comparator. If the analog input is greater than (1/2) AVREF1, the MSB of the SAR remains set (to 1), and if it is less than (1/2) AVREF1, the MSB is cleared (to 0). (f) Next, bit 6 of the SAR is set (to 1) automatically, and the next comparison is performed. Here, the series resistor string voltage tap is selected according to the value of bit 7 for which the result has already been set, as shown below.
3 383 AVREF1 .. = AVREF1 4 512 1 127 AVREF1 .. = AVREF1 4 512
* Bit 7 = 1 ........ * Bit 7 = 0 ........
This voltage tap is compared with the analog input voltage, and bit 6 of the SAR is manipulated as follows according to the result: * Analog input voltage voltage tap: Bit 6 = 1 * Analog input voltage < voltage tap: Bit 6 = 0 (g) The same kind of comparison is continued up to the LSB (bit 0) of the SAR (binary search method).
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(h) When comparison of the 8 bits is completed, a valid digital result is left in the SAR, and that value is transferred to the A/D conversion result register (ADCR) and latched. An A/D conversion operation end interrupt request (INTAD) can be generated at the same time. Figure 16-6. Basic A/D Converter Operation
Conversion time Sampling time A/D converter operation
Sampling
A/D conversion
SAR
Undefined
80H
C0H or 40H
Conversion result Conversion result
ADCR
INTAD
A/D conversion operations are performed successively until the CS bit is cleared (to 0) by software. If a write operation is performed on the ADM during an A/D conversion operation, the conversion operation is initialized, and if the CS bit is set (to 1), conversion will be started from the beginning. The contents of the ADCR are undefined after RESET input.
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(2) Input voltage and conversion result The relationship between the analog input voltage input to an analog input pin (ANI0 to ANI7) and the A/D conversion result (value stored in ADCR) is shown by the following expression:
VIN x 256 + 0.5) AVREF1
ADCR = INT(
or (ADCR - 0.5) x
AVREF1 AVREF1 VIN < (ADCR + 0.5) x 256 256
Remark INT( ): VIN:
Function that returns the integer part of the value in ( ) Analog input voltage
AVREF1: AVREF1 pin voltage ADCR: ADCR value Figure 16-7 shows the relationship between the analog input voltage and the A/D conversion result in graphic form. Figure 16-7. Relationship between Analog Input Voltage and A/D Conversion Result
255
254
A/D conversion 253 result (ADCR)
3
2
1
0
1 1 3 2 5 3 512 256 512 256 512 256
507 254 509 255 511 512 256 512 256 512
1
Input voltage/AVREF1
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(3) A/D conversion time The A/D conversion time is determined by the system clock frequency (fCLK) and the FR bit of the A/D converter mode register (ADM). The A/D conversion time includes the entire time required for one A/D conversion operation, and the sampling time is also included in the A/D conversion time. These values are shown in Table 16-1. Table 16-1. A/D Conversion Time
System Clock (fCLK) Range 2 MHz fCLK 16 MHz 2 MHz fCLK 16 MHz FR Bit 0 Conversion Time 180/fCLK (11.3 s to 90 s) 120/fCLK (7.5 s to 60 s) Sampling Time 36/fCLK (2.3 s to 18 s) 24/fCLK (1.5 s to 12 s)
1
(4) A/D converter operation modes There are two A/D converter operation modes, scan mode and select mode. These modes are selected according to the setting of bit 0 (MS) of the A/D converter mode register (ADM). In addition, scan mode 0 or 1 can be selected by bit 5 (SCMD) of the ADM. Operation in either mode continues until the ADM is rewritten.
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16.4.2 Select mode One analog input is specified by bits 1 to 3 (ANIS0 to ANIS2) of the A/D converter mode register (ADM), and A/D conversion of the specified analog input pin is started. The conversion result is stored in the A/D conversion result register (ADCR). An A/D conversion end interrupt request (INTAD) is generated at the end of each conversion operation. Figure 16-8. Select Mode Operation Timing (a) TRG bit 0
A/D conversion
ANI3
ANI3
ANI3
ANI3
ANI3
ANI3
(
Conversion start CS 1 MS 1 ANIS2 to ANIS0 011 ADCR
(
ANI3 ANI3 ANI3 ANI3 ANI3
INTAD
(b) TRG bit 1
INTP5 Initialization A/D conversion ANI0 Initialization ANI0 ANI0 ANI0 Initialization ANI0 ANI0 ANI0
(
Conversion start Conversion end CS 1 MS 1 ANIS2 to ANIS0 000
(
Conversion end Conversion end
Conversion end
Conversion end
ADCR
ANI0
ANI0
ANI0
ANI0
INTAD
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16.4.3 Scan mode Two scan modes, 1 and 0, are available. In scan mode 0, delay control that takes delay in reading the A/D conversion result by the CPU into consideration can be performed. In scan mode 1, no delay control is performed but the A/D conversion interval is fixed. Generally, use of scan mode 1 is recommended. (1) Scan mode 0 (bit 5 (SCMD) of A/D converter mode register (ADM) = 0) Input from the analog input pins specified by bits 1 to 3 (ANIS0 to ANIS2) of the ADM is selected and converted in order. For example, if ANIS2 to ANIS0 of the ADM = 001, ANI0 and ANI1 will be scanned repeatedly (ANI0 ANI1 ANI0 ANI1 ...). In the scan mode, at the end of the conversion operation for each input the conversion value is stored in the A/D conversion result register (ADCR) and an A/D conversion end interrupt request (INTAD) is generated. Figure 16-9. Scan Mode 0 Operation Timing (a) TRG bit 0
A/D conversion
ANI0
ANI1
ANI0
ANI1
ANI0
ANI1
(
Conversion start Conversion end Conversion end Conversion end CS 1 MS 0 ANIS2 to ANIS0 001
(
Conversion end
Conversion end
Conversion end
ADCR
ANI0
ANI1
ANI0
ANI1
ANI0
INTAD
(b) TRG bit 1
INTP5 Initialization A/D conversion ANI0 ANI1 Initialization Initialization ANI2 ANI0 ANI0 Initialization ANI1 ANI0
(
Conversion start Conversion end Conversion end CS 1 MS 1 ANIS2 to ANIS0 010
Conversion end
Conversion end
(
ADCR
ANI0
ANI1
ANI0
INTAD
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(2) Scan mode 1 (bit 5 (SCMD) of A/D converter mode register (ADM) = 1) When bit 5 of the ADM is set (to 1), the analog input pins specified by bits 1 to 3 (ANIS0 to ANIS2) are selected, and subjected to conversion, in order. If an A/D conversion result register (ADCR) read is not performed by the CPU by the end of the next A/D conversion after A/D conversion end (INTAD) generation, conversion is restarted without performing INTAD generation, ADCR updating or channel updating (see Figure 16-10). If an ADCR read is performed by the CPU before the end of the next A/D conversion, the same operation as in scan mode 0 is performed. Figure 16-10. Scan Mode 1 Operation Timing
Channel updating disabled A/D conversion ANI0 ANI1 ANI2 ANI2 ANI3 ANI0
ADCR updating disabled
ADCR
ANI0
ANI1
ANI2
ANI3
Interrupt generation disabled INTAD
ADCR read
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16.4.4 A/D conversion operation start by software An A/D conversion operation start by software is performed by writing a value to the A/D converter mode register (ADM) that sets the TRG bit of the ADM register to 0 and the CS bit to 1. If a value is written to the ADM during an A/D conversion operation (CS bit = 1) such that the TRG bit is set to 0 and the CS bit to 1 again, the A/D conversion operation being performed at that time is suspended, and A/D conversion is started immediately in accordance with the written value. Once A/D conversion operation is started, as soon as one A/D conversion operation ends the next A/D conversion operation is started in accordance with the operation mode set by the ADM, and conversion operations continue repeatedly until an instruction that writes to the ADM is executed. When A/D conversion operation is started by software (TRG bit = 0), INTP5 pin (P26 pin) input does not affect the A/D conversion operation. (1) Select mode A/D conversion operation An A/D conversion operation is started on the analog input pin set by the A/D converter mode register (ADM). As soon as the A/D conversion operation ends, another A/D conversion operation is performed on the same analog input pin. An A/D conversion end interrupt request (INTAD) is generated at the end of each A/D conversion operation. Figure 16-11. Software Start Select Mode A/D Conversion Operation
A/D conversion
ANIn
ANIn
ANIn
ANIm
ANIm
ANIm
Conversion start CS 1, TRG 0
ADM rewrite CS 1, TRG 0
ADCR
ANIn
ANIn
ANIm
ANIm
INTAD
Remark n = 0, 1, ..., 7 m = 0, 1, ..., 7
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(2) Scan mode A/D conversion operation When conversion operation is started, an A/D conversion operation is started on the ANI0 pin input. When the A/D conversion operation ends, an A/D conversion operation is started on the next analog input pin. An A/D conversion end interrupt request (INTAD) is generated at the end of each A/D conversion operation. Figure 16-12. Software Start Scan Mode A/D Conversion Operation
A/D conversion (ANI0 to ANI2 scanned)
ANI0 Conversion start CS 1 TRG 0
ANI1
ANI2
ANI0
ANI0
ANI1
ANI2
ANI0
ANI1
ADM rewrite CS 1 TRG 0
ADCR
ANI0
ANI1
ANI2
ANI0
ANI1
ANI2
ANI0
INTAD
Interrupt request acknowledgment
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16.4.5 A/D conversion operation start by hardware An A/D conversion operation start by hardware is made possible by setting both the TRG bit and the CS bit of the A/D converter mode register (ADM) to 1. When the TRG bit and the CS bit of the ADM are both set to 1, external signals are placed in the standby state, and an A/D conversion operation is started when a valid edge is input to the INTP5 pin (P26 pin). If another valid edge is input to the INTP5 pin after the A/D conversion operation has been started by a valid edge input to the INTP5 pin, the A/D conversion operation being performed at that time is suspended, and A/D conversion is performed from the beginning in accordance with the contents set in the ADM. If a value is written to the ADM during an A/D conversion operation (CS bit = 1) such that the TRG bit and CS bit are both set to 1 again, the A/D conversion operation being performed at that time is suspended (the standby state is also suspended), and a standby state is entered in which the A/D converter waits for input of a valid edge to the INTP5 pin in the A/D conversion operation mode in accordance with the written value, and a conversion operation is started when a valid edge is input. Use of this function allows A/D conversion operations to be synchronized with external signals. Once A/D conversion operation is started, as soon as one A/D conversion operation ends the next A/D conversion operation is started in accordance with the operation mode set by the ADM (the A/D converter does not wait for INTP5 pin input), and conversion operations continue repeatedly until an instruction that writes to the ADM is executed, or a valid edge is input to the INTP5 pin. Caution Approximately 10 s is required from the time a valid edge is input to the INTP5 pin until the A/D conversion operation is actually started. This delay must be taken into account in the design stage. See CHAPTER 22 EDGE DETECTION FUNCTION for details of the edge detection function.
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(1) Select mode A/D conversion operation An A/D conversion operation is started on the analog input pin set by the A/D converter mode register (ADM). As soon as the A/D conversion operation ends, another A/D conversion operation is performed on the same analog input pin. An A/D conversion end interrupt request (INTAD) is generated at the end of each A/D conversion operation. If a valid edge is input to the INTP5 pin during an A/D conversion operation, the A/D conversion operation being performed at that time is suspended, and a new A/D conversion operation is started. Figure 16-13. Hardware Start Select Mode A/D Conversion Operation
INTP5 pin input (rising edge valid)
A/D conversion
Standby state ADM rewrite CS 1, TRG 1
ANIn
ANIn
ANIn
ANIn
ANIn Standby state
ANIm
ANIm
ADM rewrite CS 1, TRG 1 ANIn ANIn ANIn ANIm
ADCR
INTAD
INTAD acknowledgment
Remark n = 0, 1, ..., 7 m = 0, 1, ..., 7 (2) Scan mode A/D conversion operation When conversion operation is started, an A/D conversion operation is started on the ANI0 pin input. When the A/D conversion operation ends, an A/D conversion operation is started on the next analog input pin. An A/D conversion end interrupt request (INTAD) is generated at the end of each A/D conversion operation. If a valid edge is input to the INTP5 pin during an A/D conversion operation, the A/D conversion operation being performed at that time is suspended, and a new A/D conversion operation is started on the ANI0 pin input.
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422
INTP5 pin input (rising edge valid) A/D conversion (ANI0 to ANII2 scanned) Standby state ANI0 ADM rewrite CS 1, TRG 1 ADCR
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Figure 16-14. Hardware Start Scan Mode A/D Conversion Operation
ANI1
ANI2
ANI0
ANI1 ANI0
ANI0
ANI1
ANI2
Standby state
ANI0
ANI1
ANI2
ANI0
ADM rewrite CS 1, TRG 1 ANI0 ANI1 ANI2 ANI0 ANI0 ANI1 ANI0 ANI1 ANI2
CHAPTER 16
INTAD
INTAD aknowledgment
A/D CONVERTER
CHAPTER 16
A/D CONVERTER
16.5 External Circuit of A/D Converter The A/D converter is provided with a sample & hold circuit to stabilize its conversion operation. This sample & hold circuit outputs sampling noise during sampling immediately after an A/D conversion channel has been changed. To absorb this sampling noise, an external capacitor must be connected. If the impedance of the signal source is high, an error may occur in the conversion result due to the sampling noise. Especially when the scan mode is used, the impedance of the signal source must be kept low because the channel whose signal is to be converted changes one after another. One way to absorb the sampling noise is to increase the capacitance of the capacitor. However, if the capacitance is increased too much, the sampling noise is accumulated. Therefore, the most effective way is to reduce the resistance component. 16.6 Cautions (1) Range of voltages applied to analog input pins The following must be noted concerning A/D converter analog input pins ANI0 to ANI7 (P70 to P77). * A voltage outside the range AVSS to AVREF1 should not be applied to pins subject to A/D conversion during an A/D conversion operation. If this restriction is not observed, the PD784938 may be damaged. (2) Hardware start A/D conversion Approximately 10 s is required from the time a valid edge is input to the INTP5 pin until the A/D conversion operation is actually started. This delay must be taken into account in the design stage. See CHAPTER 22 EDGE DETECTION FUNCTION for details of the edge detection function. (3) Connecting capacitor to analog input pins A capacitor should be connected between the analog input pins (ANI0 to ANI7) and AVSS and between the reference voltage input pin (AVREF1) and AVSS to prevent misoperation due to noise.
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Figure 16-15. Example of Capacitor Connection on A/D Converter Pins
PD784938
Analog input 100 to 500 pF Reference voltage input AVREF1 ANI0 to ANI7
AVSS
(4) When the STOP mode or IDLE mode is used, the consumption current should be reduced by clearing (to 0) the CS bit before entering the STOP or IDLE mode. If the CS bit remains set (to 1), the conversion operation will be stopped by entering the STOP or IDLE mode, but the power supply to the voltage comparator will not be stopped, and therefore the A/D converter consumption current will not be reduced. (5) Once the A/D converter starts operating, conversion operations are performed repeatedly until the CS bit of the A/D converter mode (ADM) is cleared (to 0). Therefore, a superfluous interrupt may be generated if ADM setting is performed after interrupt-related registers, etc., are set when A/D converter mode conversion, etc., is performed. The result of this superfluous interrupt is that the conversion result storage address appears to have been shifted when the scan mode is used. Also, when the select mode is used, the first conversion result appears to have been an abnormal value, such as the conversion result for the other channel. It is therefore recommended that A/D converter mode conversion be carried out using the following procedure. <1> Write to the ADM (CS bit must be set (to 1)) <2> Interrupt request flag (ADIF) clearance (to 0) <3> Interrupt mask flag or interrupt service mode flag setting Operations <1> to <3> should not be divided by an interrupt or macro service. When scan mode 0 (no delay control) is used, in particular, you should ensure that the time between <1> and <2> is less than the time taken by one A/D conversion operation. Alternatively, the following procedure is recommended. <1> Stop the A/D conversion operation by clearing (to 0) the CS bit of the ADM. <2> Interrupt request flag (ADIF) clearance (to 0). <3> Interrupt mask flag or interrupt service mode flag setting <4> Write to the ADM
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CHAPTER 17 OUTLINE OF SERIAL INTERFACE
The PD784938 Subseries is provided with four independent serial interface channels. Therefore, communication with an external system and local communication within the system can be simultaneously executed by using these four channels. * Asynchronous serial interface (UART)/3-wire serial I/O (IOE) x 2 channels Refer to CHAPTER 18. * Clocked serial interface (CSI) x 2 channels
*
3-wire serial I/O mode (MSB/LSB first) Refer to CHAPTER 19.
Figure 17-1 shows an example of the serial interface. Figure 17-1. Example of Serial Interface UART + 3-wire serial I/O + 2-wire serial I/O
PD784938 (master)
PD4711A
Slave [3-wire serial I/O] SI SO SCK Port INT Slave
[UART] RS-232-C driver/ receiver
RxD TxD Port
SO1 SI1 SCK1 INTPm Port
Note
VDD SI0 SO0 SCK0 INTPn Port Note
VDD SB0
SCK0 Port INT [2-wire serial I/O]
Note Handshake line
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[MEMO]
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The PD784938 incorporates two serial interface channels for which asynchronous serial interface (UART) mode or 3-wire serial I/O (IOE) mode can be selected. The two UART/IOE channels have completely identical functions. In this chapter, therefore, unless stated otherwise, UART/IOE1 will be described as representative of both UART/IOEs. When used as UART2/IOE2, the UART/IOE1 register names, bit names and pin names should be read as their UART2/IOE2 equivalents as shown in Table 18-1. Table 18-1. Differences between UART/IOE1 and UART2/IOE2 Names
Item Pin names UART/IOE1 P25/ASCK/SCK1, P30/RxD/SI1, P31/TxD/SO2 ASIM TXE, RXE, PS1, PS0, CL, SL, ISRM, SCK ASIS PE, FE, OVE CSIM1 CTXE1, CRXE1, DIR1, CSCK1 BRGC TPS0 to TPS3, MDL0 to MDL3 INTSR/ITCSI1, INTSER, INTST UART2/IOE2 P12/ASCK2/SCK2, P13/RxD2/SI2, P14/TxD2/SO2 ASIM2 TXE2, RXE2, PS21, PS20, CL2, SL2, ISRM2, SCK2 ASIS2 PE2, FE2, OVE2 CSIM2 CTXE2, CRXE2, DIR2, CSCK2 BRGC2 TPS20 to TPS23, MDL20 to MDL23 INTSR2/INTCSI2, INTSER2, INTST2 SRIC2, CSIIC2, SERIC2, STIC2, SRIF2, SCIIF2, SERIF2, STIF2
Asynchronous serial interface mode register Asynchronous serial interface mode register bit names
Asynchronous serial interface status register Asynchronous serial interface status register bit names Clocked serial interface mode register Clocked serial interface mode register bit names Baud rate generator control register Baud rate generator control register bit names Interrupt request names
Interrupt control registers and bit names used in this chapter
SRIC, CSIIC1, SERIC, STIC, SRIF, CSIIF1, SERIF, STIF
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18.1
Switching between Asynchronous Serial Interface Mode and 3-Wire Serial I/O Mode
The asynchronous serial interface mode and 3-wire serial I/O mode cannot be used simultaneously. Switching between these modes is performed in accordance with the settings of the asynchronous serial interface mode register (ASIM/ASIM2) and the clocked serial interface mode register (CSIM1/CSIM2) as shown in Figure 18-1. Figure 18-1. Switching between Asynchronous Serial Interface Mode and 3-Wire Serial I/O Mode
7 ASIM TXE 6 RXE 5 PS1 4 PS0 3 CL 2 SL 1 ISRM 0 SCK Address 0FF88H After reset 00H R/W R/W
ASIM2
TXE2
RXE2
PS21
PS20
CL2
SL2
ISRM2 SCK2
0FF89H
00H
R/W
Asynchronous serial interface mode operation specification (see Figure 18-3) TXE TXE2 0 0 0 0 0 1 1 RXE CTXE1 CRXE1 RXE2 CTXE2 CRXE2 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 0 Setting prohibited Asynchronous serial interface mode Operation Mode Operation-stopped mode 3-wire serial I/O mode
Other than the above
7
6
5 0
4 0
3 0
2 DIR1
1 CSCK1
0 0
Address 0FF84H
After reset 00H
R/W R/W
CSIM1 CTXE1 CRXE1
CSIM2 CTXE2 CRXE2
0
0
0
DIR2
CSCK2
0
0FF85H
00H
R/W
3-wire serial I/O mode operation specification (see Figure 18-11)
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18.2
Asynchronous Serial Interface Mode
A UART (Universal Asynchronous Receiver Transmitter) is incorporated as the asynchronous serial interface. With this method, one byte of data is transmitted following a start bit, and full-duplex operation is possible. A baud rate generator is incorporated, enabling communication to be performed at any of a wide range of baud rates. Also, the baud rate can be defined by scaling the clock input to the ASCK pin. 18.2.1 Configuration in asynchronous serial interface mode The block diagram of the asynchronous serial interface is described in Figure 18-2. See 18.4 Baud Rate Generator for details of the baud rate generator.
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1/8 RXB, RXB2 Serial receive buffer P30/RXD, P13/RXD2 P31/TXD, P14/TXD2 Reception control parity check Shift register
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Figure 18-2. Asynchronous Serial Interface Block Diagram
Internal bus 1/8 1/8 TXE RXE PS1 PS0 CL CL2 SL TXE2 RXE2 PS21 PS20
ASIM, ASIM2 ISRM SCK CHAPTER 18 RESET
SL2 ISRM2 SCK2
ASIS, ASIS2 PE PE2 FE FE2 OVE OVE2 RESET Serial transmit TXS, shift register TXS2
ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
INTSER, INTSER2 INTSR, INTSR2
Transmission control parity addition
INTST, INTST2 Baud rate generator
1 m
1 m 1 2n fXX Selector
P25/ASCK, P12/ASCK2
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(1) Serial receive buffer (RXB/RXB2) This is the register that holds the receive data. Each time one byte of data is received, the receive data is transferred from the shift register. If a 7-bit data length is specified, receive data is transferred to bits 0 to 6 of RXB/RXB2, and the MSB of RXB/RXB2 is always "0". RXB/RXB2 can be read only by an 8-bit manipulation instruction. The contents of RXB/RXB2 are undefined after RESET input. (2) Serial transmit shift register (TXS/TXS2) This is the register in which the data to be transmitted is set. Data written to the TXS/TXS2 is transmitted as serial data. If a 7-bit data length is specified, bits 0 to 6 of the data written in the TXS/TXS2 are treated as transmit data. A transmit operation starts when a write to the TXS/TXS2 is performed. The TXS/TXS2 cannot be written to during a transmit operation. TXS/TXS2 can be written to only with an 8-bit manipulation instruction. The contents of TXS/TXS2 are undefined after RESET input. (3) Shift register This is the shift register that converts the serial data input to the RxD pin to parallel data. When one byte of data is received, the receive data is transferred to the receive buffer. The shift register cannot be manipulated directly by the CPU. (4) Reception control parity check Receive operations are controlled in accordance with the contents set in the asynchronous serial interface mode register (ASIM/ASIM2). In addition, parity error and other error checks are performed during receive operations, and if an error is detected, a value is set in the asynchronous serial interface status register (ASIS/ASIS2) according to the type of error. (5) Transmission control parity addition Transmission operation is controlled by appending a start bit, parity bit, and stop bit to the data written to the serial transmit shift registers (TXS/TXS2) in accordance with the contents set to the asynchronous serial interface mode registers (ASIM/ASIM2). (6) Selector Selects the baud rate clock source.
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18.2.2 Asynchronous serial interface control registers (1) Asynchronous serial interface mode register (ASIM), Asynchronous serial interface mode register 2 (ASIM2) ASIM and ASIM2 are 8-bit registers that specify the UART mode operation. These registers can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The format of ASIM and ASIM is shown in Figure 18-3. RESET input clears these registers to 00H.
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Figure 18-3. Format of Asynchronous Serial Interface Mode Register (ASIM) and Asynchronous Serial Interface Mode Register 2 (ASIM2)
7 ASIM TXE 6 RXE 5 PS1 4 PS0 3 CL 2 SL 1 ISRM 0 SCK Address 0FF88H After reset 00H R/W R/W
ASIM2
TXE2
RXE2
PS21
PS20
CL2
SL2
ISRM2 SCK2
0FF89H
00H
R/W
SCK SCK2 0 1 ISRM ISRM2 0 1 SL SL2 0 1 CL CL2 0 1
Specification of Input Clock to Baud Rate Generator External clock input (ASCK, ASCK2) Internal clock (fxx) Specification of Enabling/Disabling of Reception Completion Interrupt Generation in Case of Receive Error Enabled Disabled Stop Bit Length Specification (Transmission Only) 1 bit 2 bits Data Character Length Specification 7 bits 8 bits PS0 PS20 0 1 Parity Bit Specification
PS1 PS21 0 0
No parity Transmission = 0 parity addition Reception = Parity error not generated Odd parity Even parity
1 1
0 1
TXE TXE2 0 0 1 1
RXE RXE2 0 1 0 1
Transmit/Receive Operation Transmission/reception disabled, or 3-wire serial I/O mode Reception enabled Transmission enabled Transmission/reception enabled
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Caution An asynchronous serial interface mode register (ASIM/ASIM2) rewrite should not be performed during a transmit operation. If an ASIM/ASIM2 register rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal operation is restored by RESET input). Software can determine whether transmission is in progress by using a transmission completion interrupt (INTST/INTST2) or the interrupt request flag (STIF/STIF2) set by INTST/INTST2. (2) Asynchronous serial interface status register (ASIS), Asynchronous serial interface status register 2 (ASIS2) ASIS and ASIS2 contain flags that indicate the error contents when a receive error occurs. Flags are set (to 1) when a receive error occurs, and cleared (to 0) when data is read from the serial receive buffer (RXB/RXB2). If the next data is received before RXB/RXB2 is read, the overrun error flag (OVE/OVE2) is set (to 1), and the other error flags are cleared (to 0) (if there is an error in the next data, the corresponding error flag is set (to 1)). These registers can be read only with an 8-bit manipulation instruction or bit manipulation instruction. The format of ASIS and ASIS2 is shown in Figure 18-4. RESET input clears these registers to 00H. Figure 18-4. Format of Asynchronous Serial Interface Status Register (ASIS) and Asynchronous Serial Interface Status Register 2 (ASIS2)
7 ASIS 0 6 0 5 0 4 0 3 0 2 PE 1 FE 0 OVE Address 0FF8AH After reset 00H R/W R
ASIS2
0
0
0
0
0
PE2
FE2
OVE2
0FF8BH
00H
R
Overrun error flag 1 Next receive completed before data is read from receive buffer
Framing error flag 1 Stop bit not detected
Parity error flag 1 Transmit data parity specification and receive data parity do not match
Caution The serial receive buffer (RXB/RXB2) must be read even if there is a receive error. If RXB/RXB2 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely.
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18.2.3 Data format Serial data transmission/reception is performed in full-duplex asynchronous mode. The transmit/receive data format is shown in Figure 18-5. One data frame is made up of a start bit, character bits, parity bit, and stop bit(s). Character bit length specification, parity selection and stop bit length specification for one data frame are performed by means of the asynchronous serial interface mode register (ASIM). Figure 18-5. Asynchronous Serial Interface Transmit/Receive Data Format
1 data frame
Start bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity bit
Stop bit(s)
* Start bit ************************ 1 bit * Character bits ************* 7 bits/8 bits * Parity bits ******************** Even parity/odd parity/0 parity/no parity * Stop bits ********************** 1 bit/2 bits The serial transfer rate is selected in accordance with the asynchronous serial interface mode register and baud rate generator settings. If a serial data receive error occurs, the nature of the receive error can be determined by reading the asynchronous serial interface status register (ASIS) status.
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18.2.4 Parity types and operations The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmission side and the reception side. With even parity and odd parity, 1 bit (odd number) errors can be detected. With 0 parity and no parity, errors cannot be detected. * Even parity If the number of bits with a value of "1" in the transmit data is odd, the parity bit is set to "1", and if the number of "1" bits is even, the parity bit is set to "0". Control is thus performed to make the number of "1" bits in the transmit data plus the parity bit an even number. In reception, the number of "1" bits in the receive data plus the parity bit is counted, and if this number is odd, a parity error is generated. * Odd parity Conversely to the case of even parity, control is performed to make the number of "1" bits in the transmit data plus the parity bit an odd number. In reception, a parity error is generated if the number of "1" bits in the receive data plus the parity bit is even. * 0 parity In transmission, the parity bit is set to "0" irrespective of the receive data. In reception, parity bit detection is not performed. Therefore, no parity error is generated irrespective of whether the parity bit is "0" or "1". * No parity In transmission, a parity bit is not added. In reception, reception is performed on the assumption that there is no parity bit. Since there is no parity bit, no parity error is generated.
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18.2.5 Transmission The PD784938's asynchronous serial interface is set to the transmission enabled state when the TXE bit of the asynchronous serial interface mode register (ASIM) is set (to 1). A transmit operation is started by writing transmit data to the serial transmit shift register (TXS) when transmission is enabled. The start bit, parity bit and stop bit(s) are added automatically. When a transmit operation is started, the data in the TXS is shifted out, and a transmission completion interrupt (INTST) is generated when the TXS is empty. If no more data is written to the TXS, the transmit operation is discontinued. If the TXE bit is cleared (to 0) during a transmit operation, the transmit operation is discontinued immediately. Figure 18-6. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1
STOP TxD (output) START INTST D0 D1 D2 D6 D7 Parity
(b) Stop bit length: 2
TxD (output) START INTST
D0
D1
D2
D6
D7
Parity
STOP
Cautions 1. After RESET input the serial transmit shift register (TXS) is emptied but a transmission completion interrupt is not generated. A transmit operation can be started by writing transmit data to the TXS. 2. An asynchronous serial interface mode register (ASIM) rewrite should not be performed during a transmit operation. If an ASIM rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal operation is restored by RESET input). Software can determine whether transmission is in progress by using a transmission completion interrupt (INTST) or the interrupt request flag (STIF) set by INTST.
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18.2.6 Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (to 1), receive operations are enabled and sampling of the RxD input pin is performed. RxD input pin sampling is performed using the serial clock (divide-by-m counter input clock) specified by ASIM and band rate generator control register (BRGC). When the RxD pin input is driven low, the divide-by-m counter starts counting and a data sampling start timing signal is output on the m'th count. If the RxD pin input is low when sampled again by this start timing signal, the input is recognized as a start bit, the divide-by-m counter is initialized and the count is started, and data sampling is performed. When the character data, parity bit and stop bit are detected following the start bit, reception of one data frame ends. When reception of one data frame ends, the receive data in the shift register is transferred to the serial receive buffer, RXB, and a reception completion interrupt (INTSR) is generated. If an error occurs, the receive data in which the error occurred is still transferred to RXB. If bit 1 (ISRM) of the ASIM was cleared (to 0) when the error occurred, INTSR is generated. If the ISRM was set (to 1), INTSR is not generated. If the RXE bit is cleared (to 0) during a receive operation, the receive operation is stopped immediately. In this case the contents of RXB and ASIS are not changed, and no INTSR or INTSER interrupt is generated. Figure 18-7. Asynchronous Serial Interface Reception Completion Interrupt Timing
STOP RxD (input) START INTSR D0 D1 D2 D6 D7 Parity
Caution The serial receive buffer (RXB) must be read even if there is a receive error. If RXB is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely.
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18.2.7 Receive errors Three kinds of errors can occur in a receive operation: parity errors, framing errors, and overrun errors. As the result of data reception, an error flag is raised in the asynchronous serial interface status register (ASIS) and a receive error interrupt (INTSER) is generated. Receive error causes are shown in Table 18-2. It is possible to detect the occurrence of any of the above errors during reception by reading the contents of the ASIS (see Figures 18-4 and 18-8). The contents of the ASIS register are cleared (to 0) by reading the serial receive buffer (RXB) or by reception of the next data (if there is an error in the next data, the corresponding error flag is set). Table 18-2. Receive Error Causes
Receive Error Parity error Framing error Overrun error Cause Transmit data parity specification and receive data parity do not match Stop bit not detected Reception of next data completed before data is read from receive buffer
Figure 18-8. Receive Error Timing
STOP RxD (input) START INTSRNote D0 D1 D2 D6 D7 Parity
INTSER
Note If a receive error occurs while the ISRM bit is set (to 1), INTSR is not generated. Remark In the PD784938, a break signal cannot be detected by hardware. As a break signal is a low-level signal of two characters or more, a break signal may be judged to have been input if software detects the occurrence of two consecutive framing errors in which the receive data was 00H. The chance occurrence of two consecutive framing errors can be distinguished from a break signal by having the RxD pin level read by software (confirmation is possible by setting "1" in bit 0 of the port 3 mode register (PM3) and reading port 3 (P3)) and confirming that it is "0". Cautions 1. The contents of the asynchronous serial interface status register (ASIS) are cleared (to 0) by reading the serial receive buffer (RXB) or by reception of the next data. If you want to find the details of an error, therefore, ASIS must be read before reading RXB. 2. The RXB must be read even if there is a receive error. If RXB is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely.
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18.3
3-Wire Serial I/O Mode
The 3-wire serial I/O mode is used to communicate with devices that incorporate a conventional clocked serial interface. Basically, communication is performed using three lines: the serial clock (SCK), serial data output (SO), and serial data input (SI). Generally, a handshake line is necessary for checking the communication status. Figure 18-9. Example of 3-Wire Serial I/O System Configuration 3-wire serial I/O 3-wire serial I/O
Master CPU Slave CPU
SCK SO SI
Note
SCK SI SO Port Interrupt (port)
Port (interrupt) Port
Note Handshake lines 18.3.1 Configuration in 3-wire serial I/O mode The block diagram in the 3-wire serial I/O mode is shown in Figure 18-10.
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Figure 18-10. 3-Wire Serial I/O Mode Block Diagram
Internal bus 8 CTXE1 CRXE1 RESET CTXE2 CRXE2 DIR1 DIR2 CSCK1 Direction control circuit CSCK2 8 P30/SI1, P13/SI2 SO latch 8 CHAPTER 18 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
Shift register
D
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P31/SO1, P14/SO2 N-ch open-drain output enable
P27/SCK1, P12/SCK2
Serial clock counter
Interrupt signal generator
INTCSI1, INTCSI2
Baud rate generator Serial clock control circuit Selector
CSCK1, CSCK2
CSCK1, CSCK2
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(1) Serial shift register (SIO1/SIO2) SIO1 and SIO2 convert 8-bit serial data to 8-bit parallel data, and vice versa. SIO1/SIO2 is used for both transmission and reception. Actual transmit/receive operations are controlled by writing to/reading from SIO1/SIO2. These registers can be read or written with an 8-bit manipulation instruction. The contents of SIO1/SIO2 are undefined after RESET input. (2) SO latch The SO latch holds the SO1/SO2 pin output level. (3) Serial clock selector (1/2n) Generates and selects the serial clock to be used. (4) Serial clock counter Counts the serial clocks output or input in a transmit/receive operation, and checks that 8-bit data transmission/reception has been performed. (5) Interrupt signal generator Generates an interrupt request when 8 serial clocks have been counted by the serial clock counter. (6) Selector Selects whether data is input to the serial shift registers 1 and 2 (SIO1 and SIO2) from the SI1 and SI2 pins or output latches. (7) Direction control circuit Switches between MSB-first and LSB-first modes.
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18.3.2 Clocked serial interface mode registers (CSIM1, CSIM2) CSIM1 and CSIM2 are 8-bit registers that specify operations in the 3-wire serial I/O mode. These registers can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The CSIM1 and CSIM2 format is shown in Figure 18-11. RESET input clears these registers to 00H. Figure 18-11. Format of Clocked Serial Interface Mode Register 1 (CSIM1) and Clocked Serial Interface Mode Register 2 (CSIM2)
7 6 5 0 4 0 3 0 2 DIR1 1 CSCK1 0 0 Address 0FF84H After reset 00H R/W R/W
CSIM1 CTXE1 CRXE1
CSIM2 CTXE2 CRXE2
0
0
0
DIR2
CSCK2
0
0FF85H
00H
R/W (n = 1, 2)
CSCKn
Serial Clock Selection Bit Source Clock In case of SCKn (CTXEn, CRXEn = 1)
0 1
External input Input clock to SCKn pin Baud rate generator output CMOS output
DIRn 0 1
Operation Mode Specification (Transfer Bit Order) MSB-first LSB-first Transmit/Receive Operation Transmission/reception disabled, or asynchronous serial interface mode Reception enabled Transmission enabled Transmission/reception enabled
CTXEn CRXEn 0 0
0 1 1
1 0 1
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18.3.3 Basic operation timing In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in MSB-first or LSB-first order in synchronization with the serial clock. MSB/LSB switching is specified by the DIR1 bit of the clock serial interface mode register (CSIM1). Transmit data is output in synchronization with the fall of SCK1, and receive data is sampled on the rise of SCK1. An interrupt request (INTCSI1) is generated on the 8th rise of SCK1. When the internal clock is used as SCK1, SCK1 output is stopped on the 8th rise of SCK1 and SCK1 remains high until the next data transmit or receive operation is started. 3-wire serial I/O mode timing is shown in Figure 18-12. Figure 18-12. 3-Wire Serial I/O Mode Timing (1/2) (a) MSB-first
SCK1Note
1
2
3
4
5
6
7
8
SI1 (input)
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO1 (output)
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
INTCSI1 Transfer end interrupt generation
Start of transfer synchronized with fall of SCK1 Execution of instruction that writes to SIO1, etc.
Note Master CPU: Output Slave CPU: Input
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Figure 18-12. 3-Wire Serial I/O Mode Timing (2/2) (b) LSB-first
SCK1Note
1
2
3
4
5
6
7
8
SI1 (input)
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
SO1 (output)
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
INTCSI1 Transfer end interrupt generation
Start of transfer synchronized with fall of SCK1 Execution of instruction that writes to SIO1, etc.
Note Master CPU: Output Slave CPU: Input
Remark If the PD784938 is connected to a 2-wire serial I/O device, a buffer should be connected to the SO1 pin as shown in Figure 18-13. In the example shown in Figure 18-13, the output level is inverted by the buffer, and therefore the inverse of the data to be output should be written to SIO1. In addition, non-connection of the on-chip pull-up resistor should be specified for the P31/SO1 pin. Figure 18-13. Example of Connection to 2-Wire Serial I/O
PD784938
2-wire serial I/O device
SCK1
(Serial clock line)
SCK
SI1
(Serial data line)
SIO
SO1
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18.3.4 Operation when transmission only is enabled A transmit operation is performed when the CTXE1 bit of clocked serial interface mode register (CSIM1) is set (to 1). The transmit operation starts when a write to the serial shift register (SIO1) is performed while the CTXE1 bit is set (to 1). When the CTXE1 bit is cleared (to 0), the SO1 pin is in the output high level. (1) When the internal clock is selected as the serial clock When transmission starts, the serial clock is output from the SCK1 pin and data is output in sequence from SIO1 to the SO1 pin in synchronization with the fall of the serial clock, and SI1 pin signals are shifted into SIO1 in synchronization with the rise of the serial clock. There is a delay of up to one SCK1 clock cycle between the start of transmission and the first fall of SCK1. If transmission is disabled during the transmit operation (by clearing (to 0) the CTXE1 bit), SCK1 clock output is stopped and the transmit operation is discontinued on the next rise of SCK1. In this case an interrupt request (INTCSI1) is not generated, and the SO1 pin becomes output high level. (2) When an external clock is selected as the serial clock When transmission starts, data is output in sequence from SIO1 to the SO1 pin in synchronization with the fall of the serial clock input to the SCK1 pin after the start of transmission, and SI1 pin signals are shifted into SIO1 in synchronization with the rise of the SCK1 pin input. If transmission has not started, shift operations are not performed and the SO1 pin output level does not change even if the serial clock is input to the SCK1 pin. If transmission is disabled during the transmit operation (by clearing (to 0) the CTXE1 bit), the transmit operation is discontinued and subsequent SCK1 input is ignored. In this case an interrupt request (INTCSI1) is not generated, and the SO1 pin becomes output high level. 18.3.5 Operation when reception only is enabled A receive operation is performed when the CRXE1 bit of the clocked serial interface mode register (CSIM1) is set (to 1). The receive operation starts when the CRXE1 changes from "0" to "1", or when a read from serial shift register (SIO1) is performed. (1) When the internal clock is selected as the serial clock When reception starts, the serial clock is output from the SCK1 pin and the SI1 pin data is fetched in sequence into serial shift register (SIO1) in synchronization with the rise of the serial clock. There is a delay of up to one SCK1 clock cycle between the start of reception and the first fall of SCK1. If reception is disabled during the receive operation (by clearing (to 0) the CRXE1 bit), SCK1 clock output is stopped and the receive operation is discontinued on the next rise of SCK1. In this case an interrupt request (INTCSI1) is not generated, and the contents of the SIO1 are undefined. (2) When an external clock is selected as the serial clock When reception starts, the SI1 pin data is fetched into serial shift register (SIO1) in synchronization with the rise of the serial clock input to the SCK1 pin after the start of reception. If reception has not started, shift operations are not performed even if the serial clock is input to the SCK1 pin. If reception is disabled during the receive operation (by clearing (to 0) the CRXE1 bit), the receive operation is discontinued and subsequent SCK1 input is ignored. In this case an interrupt request (INTCSI1) is not generated.
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18.3.6 Operation when transmission/reception is enabled When the CTXE1 bit and CRXE1 bit of the clocked serial interface mode register (CSIM1) register are both set (1), a transmit operation and receive operation can be performed simultaneously (transmit/receive operation). The transmit/ receive operation is started when the CRXE1 bit is changed from "0" to "1", or by performing a write to serial shift register (SIO1). When a transmit/receive operation is started for the first time, the CRXE1 bit always changes from "0" to "1", and there is thus a possibility that the transmit/receive operation will start immediately, and undefined data will be output. The first transmit data should therefore be written to SIO1 beforehand when both transmission and reception are disabled (when the CTXE1 bit and CRXE1 bit are both cleared (to 0)), before enabling transmission/reception. However, specify whether data is transferred with MSB or LSB first before writing the SIO1. Even if the specification is made after writing the SIO1, the byte order of the data already stored in the SIO1 cannot be changed. When transmission/reception is disabled (CTXE1 = CRXE1 = 0), the SO1 pin is in the output high level. (1) When the internal clock is selected as the serial clock When transmission/reception starts, the serial clock is output from the SCK1 pin, data is output in sequence from serial shift register (SIO1) to the (SO1) pin in synchronization with the fall of the serial clock, and SI1 pin data is shifted in order into SIO1 in synchronization with the rise of the serial clock. There is a delay of up to one SCK1 clock cycle between the start of transmission and the first fall of SCK1. If either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is discontinued. If transmission only is disabled, the SO1 pin becomes output high level. If reception only is disabled, the contents of the SIO1 will be undefined. If transmission and reception are disabled simultaneously, SCK1 clock output is stopped and the transmit and receive operations are discontinued on the next rise of SCK1. When transmission and reception are disabled simultaneously, the contents of SIO1 are undefined, an interrupt request (INTCSI1) is not generated, and the SO1 pin becomes output high level. (2) When an external clock is selected as the serial clock When transmission/reception starts, data is output in sequence from serial shift register (SIO1) to the SO1 pin in synchronization with the fall of the serial clock input to the SCK1 pin after the start of transmission/reception, and SI1 pin data is shifted in order into SIO1 in synchronization with the rise of the serial clock. If transmission/reception has not started, the SIO1 shift operations are not performed and the SO1 pin output level does not change even if the serial clock is input to the SCK1 pin. If either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is discontinued. If transmission only is disabled, the SO1 pin becomes output high level. If reception only is disabled, the contents of the SIO1 will be undefined. If transmission and reception are disabled simultaneously, the transmit and receive operations are discontinued and subsequent SCK1 input is ignored. When transmission and reception are disabled simultaneously, the contents of SIO1 are undefined, an interrupt request (INTCSI1) is not generated, and the SO1 pin becomes output high level. 18.3.7 Corrective action in case of slippage of serial clock and shift operations When an external clock is selected as the serial clock, there may be slippage between the number of serial clocks and shift operations due to noise, etc. In this case, since the serial clock counter is initialized by disabling both transmit operations and receive operations (by clearing (to 0) the CTXE1 bit and CRXE1 bit), synchronization of the shift operations and the serial clock can be restored by using the first serial clock input after reception or transmission is next enabled as the first clock.
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18.4
Baud Rate Generator
The baud rate generator is the circuit that generates the UART/IOE serial clock. Two independent circuits are incorporated, one for each serial interface. 18.4.1 Baud rate generator configuration The baud rate generator block diagram is shown in Figure 18-14.
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Figure 18-14. Baud Rate Generator Block Diagram
Start bit detection RESET 1/8 CSIM1, CSIM2 5-bit counter Clear UART reception shift clock 1/2 Match Start bit detection sampling clock Clocked serial interface mode registers 1 & 2
Internal bus 1/8 ASIM1, ASIM2 Asynchronous serial interface mode registers 1 & 2 8 BRGC, BRGC2
CHAPTER 18
Baud rate generator control register
RESET
CSCK1
SCK
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Shift clock for UART transmission & IOE
Selector
1/2
Selector
Match
fPRS CSCK1 5-bit counter BRGC write RESET
Selector
Frequency divider
fXX Selector P25/ASCK/SCK1, P12/ASCK2/SCK2
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(1) 5-bit counter Counter that counts the clock (fPRS) by which the output from the frequency divider is selected. Generates a signal with the frequency selected by the low-order 4 bits of the baud rate generator control registers (BRGC/BRGC2). (2) Frequency divider Scales the internal clock (fXX) or, in asynchronous serial interface mode, a clock that is twice the external baud rate input (ASCK/ASCK2), and selects fPRS with the next-stage selector. (3) Both-edge detection circuit Detects both edges of the ASCK/ASCK2 pin input signal and generates a signal with a frequency twice that of the ASCK/ ASCK2 input clock. 18.4.2 Baud rate generator control register (BRGC, BRGC2) BRGC and BRGC2 are 8-bit registers that set the baud rate clock in asynchronous serial interface mode or the shift clock in 3-wire serial I/O mode. These registers can be written to only with an 8-bit manipulation instruction. The BRGC and BRGC2 format is shown in Figure 18-15. RESET input clears BRGC to 00H. Caution When a baud rate generator control register (BRGC, BRGC2) write instruction is executed, the 5-bit counter and 1/2 frequency divider operations are reset. Consequently, if a write to the BRGC and BRGC2 is performed during communication, the generated baud rate clock may be disrupted, preventing normal communication from continuing. The BRGC and BRGC2 should therefore not be written to during communication.
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Figure 18-15. Format of Baud Rate Generator Control Register (BRGC) and Baud Rate Generator Control Register 2 (BRGC2)
7 BRGC TPS3 6 TPS2 5 TPS1 4 TPS0 3 MDL3 2 MDL2 1 MDL1 0 MDL0 Address 0FF90H After reset 00H R/W R/W
BRGC2 TPS23 TPS22 TPS21 TPS20 MDL23 MDL22 MDL21 MDL20 0FF91H
00H
R/W
fPRS: Prescaler output selection clock MDL3 MDL2 MDL1 MDL0 k 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Baud Rate Generator Input ClockNote 1 fPRS/16 fPRS/17 fPRS/18 fPRS/19 fPRS/20 fPRS/21 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 fPRS/28 fPRS/29 fPRS/30 fPRSNote 2
MDL23 MDL22 MDL21 MDL20 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Notes 1. Only fPRS/16 can be selected when ASCK/ASCK2 input is used. 2. Can only be used in 3-wire serial I/O mode. fXX: Oscillator frequency or external clock input TPS3 TPS2 TPS1 TPS0 n 0 1 2 3 4 5 6 7 8 9 10 11 12-Bit Prescaler Tap Selection (fPRS) fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 fXX/2,048 fXX/4,096 fASCK/2Note fASCK/4 fASCK/8 fASCK/16 fASCK/32 fASCK/64 fASCK/128 fASCK/256 fASCK/512 fASCK/1,024 fASCK/2,048 fASCK/4,096
TPS23 TPS22 TPS21 TPS20 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1
Other than the above
Setting prohibited
Note Can not be selected when the value set in bits MDL3 to MDL0, k = 15.
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18.4.3 Baud rate generator operation The baud rate generator only operates when UART/IOE transmit/receive operations are enabled. The generated baud rate clock is a signal scaled from the internal clock (fXX) or a signal scaled from the clock input from the external baud rate input (ASCK) pin. Caution If a write to the baud rate generator control register (BRGC) is performed during communication, the generated baud rate clock may be disrupted, preventing normal communication from continuing. The BRGC should therefore not be written to during communication. (1) Baud rate clock generation in UART mode (a) Using internal clock (fXX) This function is selected by setting (to 1) bit 0 (SCK) of the asynchronous serial interface mode register (ASIM). The internal clock (fXX) is scaled by the frequency divider, this signal (fPRS) is scaled by the 5-bit counter, and the signal further divided by 2 is used as the baud rate. The baud rate is given by the following expression: (Baud rate) = fXX (k + 16) * 2n+2
fXX: Oscillator frequency or external clock input frequency k: n: Value set in bits MDL3 to MDL0 of BRGC (k = 0 to 14) Value set in bits TPS3 to TPS0 of BRGC (n = 0 to 11)
(b) Using external baud rate input This function is selected by clearing (to 0) bit 0 (SCK) of the asynchronous serial interface mode register (ASIM). When this function is used, bits MDL3 to MDL0 of the baud rate generator control register (BRGC) must all be cleared (to 0) (k = 0). When this function is used with UART2, it is necessary to set (to 1) bit 2 of the port 1 mode control register (PMC1) and set the P12 pin to control mode. The ASCK pin input clock is scaled by the frequency divider, and the signal obtained by dividing this signal by 32 (fPRS) (division by 16 and division by 2) is used as the baud rate. The baud rate is given by the following expression: (Baud rate) = fASCK: ASCK pin input clock frequency n: Value set in bits TPS3 to TPS0 of BRGC (n = 0 to 11) fASCK 2n+6
When this function is used, a number of baud rates can be generated by one external input clock.
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(2) Serial clock generation in 3-wire serial I/O mode Selected when the CSCK1 bit of the clocked serial interface mode register (CSIM1) is set (to 1) and SCK1 is output. (a) Normal mode The internal clock (fXX) is scaled by the frequency divider, this signal (fPRS) is scaled by the 5-bit counter, and the signal further divided by 2 is used as the serial clock. The serial clock is given by the following expression: (Serial clock) = fXX (k + 16) * 2n+2
fXX: Oscillator frequency or external clock input frequency k: n: Value set in bits MDL3 to MDL0 of BRGC (k = 0 to 14) Value set in bits TPS3 to TPS0 of BRGC (n = 0 to 11)
(b) High-speed mode When this function is used, bits MDL3 to MDL0 of the baud rate generator control register (BRGC) are all set (1) (k= 15). The internal clock (fXX) is scaled by the frequency divider, and this signal (fPRS) divided by 2 is used as the serial clock. The serial clock is given by the following expression: (Serial clock) = fXX 2n+2
fXX: Oscillator frequency or external clock input frequency n: Value set in bits TPS3 to TPS0 of BRGC (n = 1 to 11)
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18.4.4 Baud rate setting in asynchronous serial interface mode There are two methods of setting the baud rate, as shown in Table 18-3. This table shows the range of baud rates that can be generated, the baud rate calculation expression and selection method for each case. Table 18-3. Baud Rate Setting Methods
Baud Rate Clock Source Selection Method Baud Rate Calculation Expression fXX (k + 16) * 2n+2 fASCK 2n+6 Baud Rate Range
Baud rate generator
Internal system clock
SCK in ASIM = 1
fXX fXX to 245,760 64 fASCK fASCKNote to 131,072 64
ASCK input
SCK in ASIM = 0
Note Including fASCK input range: (0 to fXX/256) Remarks fXX: k: n: Oscillator frequency or external clock input frequency Value set in bits MDL3 to MDL0 of BRGC (k = 0 to 14; see Figure 18-15) Value set in bits TPS3 to TPS0 of BRGC (n = 0 to 11; see Figure 18-15)
fASCK: ASCK input clock frequency (0 to fXX/4) (1) Examples of settings when baud rate generator is used Examples of baud rate generator control register (BRGC) settings when the baud rate generator is used are shown below. When the baud rate generator is used, the SCK bit of the asynchronous serial interface mode register (ASIM) should be set (to 1). Table 18-4. Examples of BRGC Settings when Baud Rate Generator is Used
Oscillator Frequency (fXX) or External Clock (fX) Baud Rate [bps] 75 110 150 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 76,800 12.0 MHz 11.0592 MHz
BRGC Value
Error (%) 2.34 1.36 2.34 2.34 2.34 2.34 2.34 2.34 2.34 2.34 0.00 2.34 2.34
BRGC Value
Error (%) 0.00 1.82 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.54 0.00 0.00
A4H 9BH 94H 84H 74H 64H 54H 44H 34H 24H 19H 14H 04H
A2H 99H 92H 82H 72H 62H 52H 42H 32H 22H 16H 12H 02H
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(2) Examples of settings when external baud rate input (ASCK) is used Table 18-5 shows an example of setting when external baud rate input (ASCK) is used. When using the ASCK input, clear the SCK bit of the asynchronous serial interface mode register (ASIM) to 0, and set the corresponding pin in the control mode by using PMC3 or PMC1. Table 18-5. Examples of Settings when External Baud Rate Input (ASCK) is Used
fASCK (ASCK Input Frequency) Baud Rate [bps] 75 150 300 600 1,200 2,400 4,800 9,600 19,200 38,400 76,800 153.6 kHz 4.9152 MHz
BRGC Value 50H 40H 30H 20H 10H 00H -- -- -- -- --
BRGC Value A0H 90H 80H 70H 60H 50H 40H 30H 20H 10H 00H
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18.5
Cautions
(1) An asynchronous serial interface mode register (ASIM) rewrite should not be performed during a transmit operation. If an ASIM rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal operation is restored by RESET input). Software can determine whether transmission is in progress by using a transmission completion interrupt (INTST) or the interrupt request flag (STIF) set by INTST. (2) After RESET input the serial transmit shift register (TXS) is emptied but a transmission completion interrupt is not generated. A transmit operation can be started by writing transmit data to the TXS. (3) The serial receive buffer (RXB) must be read even if there is a receive error. If RXB is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. (4) The contents of the asynchronous serial interface status register (ASIS) are cleared (to 0) by reading the serial receive buffer (RXB) or by reception of the next data. If you want to find the details of an error, therefore, ASIS must be read before reading RXB. (5) The baud rate generator control register (BRGC) should not be written to during communication. If a write instruction is executed, the 5-bit counter and 1/2 frequency divider operations will be reset, and the generated baud rate clock may be disrupted, preventing normal communication from continuing. (6) To specify the transfer bit order with CSIM1 and CSIM2 (bit 2 manipulation), do not set the CTXE and CRXE bits at the same time. If these bits are specified at the same time, the bit transfer order may not be as specified.
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The PD784938 has two channels of serial interfaces in 3-wire serial I/O mode (IOE0/IOE3). The two channels of IOE have identical functions. Unless otherwise specified, therefore, IOE0 is explained in this chapter. To use IOE3, refer to Table 19-1 for the register name, bit name, and pin name of IOE3. Table 19-1. Differences in Name between IOE0 and IOE3
Item Pin name P32/SCK0 P27/SI0 P33/SO0 CSIM ENCSI, DIR, CRXE, MOD, SELCL2 to SELCL0 SIO INTCSI IOE0 P105/SCK3 P106/SI3 P107/SO3 CSIM3 ENCSI3, DIR3, CRXE3, MOD3, SELCL32 to SELCL30 SIO3 INTCSI3 IOE3
Clocked serial interface mode register Clocked serial interface mode register bit names
Serial shift register Interrupt request name
19.1 Function In the 3-wire serial I/O mode (MSB/LSB first), basically, three lines are used for communication: serial clock (SCK0), serial data output (SO0), and serial data input (SI0). communication status. Generally, a handshake line is necessary for checking the
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19.2 Configuration Figure 19-1 shows the block diagram of the clocked serial interface in the 3-wire serial I/O mode (note that the functions of both channels are identical). Figure 19-1. Clocked Serial Interface Block Diagram
SIO P27/SI0
CSIM EN SEL DIR CRX MO SEL SEL SEL E D CL2 CL1 CL0 CSI ST Shift LSB/MSB N-ch open-drain specification
Selector
0
Write to SIO Read to SIO
To P33/SO0 port block
Q
S
1
R Interrupt signal generation circuit Eighth clock SELCL. 0 to 2
Serial clock counter
INTCSI
To P32/SCK0 port block
External clock selection
fXX/8 fXX/16 fXX/32 fXX/64 fXX/128
(1) Serial shift register (SIO) The SIO converts 8-bit serial data to 8-bit parallel data, and vice versa. SIO is used for both transmission and reception. Data is received or transmitted starting from the MSB (or LSB). Actual transmit/receive operations are controlled by writing to/reading from SIO. SIO can be read or written to with an 8-bit manipulation instruction. The contents of SIO are undefined after RESET input. (2) Serial clock counter Counts the serial clocks output or input in a transmit/receive operation, and checks that 8-bit data transmission/reception has been performed. (3) Interrupt signal generator A interrupt request is generated when 8 serial clocks have been counted by the serial clock counter.
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19.3 Control Registers 19.3.1 Clocked serial interface mode register (CSIM, CSIM3) CSIM and CSIM3 are 8-bit registers that specify the serial interface operation mode (enable/disable), serial clock, etc. These registers can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The CSIM and CSIM3 format is shown in Figure 19-1. RESET input clears these registers to 00H. Figure 19-2. Format of Clocked Serial Interface Mode Register (CSIM) and Clocked Serial Interface Mode Register 3 (CSIM3)
7 6 5 DIR 4 3 2 1 0 Address 0FF82H After reset 00H R/W R/W
CSIM ENCSI SELST
CRXE MOD SELCL2 SELCL1 SELCL0
CSIM3 ENCSI3 SELST3 DIR3 CRXE3 MOD3 SELCL32 SELCL31 SELCL30
0FF80H
00H
R/W
(n = 3 with CSIM3 only) SELCL SELCL SELCL n2 n1 n0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Serial Clock Specification External clockNote 1 fXX/128 fXX/64 fXX/32 fXX/16 fXX/8Note 2
Other than the above Setting prohibited MODn N-ch Open-Drain Specification (P32, P33, or P105, P107) 0 1 Not N-ch open drain N-ch open drain
CRXEn Enables/Disables Serial Interface Receive Operation 0 1 DIRn 0 1 SELSTn 0 1 ENCSIn 0 1 Reception disabled Reception enabled Serial Interface Bit Transfer Order Selection MSB first LSB first Transmit Activation Condition Selection Start with a write operation to SIO (serial shift register) Start with a read operation from SIO Enables/Disables Serial Interface Operation Disabled Enabled
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Notes 1. When the external clock is selected, the usable serial clock is MIN fXX/8 in the case of fCLK = fXX/1; otherwise, it is MIN fCLK/4. 2. Setting is prohibited when the system clock (fCLK = fXX/8) is selected. Caution When bit 3 is set, the P-ch of the output buffer is forcibly turned OFF. This channel is not affected by PM3 and PMC3, or PM10 and PMC10. Therefore, if the input or output mode is changed by using the PM register with bit 3 set in the port mode, the content of the port latch can be output and the pin level can be read in the N-ch open-drain mode.
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19.4 3-Wire Serial I/O Mode The 3-wire serial I/O mode is used to communicate with devices that incorporate a conventional clocked serial interface. Basically, communication is performed using three lines: the serial clock (SCK0), serial data output (SO0), and serial data input (SI0). Generally, a handshake line is necessary for checking the communication status. Figure 19-3. Example of 3-Wire Serial I/O System Configuration
Master CPU Slave CPU
SCK0 SO0
SCK SI SO
Note
PD784938
SI0 Port (interrupt) Port
Port Interrupt (port)
Note Handshake lines
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19.4.1 Basic operation timing In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in MSB-first or LSB-first order in synchronization with the serial clock. MSB first/LSB first switching is specified by the DIR bit of the clocked serial interface mode register (CSIM). Transmit data is output in synchronization with the fall of SCK0, and receive data is sampled on the rise of SCK0. An interrupt request (INTCSI) is generated on the 8th rise of SCK0. When the internal clock is used as SCK0, SCK0 output is stopped on the 8th rise of SCK0 and SCK0 remains high until the next data transmit or receive operation is started. 3-wire serial I/O mode timing is shown in Figure 19-4. Figure 19-4. 3-Wire Serial I/O Mode Timing (1/2) (a) MSB-first
SCK0Note
1
2
3
4
5
6
7
8
SI0 (input)
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0 (output)
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
INTCSI Transfer end interrupt generation
Start of transfer synchronized with fall of SCK0 Execution of instruction that writes to SIO, etc.
Note Master CPU: Output Slave CPU: Input
Cautions 1. If data is written to SIO during transfer operation after the transfer was started by writing SIO, malfunctioning may occur. Therefore, do not rewrite SIO during the transfer operation. 2. The operation is immediately stopped even during transfer operation if the ENCSI bit is cleared (to 0).
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Figure 19-4. 3-Wire Serial I/O Mode Timing (2/2) (b) LSB-first
SCK0Note
1
2
3
4
5
6
7
8
SI0 (input)
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
SO0 (output)
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
INTCSI Transfer end interrupt generation
Start of transfer synchronized with fall of SCK0 Execution of instruction that writes to SIO, etc.
Note Master CPU: Output Slave CPU: Input
In the 3-wire serial I/O mode, the SO0 pin functions as a CMOS push-pull output.
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19.4.2 Operation when transmission only is enabled When the CRXE bit of the clocked serial interface mode register (CSIM) is cleared (to 0), data is only transmitted and reception is disabled. Transmission is started when data is written to the serial shift register (SIO) with the ENCSI bit set (to 1). Transmit data is input to SIO instead of the data received from the SI0 pin. If reception is disabled, therefore, the transmit data can be saved without being lost. If an instruction that writes data to SI0 is executed when ENCSI = 1 and CRXE = 0, the data is transmitted in 1-bit units in synchronization with the serial clock. The data of the first bit is output from the SO0 pin, and at the same time, input to the last bit of SI0. When the transmission is completed by repeating this operation eight times, an interrupt request is generated. Figure 19-5. Operation when Reception is Disabled
SIO
SI0 pin
Serial I/O shift register
(a) When the internal clock is selected as the serial clock When transmission starts, the serial clock is output from the SCK0 pin and data is output in sequence from SIO to the SO0 pin in synchronization with the fall of the serial clock, and SI0 pin signals are shifted into SIO in synchronization with the rise of the serial clock. There is a delay of up to one SCK0 clock cycle between the start of transmission and the first fall of SCK0. (b) When an external clock is selected as the serial clock When transmission starts, data is output in sequence from SIO to the SO0 pin in synchronization with the fall of the serial clock input to the SCK0 pin after the start of transmission, and SI0 pin signals are shifted into SIO in synchronization with the rise of the SCK0 pin input. If transmission has not started, shift operations are not performed and the SO0 pin output level does not change even if the serial clock is input to the SCK0 pin. If transmission is disabled during the transmit operation (by clearing (to 0) the ENCSI), the transmit operation is discontinued and subsequent SCK0 input is ignored. In this case an interrupt request (INTCSI) is not generated. Even if the serial clock is input to SCK0 while the CTXE bit is cleared (to 0), shift operations are not performed and the SO0 pin output level does not change. Caution When the external clock is selected, do not input the serial clock to the SCK0 pin before setting transmit data to SIO after transmission has been started. Otherwise, undefined data may be output. Similarly, do not use the macro service when the external clock is selected.
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19.4.3 Operation when reception only is enabled To enable only reception, set (to 1) the ENCSI and CRXE bits of the clocked serial interface mode register (CSIM). Also set the P33/SO0 pin in the port mode by using the port 3 mode control register (PMC3) (if this pin is not set in the port mode, it outputs data). Reception can be started by reading the serial shift register (SIO). 19.4.4 Operation when transmission/reception is enabled When the ENCSI bit and CRXE bit of the clocked serial interface mode register (CSIM) are both set (to 1), a transmit operation and receive operation can be performed simultaneously (transmit/receive operation). Both transmission and reception can be started by writing data to SIO when both the ENCSI and CRXE bits are set (to 1). (a) When the internal clock is selected as the serial clock When transmission/reception starts, the serial clock is output from the SCK0 pin, data is output in sequence from serial shift register (SIO) to the SO0 pin in synchronization with the fall of the serial clock, and SI0 pin data is shifted in order into SIO in synchronization with the rise of the serial clock. There is a delay of up to one SCK0 clock cycle between the start of transmission and the first fall of SCK0. (b) When an external clock is selected as the serial clock When transmission/reception starts, data is output in sequence from serial shift register (SIO) to the SO0 pin in synchronization with the fall of the serial clock input to the SCK0 pin after the start of transmission/reception, and SI0 pin data is shifted in order into SIO in synchronization with the rise of the serial clock. If transmission/reception has not started, shift operations are not performed and the SO0 pin output level does not change even if the serial clock is input to the SCK0 pin. Caution When the external clock is selected, do not input the serial clock to the SCK0 pin before setting transmit data to SIO after transmission has been started. Otherwise, undefined data may be output. Similarly, do not use the macro service when the external clock is selected. 19.4.5 Corrective action in case of slippage of serial clock and shift operations When an external clock is selected as the serial clock, there may be slippage between the number of serial clocks and shift operations due to noise, etc. In this case, since the serial clock counter is initialized by disabling both transmit operations and receive operations (by clearing (to 0) the ENCSI bit), synchronization of the shift operations and the serial clock can be restored by using the first serial clock input after reception or transmission is next enabled as the first clock.
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20.1 IEBus Controller Function IEBus (Inter Equipment Bus) is a small-scale digital data transmission system that transmits data between units. To implement IEBus with the PD784938 Subseries, external IEBus driver and receiver are necessary because they are not provided. The internal IEBus controller of the PD784938 Subseries is of negative logic. 20.1.1 Communication protocol of IEBus The communication protocol of the IEBus is as follows: (1) Multi-master mode All the units connected to the IEBus can transmit data to the other units. (2) Broadcasting communication function Communication between one unit and plural units can be performed as follows: * Group-unit broadcasting communication: Broadcasting communication to group units * All-unit broadcasting communication: Broadcasting communication to all units. (3) Effective transfer rate The effective transfer rate is in mode 1 (the PD784938 does not support modes 0 and 2 of effective transfer rate). * Mode 1: Approx. 17 kbps Caution Different modes must not be mixed on one IEBus. (4) Communication mode Data transfer is executed in half-duplex asynchronous communication mode. (5) Access control: CSMA/CD (Carrier Sense Multiple Access with Collision Detection) The priority of the IEBus is as follows: <1> Broadcasting communication takes precedence over individual communication (communication from one unit to another). <2> The lower master address takes precedence. (6) Communication scale The communication scale of IEBus is as follows: * Number of units: 50 MAX. * Cable length: 150 m MAX. (when twisted pair cable is used)
Caution The communication scale in an actual system differs depending on the characteristics of the cables, etc., constituting the IEBus driver/receiver and IEBus.
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20.1.2 Determination of bus mastership (arbitration) An operation to occupy the bus is performed when a unit connected to the IEBus controls the other units. This operation is called arbitration. When two or more units simultaneously start transmission, arbitration is to grant one of the units the permission to occupy the bus. Because only one unit is granted the bus mastership as a result of arbitration, the priority condition of the bus is predetermined as follows: Caution The bus mastership is released if communication is aborted. (1) Priority by communication type Broadcasting communication (communication from one unit to plural units) takes precedence over normal communication (communication from one unit to another). (2) Priority by master address If the communication type is the same, communication with the lower master address takes precedence. A master address consists of 12 bits, with unit 000H having the highest priority and unit FFFH having the lowest priority. 20.1.3 Communication mode Although the IEBus has three communication modes each having a different transfer rate, the PD784938 Subseries supports only communication mode 1. The transfer rate and the maximum number of transmit bytes in one communication frame in communication mode 1 are as shown in Table 20-1. Table 20-1. Transfer Rate and Maximum Number of Transmit Bytes in Communication Mode 1
Communication Mode 1 Maximum Number of Transmit Bytes (bytes/frame) 32 Effective Transfer Rate (kbps)Note Approx. 17
Note The effective transfer rate when the maximum number of transmit bytes is transmitted. Select the communication mode (mode 1) for each unit connected to the IEBus before starting communication. If the communication mode of the master unit and that of the mating unit (slave unit) are not the same, communication is not correctly executed. 20.1.4 Communication address With the IEBus, each unit is assigned a specific 12-bit address. This communication address consists of the following identification numbers: High-order 4 bits: Group number (number to identify the group to which each unit belongs) Low-order 8 bits: Unit number (number to identify each unit in a group)
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20.1.5 Broadcasting communication Normally, transmission or reception is performed between the master unit and its mating slave unit on a one-to-one basis. During broadcasting communication, however, two or more slave units exist and the master unit executes transmission to these slave units. Because plural slave units exist, the slave units do not return an acknowledge signal during communication. Whether broadcasting communication or normal communication is to be executed is selected by broadcasting bit (for this bit, refer to 20.1.6 (2) Broadcasting request bit). Broadcasting communication can be classified into the following two types: (1) Group-unit broadcasting communication Broadcasting communication is performed to the units in a group identified by the group number indicated by the highorder 4 bits of the communication address. (2) All-unit broadcasting communication Broadcasting communication is performed to all the units, regardless of the value of the group number. Group-unit broadcasting and all-unit broadcasting are identified by the value of the slave address (for the slave address, refer to 20.1.6 (4) Slave address field). 20.1.6 Transmission format of IEBus Figure 20-1 shows the transmission signal format of the IEBus. Figure 20-1. IEBus Transmission Signal Format
Master address field Slave address field Telegraph Control field length field
Header
Data field
Frame format
Broad- Master Slave Start Control casting address P address P A PA bit bit bit bit bit
TeleData graph PA length P A bit bit
Data PA bit
Remarks 1. P: Parity bit, A: ACK/NACK bit 2. The master station ignores the acknowledge bit during broadcasting communication. (1) Start bit The start bit is a signal that informs the other units of the start of data transmission. The unit that is to start data transmission outputs a high-level signal (start bit) from the TX pin for a specific time, and then starts outputting the broadcasting bit. If another unit has already output its start bit when one unit is to output the start bit, this unit does not output the start bit but waits for completion of output of the start bit by the other unit. When the output of the start bit by the other unit has completed, the unit starts outputting the broadcasting bit in synchronization with the completion of the start bit output by the other unit. The units other than the one that has started communication detect this start bit, and enter the reception status.
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(2) Broadcasting bit This bit indicates whether the master selects one slave (individual communication) or plural slaves (broadcasting communication) as the other party of communication. When the broadcasting request bit is 0, it indicates broadcasting communication; when it is 1, individual communication is indicated. Broadcasting communication is classified into two types: group-unit communication and all-unit communication. These communication types are identified by the value of the slave address (for the slave address, refer to (4) Slave address field). Because two or more slave units exist in the case of broadcasting communication, the acknowledge bit in each field subsequent to the master address field is not returned. If two or more units start transmitting a communication frame at the same time, broadcasting communication takes precedence over individual communication, and wins in arbitration. If one station occupies the bus as the master, the value set to the broadcasting request bit (ALLRQ) of the bus control register (BCR) is output. (3) Master address field The master address field is output by the master to inform a slave of the master's address. The configuration of the master address field is as shown in Figure 20-2. If two or more units start transmitting the broadcasting bit at the same time, the master address field makes a judgment of arbitration. The master address field compares the data it outputs with the data on the bus each time it has output one bit. If the master address output by the master address field is found to be different from the data on the bus as a result of comparison, it is assumed that the master has lost in arbitration. As a result, the master stops transmission and enters the reception status. Because the IEBus is configured of wired AND, the unit having the minimum master address of the units participating in arbitration (arbitration masters) wins in arbitration. After a 12-bit master address has been output, only one unit remains in the transmission status as one master unit. Next, this master unit outputs a parity bit, determines the master address of other unit, and starts outputting a slave address field. If one unit occupies the bus as the master, the address set by the unit address register (UAR) is output. Figure 20-2. Master Address Field
Master address field Master address (12 bits) MSB LSB Parity
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(4) Slave address field The master outputs the address of the unit with which it is to communicate. Figure 20-3 shows the configuration of the slave address field. A parity bit is output after a 12-bit slave address has been transmitted in order to prevent a wrong slave address from being received by mistake. Next, the master unit detects an acknowledge signal from the slave unit to confirm that the slave unit exists on the bus. When the master has detected the acknowledge signal, it starts outputting the control field. During broadcasting communication, however, the master does not detect the acknowledge bit but starts outputting the control field. The slave unit outputs the acknowledge signal if its slave address coincides and if the slave detects that the parities of both the master address and slave address are even. The slave unit judges that the master address or slave address has not been correctly received and does not output the acknowledge signal if the parities are odd. At this time, the master unit is in the standby (monitor) status, and communication ends. During broadcasting communication, the slave address is used to identify group-unit broadcasting or all-unit broadcasting, as follows: If slave address is FFFH: If slave address is other than FFFH: All-unit broadcasting communication Group-unit broadcasting communication
Remark The group No. during group-unit broadcasting communication is the value of the high-order 4 bits of the slave address. If one unit occupies the bus as the master, the address set by the slave address register (SAR) is output. Figure 20-3. Slave Address Field
Slave address field Slave address (12 bits) Group No. MSB Unit No. LSB Parity ACK
(5) Control field The master outputs the operation it requires the slave to perform, by using this field. The configuration of the control field is as shown in Figure 20-4. If the parity following the control bit is even and if the slave unit can execute the function required by the master unit, the slave unit outputs an acknowledge signal and starts outputting the telegraph length field. If the slave unit cannot execute the function required by the master unit even if the parity is even, or if the parity is odd, the slave unit does not output the acknowledge signal, and returns to the standby (monitor) status. The master unit starts outputting the telegraph field after confirming the acknowledge signal. If the master cannot confirm the acknowledge signal, the master unit enters the standby status, and communication ends. During broadcasting communication, however, the master unit does not confirm the acknowledge signal, and starts outputting the telegraph length field. Table 20-2 shows the contents of the control bits.
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Table 20-2. Contents of Control Bits
Bit 3Note 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reads slave status Undefined Undefined Reads data and locksNote 2 Reads lock address (low-order 8 bits)Note 3 Reads lock address (high-order 4 bits)Note 3 Reads slave status and unlocksNote 2 Reads data Undefined Undefined Writes command and locksNote 2 Writes data and locksNote 2 Undefined Undefined Writes command Writes data Function
Notes 1. The telegraph length bit of the telegraph length field and data transfer direction of the data field change as follows depending on the value of bit 3 (MSB). If bit 3 is `1': Transfer from master unit to slave unit If bit 3 is `0': Transfer from slave unit to master unit 2. This is a control bit that specifies locking or unlocking (refer to 20.1.7 (4) Locking and unlocking). 3. The lock address is transmitted in 1-byte (8-bit) units and is configured as follows:
MSB Control bit: 4H Low-order 8 bits LSB
Control bit: 5H
Undefined
High-order 4 bits
If the control bit received from the master unit is not as shown in Table 20-3, the unit locked by the master unit rejects accepting the control bit, and does not output the acknowledge bit.
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Table 20-3. Control Field for Locked Slave Unit
Bit 3 0 0 0 Bit 2 0 1 0 Bit 1 0 0 0 Bit 0 0 0 1 Reads slave status Reads lock address (low-order 8 bits) Reads lock address (high-order 4 bits) Function
If the unlocked unit receives the control data shown in Table 20-4, the unit rejects accepting the control data and does not output the acknowledge bit. Table 20-4. Control Field for Unlocked Slave Unit
Bit 3 0 0 Bit 2 1 1 Bit 1 0 0 Bit 0 0 1 Function Interrupts lock address (low-order 8 bits) Interrupts lock address (high-order 4 bits)
If one unit occupies the bus as the master, the value set to the control data register (CDR) is output. Figure 20-4. Control Field
Control field Control bit (4 bits) MSB LSB Parity ACK
(6) Telegraph length field This field is output by the transmission side to inform the reception side of the number of bytes of the transmit data. The configuration of the telegraph length field is as shown in Figure 20-5. Table 20-5 shows the relation between the telegraph length bit and the number of transmit data. Figure 20-5. Telegraph Length Field
Telegraph length field Telegraph length bit (8 bits) MSB LSB Parity ACK
Table 20-5. Contents of Telegraph Length Bit
Telegraph Length Bit (Hex) 01H 02H | FFH 00H Number of Transmit Data Bytes 1 byte 2 bytes | 255 bytes 256 bytes
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The operation of the telegraph length field differs depending on whether the master transmits (when control bit 3 is 1) or receives (when control bit 3 is 0) data. <1> When master transmits data The telegraph length bit and parity bit are output by the master unit. When the slave unit detects that the parity is even, it outputs the acknowledge signal, and starts outputting the data field. communication, however, the slave unit does not output the acknowledge signal. If the parity is odd, the slave unit judges that the telegraph length bit has not been correctly received, does not output the acknowledge signal, and returns to the standby (monitor) status. At this time, the master unit also returns to the standby status, and communication ends. <2> When master receives data The telegraph length bit and parity bit are output by the slave unit. If the master unit detects that the parity bit is even, it outputs the acknowledge signal. If the parity bit is odd, the master unit judges that the telegraph length bit has not been correctly received, does not output the acknowledge signal, and returns to the standby status. At this time, the slave unit also returns to the standby status, and communication ends. (7) Data field This is data output by the transmission side. The master unit transmits or receives data to or from a slave unit by using the data field. The configuration of the data field is as shown in Figure 20-6. Figure 20-6. Data Field
Data field (number specified by telegraph length field) One data Control bit (8 bits) MSB LSB Parity ACK Parity ACK
During broadcasting
Following the data bit, the parity bit and acknowledge bit are respectively output by the master unit and slave unit. Broadcasting communication is used only when the master unit transmits data. At this time, the acknowledge bit is ignored.
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The operation differs as follows depending on whether the master transmits or receives data. <1> When master transmits data When the master units writes data to a slave unit, the master unit transmits the data bit and parity bit to the slave unit. If the parity is even and receive data is not stored in the data register (DR) when the slave unit receives the data bit and parity bit, the slave unit outputs an acknowledge signal. If the parity is odd or if receive data is stored in the DR, the slave unit rejects receiving the data, and does not output the acknowledge signal. If the slave unit does not output the acknowledge signal, the master unit transmits the same data again. This operation continues until the master detects the acknowledge signal from the slave unit, or the data exceeds the maximum number of transmit bytes. If the data is continuous and the maximum number of transmit bytes is not exceeded when the parity is even and when the slave unit outputs the acknowledge signal, the master unit transmits the next data. During broadcast communication, the slave unit does not output the acknowledge signal, and the master unit transfers 1 byte of data at a time. During broadcast communication, the slave unit receives the data and parity bits, and if the parity is odd or receive data is stored in the DR, reception is considered not to have been performed correctly and is stopped. <2> When master receives data When the master unit reads data from a slave unit, the master unit outputs a sync signal corresponding to all the read bits. The slave unit outputs the contents of the data and parity bits to the bus in response to the sync signal from the master unit. The master unit reads the data and parity bits output by the slave unit, and checks the parity. If the parity is odd or the DR is receiving data, the master unit refuses to acknowledge this data and does not output the acknowledge signal. If the maximum number of transmit bytes is a value within the range that can be transmitted in one communication frame, the master unit repeats reading the same data. If the parity is even and the DR is not receiving data, the master unit accepts the data and returns the acknowledge signal. If the maximum number of transmit bytes is within the value that can be transmitted in one frame, the master unit reads the next data. (8) Parity bit The parity bit is used to confirm that the transmit data has no error. The parity bit is appended to each data of the master address, slave address, control, telegraph length, and data bits. The parity is an even parity. If the number of bits in the data that are `1' is odd, the parity bit is `1'. If the number of bits in the data that are `1' is even, the parity bit is `0'. (9) Acknowledge bit During normal communication (communication from one unit to another), an acknowledge bit is appended to the following locations to confirm that the data has been correctly received. * End of slave address field * End of control field * End of telegraph length field * End of data field The definition of the acknowledge bit is as follows: * `0': Indicates that the transmit data is recognized (ACK). * `1': Indicates that the transmit data is not recognized (NACK).
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During broadcast communication, however, the content of the acknowledge bit is ignored. <1> Last acknowledge bit of slave address field The last acknowledge bit of the slave address field serves as NACK in any of the following cases, and transmission is stopped. * If the parity of the master address bit or slave address bit is incorrect * If a timing error (error in bit format) occurs * If a slave unit does not exist <2> Last acknowledge bit of control field The last acknowledge bit of the control field serves as NACK in any of the following cases, and transmission is stopped. * If the parity of the control bit is incorrect * When control bit 3 is "1" (write operation) when the slave receive enable flag (ENSLVRX)Note is not set * When control bits for which ENSLVRXNote is not set are data read (3H, 7H) * If control bits 3H, 6H, 7H, AH, BH, EH, or FH are requested from a unit other than one for which lock has been set * If the control bit indicates reading of a lock address (4H or 5H) even when locking is not set * If a timing error occurs * If the control bit is undefined Note Bit 3 of the bus control register (BCR) Cautions 1. When the slave status request control data is received even if the slave transmit enable flag (ENSLVTX) is not set, ACK is always returned. 2. When data/command write control data is received even when the slave receive enable flag (ENSLVRX) is not set, the control field acknowledge bit returns NACK. Prohibiting receive operations (stopping communication) using ENSLVRX is limited to individual sommunication. In the case of broadcast communication, communication continues until a data request interrupt (INTIE1) or end interrupt (INTIE2) is generated. <3> Last acknowledge bit of telegraph length field The last acknowledge bit of the telegraph length field serves as NACK in any of the following cases, and transmission is stopped. * If the parity of the telegraph length bit is incorrect * If a timing error occurs <4> Last acknowledge bit of data field The last acknowledge bit of the data field serves as NACK in any of the following cases, and transmission is stopped. * If the parity of the data bit is incorrectNote * If a timing error occurs after the preceding acknowledge bit has been transmitted * When receive data is stored in the data register (DR), and no more data can be acceptedNote. Note In this case, for the individual communication, if the maximum number of transmission bytes is a value within the range that can be transmitted in one frame, the transmission side performs transmission of that data field again. In the case of broadcast communication, the transmission side does not perform transmission of that data field again, and a transmission error occurs on the receiving side and reception is stopped.
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20.1.7 Transmit data (1) Slave status The master unit can learn why the slave unit did not return the acknowledge bit (ACK), by reading the slave status. The slave status is determined depending on the result of the last communication the slave unit has executed. All the slave units can supply information on the slave status. Table 20-6 shows the meaning of the slave status. Figure 20-7. Bit Configuration of Slave Status
MSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB
Table 20-6. Meaning of Slave Status
Bit Bit 0 Note 1 Value 0 1 Bit 1 Note 2 0 1 Bit 2 0 1 Bit 3 Bit 4 Note 3 0 0 1 Bit 5 Bit 7 Bit 6 0 00 01 10 11 Meaning Transmit data is not written to data register (DR) Transmit data is written to DR Receive data is not saved to DR Receive data is saved to DR Unit is not locked Unit is locked Fixed to `0' Slave transmission is stopped Slave transmission is ready Fixed to `0' Mode 0 Mode 1 Mode 2 Not used Indicates highest mode supported by unitNote 4
Notes 1. The value of this buffer of the PD784938 Subseries is initialized to 1 at reset. 2. The receive buffer of the PD784938 Subseries has a capacity of 1 byte. 3. When the PD784938 Subseries serves as a slave unit, this bit corresponds to the status indicated by bit 4 (ENSLVTX) of the bus control register (BCR). 4. When the PD784938 Subseries serves as a slave unit, bits 7 and 6 are fixed to `0' and `1' (mode 1), respectively.
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(2) Lock address When the lock address is read (control bit: 4H or 5H), the address (12 bits) of the master unit that has issued the lock instruction is configured in 1-byte units as shown below and read. Figure 20-8. Configuration of Lock Address
MSB Control bit: 4H Low-order 8 bits LSB
Control bit: 5H
Undefined
High-order 4 bits
(3) Data If the control bit indicates reading of data (3H or 7H), the data in the data buffer of the slave unit is read by the master unit. If the control bit indicates writing of data (BH or FH), the data received by the slave unit is processed according to the operation rule of that slave unit. (4) Locking and unlocking The lock function is used when a message is transferred in two or more communication frames. The unit that is locked does not receive data from units other than the one that has locked the unit. A unit is locked or unlocked as follows: <1> Locking If the communication frame is completed without succeeding in transmission or reception of the data of the number of bytes specified by the telegraph length bit after the acknowledge bit `0' of the telegraph length field has been transmitted or received by the control bit that specifies locking (3H, AH, or BH), the slave unit is locked by the master unit. At this time, the bit (bit 2) in the byte indicating the slave status is set to `1'. <2> Unlocking After transmitting or receiving data of the number of data bytes specified by the telegraph length bit in one communication frame by the control bit that has specified locking (3H, AH, or BH), or the control bit that has specified unlocking (6H), the slave unit is unlocked by the master unit. At this time, the bit related to locking (bit 2) in the byte indicating the slave status is reset to `0'. Locking or unlocking is not performed during broadcasting communication.
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20.1.8 Bit format Figure 20-9 shows the format of the bits constituting the communication frame of the IEBus. Figure 20-9. Bit Format of IEBus
Logic "1" Logic "0" Preparation period Synchronization Data period period Stop period
Preparation period: Data period: Stop period:
First low-level (logic "1") period Period indicating value of bit Last low-level (logic "1") period
Synchronization period: Next high-level (logic "0") period
The synchronization period and data period are almost equal to each other in length. The IEBus synchronizes each 1 bit. The specifications on the time of the entire bit and the time related to the period allocated to that bit differ depending on the type of the transmit bit, or whether the unit is the master unit or a slave unit.
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20.2 Simple IEBus Controller The PD784938 has a newly developed IEBus controller. The functions of this IEBus controller are limited as compared with the IEBus interface functions of the existing models (provided to the 78K/0 Series). Table 20-7 compares the IEBus interface functions of the existing models with the simple IEBus interface functions of the PD784938 Subseries. Table 20-7. Comparison between Existing and Simple IEBus Interface Functions
Item Communication mode Internal system clock Internal buffer size Existing Function (IEBus of 78K/0) Modes 0, 1, and 2 6.0 (6.29) MHz Transmit buffer: 33 bytes (FIFO) Receive buffer: 40 bytes (FIFO) Up to 4 frames can be received. CPU processing Communication start preprocessing (data setting) Setting and management of each communication status Writing data to transmit buffer Reading data from receive buffer Communication start preprocessing (data setting) Setting and management of each communication status 1-byte data write processing 1-byte data read processing Management of transmission such as slave status Management of plural frames, master request reprocessing Hardware processing Bit processing (modulation/demodulation, error detection) Field processing (generation/management) Arbitration result detection Parity processing (generation/error detection) Automatic return of ACK/NACK Automatic data re-processing Automatic master re-processing
Note
Simple IEBus Fixed to mode 1
Transmit/receive data register
Bit processing (modulation/demodulation, error detection) Field processing (generation/management) Arbitration result detection Parity processing (generation/error detection) Automatic return of ACK/NACK Automatic data transmission re-processing
Transmission processing such as automatic slave status transmission Plural-frame reception processing
Note Automatic master re-processing: After generating the master request, if the master request is cancelled by arbitration, etc., the bus is released and automatically re-issue the master request.
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20.3 IEBus Controller Configuration Figure 20-10 shows the block diagram of the IEBus controller. Figure 20-10. IEBus Controller Block Diagram
CPU interface block 8 12 Internal BCR (8) UAR (12) registers 8 12 12 SAR (12) 12 12 PAR (12) 12 8 CDR (8) 8 8 DLR (8) 8 8 8 8 8 8 8
DR (8) USR (8) 8 8
ISR (8) SSR (8) SCR (8) CCR (8) 8 8 8 8
Internal bus 8 8 RX NF MPX TX/RX PSR (8 bits) 12-bit latch Comparator Contention detection Interrupt control circuit Interrupt control block INT request (vector, macro service) 12
TX
MPX
Parity generation error detection
ACK generation IEBus interface block
CLK
5 Internal bus R/W
Bit processing block
Field processing block
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*
Hardware configuration and function The IEBus mainly consists of the following six internal blocks. * CPU interface block * Interrupt control block * Internal registers * Bit processing block * Field processing block * IEBus interface block This is a control block that interfaces between the CPU (78K/IV) and IEBus. This control block transfers interrupt request signals from the IEBus to the CPU. These registers set data to the control registers and fields that control the IEBus (for the internal registers, refer to 20.4 Internal Registers of IEBus Controller). This block generates and disassembles bit timing, and mainly consists of a bit sequence ROM, 8-bit preset timer, and comparator. This block generates each field in the communication frame, and mainly consists of a field sequence ROM, 4-bit down counter, and comparator. This is the interface block for an external driver/receiver, and mainly consists of a noise filter, shift register, collision detector, parity detector, parity generation circuit, and ACK/NACK generation circuit.
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20.4 Internal Registers of IEBus Controller The IEBus controller consists of the following registers: 20.4.1 Internal register list Table 20-8 lists the internal registers of the IEBus controller. Table 20-8. Internal Registers of IEBus Controller
Address IEBus Register Name Symbol R/W Bit Units for Manipulation 1 bit 0FFB0H 0FFB2H 0FFB4H 0FFB6H 0FFB8H 0FFB9H 0FFBAH 0FFBBH 0FFBCH 0FFBDH 0FFBEH 0FFBFH Bus control register Unit address register Slave address register Partner address register Control data register Telegraph length register Data register Unit status register Interrupt status register Slave status register Communication success counter Transmit counter BCR UAR SAR PAR CDR DLR DR USR ISR SSR SCR CCR R R/W R R R/W R/W -- -- -- -- -- -- -- -- 8 bits -- -- -- 16 bits -- -- -- -- -- -- -- -- -- 41H 01H 20H 00H 01H 00H 0000H Initial Value
Cautions 1. The above registers are mapped to the SFR space. 2. Registers UAR, SAR, and PAR must be manipulated in word units. 3. Instructions in Read Modify Write mode (such as XCH and ROL4) cannot be used for DR, CDR, DLR, and ISR.
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20.4.2 Description of internal registers Each internal register of the IEBus controller is explained below. (1) Bus control register (BCR) Figure 20-11. Bus Control Register (BCR) Format
7 6 5 4 3 2 0 1 0 0 0 Address After reset R/W 0FFB0H 00H R/W
BCR ENIEBUS MSTRQ ALLRQ ENSLVTX ENSLVRX
ENSLVRX
Slave Reception Enable Flag Slave reception disabled Slave reception enabled Slave Transmission Enable Flag Slave transmission disabled Slave transmission enabled Broadcasting Request Flag Requests individual communication Requests broadcasting communication Master Request Flag Does not request IEBus unit as master Requests IEBus unit as master Communication Enable Flag Stops IEBus unit Makes IEBus unit active
0 1
ENSLVTX
0 1 ALLRQ 0 1 MSTRQ 0 1 ENIEBUS 0 1
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* Communication enable flag (ENIEBUS) ... Bit 7 [Set/reset condition] Set: Through software manipulation Reset: Through software manipulation Caution Before setting this flag, the following registers for communication must be set.
During master transmission During master reception During slave transmission During slave reception UAR
* Master request flag (MSTRQ) ... Bit 6 [Set/reset condition] Set: Through software manipulation Reset: Through hardware at the end of the arbitration period Caution Make a remaster request through software processing in case the unit loses in contention. * Broadcasting request flag (ALLRQ) ... Bit 5 [Set/reset condition] Set: Through software manipulation Reset: Through software manipulation Caution Be sure to set this flag to request broadcasting communication, and set bit 6. * Slave transmission enable flag (ENSLVTX) ... Bit 4 [Set/reset condition] Set: Through software manipulation Reset: Through software manipulation Cautions 1. Clear this flag before setting the master request flag during master request. If a slave transmission request is made by the master with this flag not set during slave, or if the disabled status is to be returned to the enabled status, the next new frame and those that follow become valid. 2. When ENSLVTX is not set, upon reception of data/command write control data "3H, 7H", the acknowledge bit of the control field returns NACK. 3. Even if ENSLVTX has been reset, when slave status request control data is returned, a status interrupt (INTIE2) is generated and communication is continued. * Slave reception enable flag (ENSLVRX) ... Bit 3 [Set/reset condition] Set: Through software manipulation Reset: Through software manipulation
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Caution When the CPU is busy with other processing, slave reception can be disabled by resetting this flag and returning NACK with the acknowledge bit of the control field. Therefore, when this flag is reset, individual communication can be disabled, but broadcasting communication cannot. Furthermore, during individual communication, start interrupt (INTIE2) is generated. When CPU processing is prioritized (in case neither reception nor transmission are to be performed), reset ENIEBUS (communication enable flag) and stop the IEBus unit. Also, when returning to the enabled status from the disabled status, the operation becomes effective from the next new frame. (2) Unit address register (UAR) This register sets the unit address of an IEBus unit. This register must be always set before starting communication. Figure 20-12. Unit Address Register (UAR) Format
15 14 13 12 11 10 UAR 0 0 0 0 9 8 7 6 5 4 3 2 1 0 Address After reset R/W 0FFB2H 0000H R/W
Sets unit address (12 bits)
(3) Slave address register (SAR) During master request, the value of this register is reflected on the value of the transmit data in the slave address field. This register must be always set before starting communication. Figure 20-13. Slave Address Register (SAR) Format
15 14 13 12 11 10 SAR 0 0 0 0 9 8 7 6 5 4 3 2 1 0 Address After reset R/W 0FFB4H 0000H R/W
Sets slave address (12 bits)
(4) Partner address register (PAR) [During slave unit] The value of the receive data in the master address field (address of the master unit) is written to this register. If a request "4H" to read the lock address (low-order 8 bits) is received from the master, the CPU must read the value of this register, and write the data of the low-order 8 bits to the data register (DR). If a request "5H" to read the lock address (high-order 4 bits) is received from the master, the CPU must read the value of this register and write the data of the high-order 4 bits to DR. Figure 20-14. Partner Address Register (PAR) Format
15 14 13 12 11 10 PAR 0 0 0 0 9 8 7 6 5 4 3 2 1 0 Address After reset R/W 0FFB6H 0000H R
Sets partner address (12 bits)
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(5) Control data register (CDR) [During master unit] The data of the low-order 4 bits is reflected on the data transmitted in the control field. During master request, this register must be set in advance before starting communication. [During slave unit] The data received in the control field is written to the low-order 4 bits. When the status transmission flag (STATUS) is set, an interrupt (INTIE2) is issued, and each processing should be performed by software, according to the value of the low-order 4 bits of this register. Figure 20-15. Control Data Register (CDR) Format
7 CDR 0 6 0 5 0 4 0 3 2 1 0 Address After reset R/W 01H R/W
MOD SELCL2 SELCL1 SELCL0 0FFB8H
MOD SELCL2 SELCL1 SELCL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reads slave status Undefined Undefined
Function
Reads data and locks Reads lock address (low-order 8 bits) Reads lock address (low-order 4 bits) Reads slave status and unlocks Reads data Undefined Undefined Writes command and locks Writes data and locks Undefined Undefined Writes command Writes data
Cautions 1. Because the slave unit must judge whether the received data is a "command" or "data", it must read the value of this register after completing communication. 2. The Read Modify Write instruction (such as XCH and ROL4) cannot be used for CDR. 3. If the master unit sets an undefined value, NACK is returned from the slave unit, and communication is aborted. During broadcasting communication, however, the master unit continues communication without recognizing ACK/NACK; therefore, make sure not to set an undefined value to this register during broadcasting communication. 4. In the case of defeat in a bus conflict and a slave status request is received from the unit that won, telegraph length register (DLR) is fixed to "01H". Therefore, in a re-request of the master follows, the appointed telegraph length must be set to DLR.
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[Slave status response operation] The ACK response operation of the control field differs depending on the status of slave side when a slave status request (control data: "0H, 6H") and a lock address request "4H, 5H" are received. <1> In unlocked status, when "0H, 6H" control data is received <2> In unlocked status, when "4H, 5H" control data is received <3> In locked status, when "0H, 4H, 5H, 6H" control data is received from the request unit <4> In locked status, when "0H, 4H, 5H" control data is received from an address other than the request unit <5> In locked status, when "6H" control data is received from an address other than the request unit Return ACK Return ACK Return ACK Don't return ACK Return ACK
In all cases from <1> to <5>, the status transmission flag (bit 4 of the interrupt status register (ISR)) is set upon reception of the slave status and lock address request, and the status interrupt request (INTIE2) is generated. The generation timing is the end of the control field parity bit (start of the ACK bit). However, if ACK communication is not performed, an NACK error occurs at the end of the ACK bit and communication is stopped. Figure 20-16. Interrupt Generation Timing (in case of <1>, <3>, <4>)
IEBus sequence Control bits (4 bits) Parity bit (1 bit) ACK bit (1 bit) End with communication error
INTIE2
Status transmission flag Internal NACK flag
Flag is set upon reception of "0H, 4H, 5H, 6H"
Flag is reset with CPU processing
Figure 20-17. Interrupt Generation Timing (in case of <2>, <5>)
IEBus sequence Control bits (4 bits) Parity bit (1 bit) ACK bit (1 bit) End with communication error
INTIE2 Flag is reset with CPU processing
Status transmission flag Internal NACK flag
Flag is set upon reception of "0H, 4H, 5H, 6H"
Error is set upon NACK detection
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In the case of <4> and <5>, communication is performed from other than lock request in the locked status, so that even if the unit address is the target of the communication, no start interrupt or communication end interrupt (INTIE2) is generated. However, if a slave status, lock address request is received, the status transmission flag (bit 4 of interrupt status register (ISR)) is set, and a status interrupt request (INTIE2) is generated. In this way, even if the same control data is received in the locked status, the INTIE2 generation timing differs depending on whether the master side is the lock request address (<3>) or it is a different address. Figure 20-18. INTIE2 Interrupt Generation Timing in Locked Status (in case of <4>, <5>)
IEBus sequence Start Broadcasting Master address (12 + A) Slave address (12 + P + A) Control (4 + P + A) Telegraph Data length (8 + P + A) (8 + P + A)
INTIE2
Status interrupt
Figure 20-19. INTIE2 Interrupt Generation Timing in Locked Status (in case of <3>)
IEBus sequence Start Broadcasting Master address (12 + P) Slave address (12 + P + A) Control (4 + P + A) Telegraph Data length (8 + P + A) (8 + P + A) Communication end interrupt
INTIE2
Start interrupt
Status interrupt
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(6) Telegraph length register (DLR) [During transmission unit] ... Master transmission, slave transmission The data of this register is reflected on the data transmitted in the telegraph length field and indicates the number of bytes of the transmit data. This register must be set in advance before transmission. [During reception unit] ... Master reception, slave reception The receive data in the telegraph length field transmitted from the transmission unit is written to this register. Figure 20-20. Telegraph Length Register (DLR) Format
7 DLR 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Address After reset R/W 0FFB9H 01H R/W
Remaining Number of Communication Data Bytes 01H 02H 1 byte 2 bytes
20H
32 bytes
FFH 00H
255 bytes 256 bytes
Cautions 1. If the master issues a request "0H, 4H, 5H, or 6H" to transmit a slave status and lock address (high-order 4 bits, low-order 8 bits), the contents of this register are set to "01H" by hardware; therefore, the CPU does not have to set this register. An instruction of Read Modify Write mode (such as XCH and ROL4) cannot be used for DLR. 2. In the case of defeat in a bus conflict and a slave status request is received from the unit that won, DLR is fixed to "01H". Therefore, if a re-request of the master follows, the appointed telegraph length must be set to DLR.
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(7) Data register (DR) [During transmission unit] The data (1 byte) written to the data register (DR) is stored to the internal shift register of the IEBus. It is then output from the most significant bit, and an interrupt (INTIE1) is issued to the CPU each time 1 byte has been transmitted. INTIE is generated at the timing of the data register (DR) value stored in the internal shift register of the IEBus. However, INTIE1 is not generated when the last byte and the 32nd byte (last byte of one communication frame) is delivered to the internal register. [During reception unit] One byte of the data received by the internal shift register of the IEBus is stored to this register. Each time 1 byte has been correctly received, an interrupt (INTIE1) is issued. Figure 20-21. Data Register (DR) Format
7 DR 6 5 4 3 2 1 0 Address After reset R/W 0FFBAH 00H R/W
Sets communication data (8 bits)
Caution If the next data is not in time while the transmission unit is set, an underrun occurs, and a communication error interrupt (INTIE2) occurs. An instruction of Read Modify Write mode (such as XCH and ROL4) cannot be used for DR.
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(8) Unit status register (USR) Figure 20-22. Unit Status Register (USR) Format
7 USR 0 6 5 4 3 2 LOCK 1 0 0 0 Address 0FFBBH After reset 00H R/W R
SLVRQ ARBIT ALLTRNS ACK
LOCK 0 1 ACK 0 1 ALLTRNS 0 1 ARBIT 0 1 SLVRQ 0 1
Lock Status Flag Non-lock status Lock status ACK Transmission Flag Transmits NACK Transmits ACK Broadcasting Communication Flag Individual communication status Broadcasting communication status Contention Flag Wins in contention Loses in contention Slave Request Flag No slave request Slave request
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* Slave request flag (SLVRQ) ... Bit 6 This flag indicates whether the master has issued a slave request. * Contention flag (ARBIT) ... Bit 5 This flag indicates the result of contention. [Set/reset condition] Set: Reset: Set if the data output by a unit does not coincide with the data on the bus line during the arbitration period after the master request has been made. Cleared at start bit timing
* Broadcasting communication flag (ALLTRANS)... Bit 4 This flag indicates if the unit is performing broadcasting communication. The contents of the flag are initialized upon detection of the start bit of each frame, and updated to the broadcasting field. The set/bit conditions change depending on the broadcasting field bit reception data at all times except initialization (reset) through system reset. [Set/reset condition] Set: Reset: Upon reception of "broadcasting" in broadcasting field Upon reception of "individual" in broadcasting field, or upon input of system reset.
Caution Update of the broadcasting communication flag is performed regardless of whether or not the communication target is the unit address. Figure 20-23. Broadcasting Communication Flag Operation Example
IEBus sequence
Start
Broadcasting M11
M10
Start
Broadcasting
M11
M10
INTIE2
Set
No reset with start bit
Reset
* ACK transmission flag (ACK) ... Bit 3 This flag indicates whether ACK is transmitted during the ACK period of each field while the unit serves as a reception unit. The content of the flag is updated during the ACK period of each frame. If the internal circuit is initialized due to the occurrence of a parity error, the content of the flag cannot be updated during the ACK period of the field. * Lock status flag (LOCK) ... Bit 2 This flag indicates whether the unit is locked. [Set/reset condition] Set: Reset: Set if lock specifications "3H, 6H, AH, and BH" are received in the control field, and if the communication end flag is "L" and frame end flag is "H". If the communication enable flag is cleared. If unlocking commands "3H, 6H, AH, and BH" are received by the control field and the communication end flag is set. Caution Locking or unlocking is not performed during broadcasting communication.
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(9) Interrupt status register (ISR) This status register indicates the status when an interrupt of the IEBus is issued. User must read this register and perform the subsequent processing each time an interrupt has been generated. Clear the contents of the following communication error flag (IEERR), start interrupt flag (START), and status transmission flag (STATUS) through software manipulation in vector interrupt processing. Also be sure to check and clear the contents of the communication end flag (ENDTRANS) and frame end flag (ENDFRAM) through software manipulation. Figure 20-24. Interrupt Status Register (ISR) Format
7 ISR 0 6 5 4 3 2 1 0 0 0 Address 0FFBCH After reset 00H R/W R/W
IEERR START STATUS ENDTRNS ENDFRAM
ENDFRAM 0 1 ENDTRNS 0 1 STATUS 0 1 START 0 1
Frame End Flag Frame does not end Frame ends Communication End Flag Communication does not end Communication ends Status Transmission Flag No status transmission request Status transmission request Start Interrupt Flag Interrupt after ACK period of slave address field Interrupt during ACK period of slave address field Communication Error Flag No communication error Communication error occurs
IEERR 0 1
Remark Reset of IEER, STARTF, and STATUSF flags is performed by writing a byte in to the interrupt status register (ISR).
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* Communication error flag (IEERR) ... Bit 6 This flag detects an error during communication. [Set/reset condition] Set: Reset: Set if a timing error, parity error (except the data field), NACK reception (except the data field), or underrun occurs Through software manipulation
* Start interrupt flag (START) ... Bit 5 This flag indicates the interrupt during the ACK period of the slave address field. [Set/reset condition] Set: Set in the slave address field during the master request. Set if there was a slave request from the master. (In the case of lock status, only if there was a slave request from the lock request unit.) Reset: Through software manipulation
* Status transmission flag (STATUS) ... Bit 4 This flag indicates that the master transmits a slave status or lock address (high-order 4 bits, low-order 8 bits) while the unit serves as a slave. [Set/reset condition] Set: Reset: Set when "0H, 4H, 5H, or 6H" is received from the master in the control field while the unit serves as a slave. Through software manipulation
* Communication end flag (ENDTRNS) ... Bit 3 This flag indicates whether communication has been completed by the number of transmit bytes set by the telegraph length field. [Set/reset condition] Set: Reset: When the count value of the SCR counter has reached 0. When any of the master request flag, slave transmission enable flag, or slave reception enable flag is set. * Frame end flag (ENDFRAM) ... Bit 2 This flag indicates whether communication of the maximum number of transmit bytes (32 bytes) specified by each communication mode is completed. [Set/reset condition] Set: Reset: When the count value of the CCR has reached 0. When any of the master request fag, slave transmission enable flag, or slave reception enable flag is set
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[Description of communication error source] Condition of occurrence: Remark: If the high-/low-level width of the communication bit exceeds or falls below a rated value. Each rated value is set by the bit processing block and is monitored by the internal 8-bit timer. If a timing error occurs, an interrupt is issued. Condition of occurrence: Remark: If the generated parity and received parity do not coincide in each field while the unit serves as a receive unit. During individual communication, if a parity error occurs in other than the data field, an interrupt is issued. During broadcasting communication, even if a parity error occurs in the data field, an interrupt is issued. Limitations: If a broadcasting communication request is performed and a slave request defeated in contention occurs, no interrupt is generated even if a parity error occurs in the data field. Condition of occurrence: Remark: Condition of occurrence: Remark: Condition of occurrence: When the unit is used as a receive unit, a data interrupt request (INTIE1), which stores data one byte at a time in the data register (DR), is generated, and the CPU performs DR read processing. If this read processing is late and the next data receive timing starts, an overrun error occurs. Remark: When the unit is used for individual communication reception, no acknowledge is returned during the ACK period of the next data. Through this, the transmission unit performs retransmission of the data. Therefore, the communication count register (CCR) is decremented, but the success count register (SCR) is not decremented. When the unit is used for broadcast communication reception, a communication error interrupt request (INTIE2) occurs, and reception is stopped. At this time, DR is not updated. Moreover, no INTIE1 is generated, and the DR reception status flag (bit 1 of the timer mode control register (SSR)) is set (to 1) and maintained. The overrun status is canceled using the data reception timing following DR read. If the data that is to be transmitted next to the data register (DR) until ACK is received is not written in time during data transmission. If underrun occurs, an interrupt is issued. If NACK is received during the ACK period in the slave address, control, or telegraph length field while the unit serves as a receive transmit unit. If NACK is received (transmitted) in other than the data field, an interrupt is issued.
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[Supplementary explanation of overrun error] (1) If overrun occurs during individual communication reception, resulting in frame end If DR read is not performed following the overrun status and data retransmission reaches the maximum number of data transfer bytes (32 bytes), a frame end interrupt (INTIE2) occurs. The overrun status is maintained until DR read is performed even after frame end. (2) If the next reception starts in the case of (1) above, or if the next transmission starts without DR read being performed, following reception of the last data, regardless of whether it is broadcasting or individual communication Even if communication is started to one's own address in the overrun status, an overrun caused NACK return does not occur during the ACK period in each of the slave address, control, and telegraph length fields. However, when DR read is not performed until data reception completion in the data field, no acknowledge is returned and reception is not performed (DR update is not performed). If the next communication is not directed to one's own address, DR is not updated until DR read is performed. Since the communication is not directed at one's own address, data interrupt (INTIE1) or communication error interrupt (INTIE2) is not generated.
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(10) Slave status register (SSR) This register indicates the communication status of the slave unit. After receiving a slave status transmission request from the master, the CPU reads this register, and writes a slave status to the data register (DR) to transmit the slave status. At this time, the telegraph length is automatically set to "01H" that setting of telegraph length register (DLR) is not required (because it is preset by hardware). Figure 20-25. Slave Status Register (SSR) Format
7 SSR 0 6 1 5 0 4 STATSLV 3 0 2 1 0 Address 0FFBDH After reset 41H R/W R
STATLOCK STATRX STATTX
STATTX 0 1 STATRX 0 1 STATLOCK 0 1 STATSLV 0 1
DR Transmit Status Transmission data not stored in DR Transmission data stored in DR DR Receive Status Receiving data not stored in DR Receiving data stored in DR Lock Status Flag Unlock status Lock status Slave Transmission Enable Flag Slave transmission stops Slave transmission enabled
* Slave transmission status flag (STATSLV) ... Bit 4 Reflects the content of the slave transmission enable flag. * Lock status flag (STATLOCK) ... Bit 2 Reflects the content of the lock status flag. * DR receive status (STATRX) ... Bit 1 The flag that indicates the receive status of the DR. * DR transmit status (STATTX) ... Bit 0 The flag that indicates the transmit status of the DR. Bits 6 and 7 indicate the highest mode supported by the unit, and are fixed to "01H" (mode 1).
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(11) Success count register (SCR) This register reads the count value of the counter that decrements the value set by the telegraph length register by ACK in the data field. When the count value has reached "00H", the communication end flag (ENDTRNS) is set. Figure 20-26. Success Count Register (SCR) Format
7 SCR 6 5 4 3 2 1 0 Address After Reset R/W 0FFBEH 01H R
Remaining Number of Communication Data Bytes 01H 02H 1 byte 2 bytes
20H
32 bytes
FFH 00H
255 bytes 0 byte (end of communication) or 256 bytesNote
Note The bit length of the actual hard counter consists of 9 bits. When "00H" is read, it cannot be judged whether the remaining number of communication data bytes is 0 (end of communication) or 256. Therefore, either the communication end flag is used, or if "00H" is read when the first interrupt occurs at the beginning of communication, the remaining number of communication data bytes is judged to be 256. (12) Communication count register (CCR) This register reads the count value of the counter that is preset to the maximum number of transmitted bytes (32 bytes) per frame specified in mode 1 and is decremented during the ACK period of the data field regardless of ACK/NACK. When the count value has reached "00H", the frame end flag (ENDFRAM) is set. Figure 20-27. Communication Count Register (CCR) Format
7 CCR 6 5 4 3 2 1 0 Address After reset R/W 0FFBFH 20H R
Number of transmitted bytes
* Preset value in mode 1 and maximum number of transmitted bytes per frame ... 20H (32 bytes)
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20.5 Interrupt Operations of IEBus Controller 20.5.1 Interrupt control block 1. 2. 3. 4. 5. 6. 7. Communication error Start interrupt Status communication End of communication End of frame Transmit data write request Receive data read request (IEERR) (START) (STATUS) (ENDTRANS) (ENDFRAM) (STATTX) (STATRX)
1 through 5 of the above interrupt requests 1 are assigned to the interrupt status register (ISR). For details, refer to Table 20-9 Interrupt Requests. The configuration of the interrupt control block is illustrated below. Figure 20-28. Configuration of Interrupt Control Block
IEERR START STATUS ENDTRANS ENDFRAM STATTX STATRX INTIE1 INTIE2
IEBus macro
Interrupt control block
78K/IV CPU
Cautions 1. With regard to ORed output of STATTX, STATRX, faster processing is aimed for by using a macro service. 2. With regard to ORed output of IEERR, START, STATUS, ENDTRANS, ENDFRAM, check the interrupt generation source using vector interrupt processing.
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20.5.2 Interrupt source list The interrupt request signals of the internal IEBus controller in the 78K/IV Series can be classified into vector interrupts and macro service interrupts. These interrupt processing can be specified through software manipulation. The interrupt sources are listed below. Table 20-9. Interrupt Source List
Interrupt Source Condition of Generation Unit Communication error (Timing error) (Parity error) Master/slave Reception All fields Other than data (individual) All fields (broadcasting) (NACK reception) Transmission Other than data (individual) Data Data (broadcasting) Start interrupt Master Slave/address Slave request judgment Contention judgment (If loses, remaster processing) Communication preparation processing Slave Slave/address Slave request judgment Communication preparation processing Status transmission Slave Control Refer to transmission processing example such as slave status. Generated regardless of the slave transmission enable flag. Invalid if flag is disabled. End of communication Transmission Reception Data Data Macro service end processing Macro service end processing Receive data processing End of frame Transmission Data Retransmission preparation processing Reception Data Re-reception preparation processing Transmit data write Transmission Data None (processed by macro service) None (processed by macro service) Set after transfering of transmit data to internal shift register Set after normal data reception Set if CCR is cleared to 0 Set if CCR is cleared to 0 Set if SCR is cleared to 0 Set if CCR is cleared to 0 Generated only during slave request Interrupt always occurs if loses in contention during master request. Field CPU Processing after Generation of Interrupt Undo communication processing Communication error is OR output of timing error, parity error, NACK reception, underrun error, and overrun error. Remark
(Underrun error) (Overrun error)
Transmission Reception
Receive data read
Reception
Data
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20.6 Interrupt Generation Timing and Main CPU Processing 20.6.1 Master transmission
Approx. 624 s (mode 1) <1> Start
Broadcasting
6 Control P A
Telegraph length
M address P S address P
A
P
A
Data 1
Approx. 390 s (mode 1) 6 Data 1 P A Data 2 P A 6 6 Data n-1 P A 5 Data n P <2> A
n = Final number of data bytes
Caution
indicates that an interrupt (INTIE1) does not occur.
Initial preparation processing Sets a unit address, slave address, control data, telegraph length, and the first byte of the transmit data. Communication start processing Sets the bus control register (enables communication, master request, and slave reception). <1> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of slave request Judgment of contention result Remaster request processing Slave reception processingNote 1 Error processing
Interrupt (INTIE1) occurrenceNote 2 The transmit data of the second byte and those that follow are written to the data register (DR) by macro service. At this time, the data transfer direction is RAM (memory) SFR (peripheral) <2> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of end of communication Judgment of end of frame Re-communication processingNote 3 End of communication processing Error processing
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Notes 1. If a slave reception request is confirmed during vector interrupt processing, the data transfer direction of macro service must change from RAM (memory) SFR (peripheral) to SFR (peripheral) RAM (memory) until the first data is received. The maximum pending period of this data transfer direction changing processing is about 1,040 s in communication mode 1. 2. If NACK is received from the slave in the data field, an interrupt (INTIE1) is not issued to the CPU, but the same data is retransmitted by hardware. If the transmit data is not written during the period while the next data is being written, a communication error interrupt occurs due to the occurrence of an underrun, and communication is ended midway through. 3. The vector interrupt processing in <2> judges whether the data has been correctly transmitted within one frame. If the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the remainder of the data must be transmitted.
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20.6.2 Master reception If master reception is performed, it is necessary to give prior notice of "Slave transmission" to the unit set as slave. Therefore, master reception requires at least two communication frames. The slave unit prepares the transmission data, sets ENSLVTX (slave request transmission flag (bit 4 of the bus control register (BCR)), and then waits.
Approx. 1,014 s (mode 1) <1> Start
Broadcasting Telegraph length
M address P
S address
P
A
Control
P
A
P
A
Data 1
Approx. 390 s (mode 1) <2> Data 1 P A Data 2 P A Data n-1 P A Data n P A
n = Final number of data bytes
Initial preparation processing Sets a unit address, slave address, and control data. Communication start processing Sets the bus control register (enables communication and master request). <1> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of slave request Judgment of collision result Remaster request processing Slave processing Error processing
Interrupt (INTIE1) occurrenceNote 1 The receive data stored to the data register (DR) is read by macro service. At this time, the data transfer direction is SFR (peripheral) RAM (memory). <2> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of end of communication Judgment of end of frame Re-communication processingNote 2 End of communication processing Error processing
Notes 1. If NACK is transmitted (hardware processing) in the data field, an interrupt (INTIE1) is not issued to the CPU, but the same data is retransmitted from the slave. If the receive data is not read in time until the next data is received, the hardware automatically transmits NACK. 2. The vector interrupt processing in <2> judges whether the data has been correctly received within one frame. If the data has not been correctly received (if the number of data to be received in one frame could not be received), a request to retransmit the data must be made to the slave in the next communication frame.
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20.6.3 Slave transmission
Approx. 624 s (mode 1) <1> Start
Broadcasting
6 Control P A
Telegraph length
M address P S address P
A
P
A
Data 1
Approx. 390 s (mode 1) 6 Data 1 P A Data 2 P A 6 6 Data n-1 P A 5 Data n P <2> A
n = Final number of data bytes
Caution
indicates that an interrupt (INTIE1) does not occur.
Initial preparation processing Sets a unit address, telegraph length, and the first byte of the transmit data. Communication start processing Sets the bus control register (enables communication, slave transmission, and slave reception). <1> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of slave request Interrupt (INTIE2) occurrence An interrupt occurs only when 0H, 4H, 5H, or 6H is received in the control field in the slave status. Interrupt (INTIE1) occurrenceNote 1 The transmit data of the second byte and those that follow are written to the data register (DR) by macro service. At this time, the data transfer direction is RAM (memory) SFR (peripheral). <2> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of end of communication Judgment of end of frame Re-communication processingNote 2 End of communication processing Error processing Error processing
Notes 1. If NACK is received from the master in the data field, an interrupt (INTIE1) is not issued to the CPU, but the same data is retransmitted by hardware. If the transmit data is not written in time during the period of writing the next data, a communication error interrupt occurs due to occurrence of underrun, and communication is abnormally ended. 2. The vector interrupt processing in <2> judges whether the data has been correctly transmitted within one frame. If the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the continuation of the data must be transmitted.
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20.6.4 Slave reception
Approx. 1,014 s (mode 1) <1> Start
Broadcasting Telegraph length
M address P S address P
A
Control
P
A
P
A
Data 1
Approx. 390 s (mode 1) 6 Data 1 P A Data 2 P A 6 Data n-1 P 6 A Data n P 6<2> A
n = Final number of data bytes
Initial preparation processing Sets a unit address. Communication start processing Sets the bus control register (enables communication, disables slave transmission, and enables slave reception). <1> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of slave request Slave processingNote 1 Error processing
Interrupt (INTIE1) occurrenceNote 1 The receive data stored to the data register (DR) is read by macro service. At this time, the data transfer direction is SFR (peripheral) RAM (memory). <2> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of end of communication Judgment of end of frame End of frame processingNote 2 End of communication processing Error processing
Notes 1. If NACK is transmitted in the data field, an interrupt (INTIE1) is not issued to the CPU, but the same data is retransmitted from the master. If the receive data is not read in time until the next data is received, NACK is automatically transmitted. 2. The vector interrupt processing in <2> judges whether the data has been correctly received within one frame.
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20.6.5 Interval of occurrence of interrupt for IEBus control Each control interrupt must occur at each point of communication and perform the necessary processing until the next interrupt occurs. Therefore, the CPU must control the IEBus control block, taking the shortest time of this interrupt into consideration. The locations at which the following interrupts may occur are indicated by in the field where it may occur. does not mean that the interrupt occurs at each of the points indicated by . If an error interrupt (timing error, parity error, or ACK error) occurs, the IEBus internal circuit is initialized. As a result, the following interrupt does not occur in that communication frame. (1) Master transmission
Start bit t1 T
Broadcasting Master address P
Slave address T
PA t3
Control A T
PA
Telegraph lengh
PA
Data A T t5
PA U
T
T t2
A
T t4
Communication starts
P Communication starts
Data T
PA U
Data
Data T t4
PA
End of communication End of frame
Remarks 1. T: timing error, P: parity error, A: ACK error, U: underrun error : data set interrupt (INTIE1) 2. End of frame occurs at the end of 32-byte data.
(IEBus: @ 6-MHz operation) Item Communication starts - timing error Communication starts - communication start interrupt Communication start interrupt - ACK error Communication start interrupt - end of communication Data transmission - underrun error Symbol t1 t2 t3 t4 t5 MIN. Approx. 97 Approx. 1,380 Approx. 16 Approx. 1,014 Approx. 390 Unit
s s s s s
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(2) Master reception
Start bit t1 T
Broadcasting Master address P
Slave address T
PA t3
Control A T
PA
Telegraph lengh
PA P
Data A T
PA
T
T t2
A
T t4
Communication starts
P Communication starts
Data T
PA
Data
Data T
PA
t4 t5 End of communication End of frame
Remarks 1. T: timing error, P: parity error, A: ACK error,
: data set interrupt (INTIE1)
2. End of frame occurs at the end of 32-byte data.
(IEBus: @ 6-MHz operation) Item Communication starts - timing error Communication starts - communication start interrupt Communication start interrupt - ACK error Communication start interrupt - end of communication Receive data read interval Symbol t1 t2 t3 t4 t5 MIN. Approx. 97 Approx. 1,380 Approx. 16 Approx. 1,014 Approx. 390 Unit
s s s s s
(3) Slave transmission
Start bit t1 T
Broadcasting Master address P
Slave address P T
PA P
Control T
PA
Telegraph PA lengh
Data A T
PA
T
T t2
PA
T t4
Communication starts
t3 Communication starts
t5 Status request
Data U T
PA
Data U t4 t5
Data T
PA
End of communication End of frame
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Remarks 1. T: timing error, P: parity error, A: ACK error, U: underrun error, 2. End of frame occurs at the end of 32-byte data.
: data set interrupt (INTIE1)
(IEBus: @ 6-MHz operation) Item Communication starts - timing error Communication starts - communication start interrupt Communication start interrupt - status request Communication start interrupt - end of communication Status request - end of communication Symbol t1 t2 t3 t4 t5 MIN. Approx. 97 Approx. 1,380 Approx. 234 Approx. 1,014 Approx. 780 Unit
s s s s s
(4) Slave reception
Start bit t1 T
Broadcasting Master address P
Slave address P T
PA t3
Control A T
PA
Telegraph lengh
PA P
Data T
PA
T
T t2
PA
T t4
Communication starts
P Communication starts
Data T
PA
Data T t4
Data
PA
t5 End of communication End of frame
Remarks 1. T: timing error, P: parity error, A: ACK error,
: data set interrupt (INTIE1)
2. End of frame occurs at the end of 32-byte data.
(IEBus: @ 6-MHz operation) Item Communication starts - timing error Communication starts - communication start interrupt Communication start interrupt - ACK error Communication start interrupt - end of communication Receive data read interval Symbol t1 t2 t3 t4 t5 MIN. Approx. 97 Approx. 1,380 Approx. 16 Approx. 1,014 Approx. 390 Unit
s s s s s
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20.7 Cautions when Using IEBus Controller (1) Receiving slave status request The PD784938 Subseries operates differently from the PD784908 Subseries when receiving the slave status request. The differences are as follows. Table 20-10 shows the operation (slave status request) of IEBus controller of the PD784938 Subseries. Table 20-10. IEBus Controller Operation (Slave Status Request) of PD784938 Subseries
State of PD784938 Subseries Unlocked state Locked state Slave Status Received Control Request 0H, 4H, 5H, 6H Operation During Reception Data * ACK return at ACK period of the control field. * Sets status transmission flag and generates INTIE2.
All units Units that have lock requested Except units that have lock requested
(2) Data register (DR) read operation When receiving a unit, after the reception of each byte is completed, a macro-service activated signal (INTIE1) is generated, and the CPU needs to perform data register (DR) read processing. When this DR read processing is delayed and the next data reception is completed, DR will be updated. Therefore, DR read processing should be completed in the period between INTIE1 generation and the next data reception. The maximum holding time from INTIE1 generation to DR read is approximately 390 s. The PD784908 Subseries has 40 bytes of reception buffer. When receiving data when there is no space in the reception buffer, NACK is returned and a request for data to be retransmitted to the transmission unit is automatically generated. Because, in the case of the PD784938 Subseries (simple IEBus controller), INTIE1 is generated for every 1 byte reception, that DR needs to be read by interrupt processing (macro service recommendation).
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CHAPTER 21 CLOCK OUTPUT FUNCTION
The PD784938 has a clock function that outputs a signal scaled from the system clock. The clock output function can output the system clock directly, or a 1/2, 1/4, 1/8, or 1/16 system clock signal. In addition, it can be used as a 1-bit output port. The output pin has a alternate function as the ASTB pin. Caution This function cannot be used when the external memory expansion mode is used. 21.1 Configuration The clock output function configuration is shown in Figure 21-1. Figure 21-1. Clock Output Function Configuration
LV
0
0
CLE
0
FS2
FS1
FS0
Clock output mode register (CLOM)
fCLK fCLK/2 fCLK/4 fCLK/8 fCLK/16 Selector 1 Output control Selector 2 ASTB/CLOCKOUT
Address latch signal
RESET
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(1) Clock output mode register (CLOM) Register that controls the operation of the clock output function. (2) Selector 1 Selector that selects the frequency of the clock to be output. (3) Output control Controls the output signal in accordance with the contents of the clock output mode register (CLOM). (4) Selector 2 Selects either the ASTB signal or the CLOCKOUT signal as the signal to be output to the ASTB/CLOCKOUT pin. (5) ASTB/CLOCKOUT pin Pin that outputs the signal selected by selector 2. While the RESET input is low, the ASTB/CLOCKOUT pin is in the Hi-Z state, and when the RESET input becomes high, it outputs a low-level signal, and then outputs a signal according to the set function.
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21.2 Clock Output Mode Register (CLOM) The CLOM controls the clock output function. CLOM can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The CLOM format is shown in Figure 21-2. RESET input clears CLOM to 00H. Figure 21-2. Clock Output Mode Register (CLOM) Format
7 CLOM LV 6 0 5 0 4 CLE 3 0 2 FS2 1 FS1 0 FS0 Address 0FFC6H After reset 00H R/W R/W
FS2 0 0 0 0 1
FS1 0 0 1 1 0
FS0 0 1 0 1 0
Frequency Selection fCLKNote fCLK/2 fCLK/4 fCLK/8 fCLK/16
Note Outputs the system clock Duty 50 %
CLE 0 1
Clock Output Control Outputs LV bit contents Outputs clock selected by bits FS2 to FS0
LV 0 1
Output Level Control Outputs low level Outputs high level
Cautions 1. When the external memory expansion mode is used, the clock output mode register (CLOM) should be set to 00H (value after RESET release). 2. The other bits (FS0 to FS2 and LV) must not be changed while the CLE bit is set (to 1). 3. The other bits (FS0 to FS2 and LV) must not be changed at the same time when the CLE bit is changed.
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21.3 Operation 21.3.1 Clock output A signal with the clock output frequency selected by bits FS0 to FS2 is selected by selector 1 and output. The output signal has the same level as the LV bit when the CLE bit is cleared (to 0), and is output from the clock signal immediately after the CLE bit is set (to 1). When the CLE bit is cleared (to 0), the contents of the LV bit are output in synchronization with the clock signal, and further output operations are stopped. Figure 21-3. Clock Output Operation Timing (a) LV = 0
fCLK/n (n = 1, 2, 4, 8, 16)
CLE
CLOCKOUT
(b) LV = 1
fCLK/n (n = 1, 2, 4, 8, 16)
CLE
CLOCKOUT
Setting of bits FS0 to FS2 and the LV bit should only be performed when CLE = 0 (bits FS0 to FS2 and the LV bit should not be changed within the same instruction that changes the CLE bit contents). MOV CLOM, #82H; CLOCKOUT pin: high level, clock output: fCLK/4 SET1 CLE; ...... CLR1 CLE; Stops clock output, CLOCKOUT pin: high level Starts clock output
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21.3.2 1-bit output port When the CLE bit is cleared (to 0), the contents of the LV bit are output from the CLOCKOUT pin. The CLOCKOUT pin changes as soon as the contents of the LV bit change. Figure 21-4. 1-Bit Output Port Operation
LV
CLOCKOUT
SET1 LV instruction executed
CLR1 LV instruction executed
21.3.3 Operation in standby mode (1) HALT mode The state prior to setting of the HALT mode is maintained. That is, if, during clock output, clock output has been performed continuously, and clock output has been disabled, the LV bit contents set before the HALT mode setting are output unchanged. (2) STOP mode and IDLE mode Clock output must be disabled before setting the STOP mode or IDLE mode (this must be done by software). The CLOCKOUT pin level output is the level before the STOP mode or IDLE mode was set (the contents of the LV bit). 21.4 Cautions (1) This function cannot be used when the external memory expansion mode is used. (2) When the external memory expansion mode is used, the clock output mode register (CLOM) should be set to 00H (value after RESET release). (3) The other bits (FS0 to FS2 and LV) must not be changed while the CLE bit is set (to 1). (4) The other bits (FS0 to FS2 and LV) must not be changed at the same time when the CLE bit is changed.
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CHAPTER 22 EDGE DETECTION FUNCTION
P20 to P26 have an edge detection function that allows a rising edge/falling edge to be set programmable, and the detected edge is sent to internal hardware. The relation between pins P20 to P26 and the use of the detected edge is shown in Table 22-1. Table 22-1. Pins P20 to P26 and Use of Detected Edge
Pin P20 P21 NMI, standby circuit control INTP0, timer/event counter 1 capture signal timer/event counter 1 count clock signal Real-time output port trigger signal INTP1, timer/event counter 2 CR22 capture signal INTP2, CI (timer/event counter 2 count clock signal), timer/event counter 2 CR21 capture signal INTP3, timer/event counter 0 capture signal timer/event counter 0 count clock signal INTP4, standby circuit control INTP5, A/D converter conversion start signal, standby circuit control INTM1 Use Detected Edge Specification Register INTM0
P22 P23
P24
P25 P26
The edge detection function operates at all times except in STOP mode and IDLE mode (although the edge detection function for pins P20, P25, and P26 also operates in STOP mode and IDLE mode). For the P21/INTP0 pin, the noise elimination time when edge detection is performed can be selected by software. 22.1 Edge Detection Function Control Registers 22.1.1 External interrupt mode registers (INTM0, INTM1) The INTMn (n = 0, 1) specify the valid edge to be detected on pins P20 to P26. The INTM0 specifies the valid edge for pins P20 to P23, and the INTM1 specifies the valid edge for pins P24 to P26. The INTMn can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The format of INTM0 and INTM1 are shown in Figures 22-1 and 22-2 respectively. RESET input clears these registers to 00H.
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Figure 22-1. External Interrupt Mode Register 0 (INTM0) Format
7 INTM0 ES21 6 ES20 5 ES11 4 ES10 3 ES01 2 ES00 1 0 0 ESNM1 Address 0FFA0H After reset 00H R/W R/W
ESNM1 0 1
P20 (NMI) Pin Input Detected Edge Specification Falling edge Rising edge P21 (INTP0, CR11/CR11W Capture Trigger, TM1/TM1W Count Clock, Real-Time Output Port Output Trigger) Pin Input Detected Edge Specification Falling edge Rising edge Setting prohibited Both falling & rising edges
ES01 ES00
0 0 1 1
0 1 0 1
ES11 ES10 P22 (INTP1, CR22/CR22W Capture Trigger) Pin Input Detected Edge Specification 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both falling & rising edges
ES21 ES20 P23 (INTP2, CR21/CR21W Capture Trigger, CI) Pin Input Detected Edge Specification 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both falling & rising edges
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Figure 22-2. External Interrupt Mode Register 1 (INTM1) Format
7 INTM1 0 6 0 5 ES51 4 ES50 3 ES41 2 ES40 1 ES31 0 ES30 Address 0FFA1H After reset 00H R/W R/W
ES31 ES30 P24 (INTP3, CR02 Capture Trigger, TM0 Count Clock) Pin Input Detected Edge Specification 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both falling & rising edges P25 (INTP4) Pin Input Detected Edge Specification Falling edge Rising edge Setting prohibited Both falling & rising edges
ES41 ES40 0 0 1 1 0 1 0 1
ES51 ES50 P26 (INTP5, A/D Conversion Start Signal) Pin Input Detected Edge Specification 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both falling & rising edges
Caution Valid edge detection cannot be performed when the valid edge is changed by a write to the external interrupt mode register (INTMn: n = 0, 1). Also, if an edge is input during a change of the valid edge, that edge may or may not be judged to be a valid edge.
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22.1.2 Sampling clock selection register (SCS0) SCS0 specifies the sampling clock (fSMP) for digital noise elimination performed on pin P21. SCS0 can be read or written to with an 8-bit manipulation instruction. The format of SCS0 is shown in Figure 22-3. RESET input clears SCS0 to 00H. Figure 22-3. Sampling Clock Selection Register (SCS0) Format
7 SCS0 0 6 0 5 0 4 0 3 0 2 0 1 0 Address 0FFA4H After reset 00H R/W R/W fXX = 12.58 MHz fCLK = 12.58 MHz SCS01 SCS00 Sampling Clock (fSMP) Pulse Width Eliminated as Noise Minimum Pulse Width Recognized as Signal 3/fCLK (239 ns) 96/fXX (7.7 s) 192/fXX (15.3 s) 384/fXX (30.5 s)
SCS01 SCS00
0 0 1 1
0 1 0 1
fCLK fXX/32 fXX/64 fXX/128
2/fCLK (159 ns) 64/fXX (5.1 s) 128/fXX (10.2 s) 256/fXX (20.3 s)
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22.2 Edge Detection for Pins P20, P25, and P26 On pins P20, P25, and P26, noise elimination is performed by means of analog delay before edge detection. Therefore, an edge cannot be detected unless the pulse width is a given time (10 s) or longer. Figure 22-4. Edge Detection for Pins P20, P25, and P26
10 s (MIN.) P20/P25/P26 input 10 s (MAX.)
P20/P25/P26 input signal after noise elimination
10 s (MAX.)
Rising edge
Falling edge
Eliminated as noise since pulse is short
Eliminated as noise since pulse is short Falling edge detected since Rising edge detected since pulse is sufficiently wide pulse is suficiently wide
Caution Since analog delay noise elimination is performed on pins P20, P25, and P26, an edge is detected up to 10 s after it is actually input. Also, unlike pins P21 to P24, the delay before an edge is detected is not a specific value, because of differences in the characteristics of various devices.
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22.3 P21 Pin Edge Detection In P21 edge detection, digital noise elimination is performed using the clock (fSMP) specified by the sampling clock selection register (SCS0). In digital noise elimination, input is sampled using the fSMP clock, and if the input level is not the same at least three times in succession (if it is the same only two or fewer times in succession), it is eliminated as noise. Therefore, the level must be maintained for at least 3 fSMP clock cycles in order to be recognized as a valid edge. Remark When the pulse width of a signal with a comparatively long pulse width and a lot of noise, such as a reception signal infrared remote controller, is measured, or when a signal is input in which oscillation occurs when an edge occurs, as with switch input chattering, for instance, it is better to set the sampling clock to low speed with the sampling clock selection register (SCS0). If the sampling clock is high-speed, there will be a reaction to the short-pulse noise components as well, and the program will frequently have to judge whether the input is noise or a signal. However, by slowing down the sampling clock, reaction to short pulse width noise is eliminated and thus the program does not have to make judgments so frequently, and can thus be simplified. Figure 22-5. P21 Pin Edge Detection
P21 input fSMP
P21 input signal after noise elimination Rising edge
Falling edge
Digital noise elimination by fSMP clock
Cautions 1. Since digital noise elimination is performed with the fSMP clock, there is a delay of 2 to 3 fSMP clocks between input of an edge to the pin and the point at which the edge is actually detected. 2. If the input pulse width is 2 to 3 fSMP clocks, it is uncertain whether a valid edge will be detected. Therefore, to ensure reliable operation, the level should be held for at least 3 clocks. 3. If noise input to the pin is synchronized with the fSMP clock in the PD784938, it may not be recognized as noise. If there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pin.
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22.4 Pin Edge Detection for Pins P22 to P24 Edge detection for pins P22 to P24 is performed after digital noise elimination by means of clock sampling. Unlike the P21 pin, fCLK is used as the sampling clock. In digital noise elimination, input is sampled using the fCLK clock, and if the input level is not the same at least three times in succession (if it is the same only two or fewer times in succession), it is eliminated as noise. Therefore, the level must be maintained for at least 3 fCLK clock cycles (0.24 s: fCLK = 12.58 MHz) in order to be recognized as a valid edge. Figure 22-6. Edge Detection for Pins P22 to P24
P22 to P24 input
fCLK
P22 to P24 input signal after noise elimination Rising edge
Falling edge
Digital noise elimination with fCLK clock
Cautions 1. Since digital noise elimination is performed with the fCLK clock, there is a delay of 2 to 3 fCLK clocks between input of an edge to the pin and the point at which the edge is actually detected. 2. If the input pulse width is 2 to 3 fCLK clocks, it is uncertain whether a valid edge will be detected. Therefore, to ensure reliable operation, the level should be held for at least 3 clocks. 3. If noise input to a pin is synchronized with the fCLK clock in the PD784938, it may not be recognized as noise. If there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pins.
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22.5 Cautions (1) Valid edge detection cannot be performed when the valid edge is changed by a write to the external interrupt mode register (INTMn: n = 0, 1). Also, if an edge is input during a change of the valid edge, that edge may or may not be judged to be a valid edge. (2) Since analog delay noise elimination is performed on pins P20, P25, and P26, an edge is detected up to 10 s after it is actually input. Also, unlike pins P21 to P24, the delay before an edge is detected is not a specific value, because of differences in the characteristics of various devices. (3) Since digital noise elimination is performed on the P21 pin with the fSMP clock, there is a delay of 2 to 3 fSMP clocks between input of an edge to the pin and the point at which the edge is actually detected. (4) If the input pulse width on the P21 pin is 2 to 3 fSMP clocks, it is uncertain whether a valid edge will be detected. Therefore, to ensure reliable operation, the level should be held for at least 3 clocks. (5) If noise input of the P21 pin is synchronized with the fSMP clock in the PD784938, it may not be recognized as noise. If there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pins. (6) Since digital noise elimination is performed on pins P22 to P24 with the fCLK clock, there is a delay of 2 to 3 fCLK clocks between input of an edge to the pin and the point at which the edge is actually detected. (7) If the input pulse width on pins P22 to P24 is 2 to 3 fCLK clocks, it is uncertain whether a valid edge will be detected. Therefore, to ensure reliable operation, the level should be held for at least 3 clocks. (8) If noise input to pins P22 to P24 is synchronized with the fCLK clock in the PD784938, it may not be recognized as noise. If there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pins.
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CHAPTER 23 INTERRUPT FUNCTIONS
The PD784938 is provided with three interrupt request service modes (see Table 23-1). These three service modes can be set as required in the program. However interrupt service by macro service can only be selected for interrupt request sources provided with the macro service processing mode shown in Table 23-2. Context switching cannot be selected for non-maskable interrupts or operand error interrupts. Multiple-interrupt control using 4 priority levels can easily be performed for maskable vectored interrupts. Table 23-1. Interrupt Request Service Modes
Interrupt Request Service Mode Vectored interrupts Servicing Performed PC & PSW Contents Service
Software
Saving to & restoration from stack Saving to & restoration from fixed area in register bank
Executed by branching to service program at addressNote specified by vector table Executed by automatic switching to register bank specified by vector table and branching to service program at addressNote specified by fixed area in register bank
Context switching
Macro service
Hardware (firmware)
Retained
Execution of pre-set service such as data transfers between memory and I/O
Note The start addresses of all interrupt service programs must be in the base area. If the body of a service program cannot be located in the base area, a branch instruction to the service program should be written in the base area.
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23.1 Interrupt Request Sources The PD784938 has the 29 interrupt request sources shown in Table 23-2, with a vector table allocated to each. Table 23-2. Interrupt Request Sources (1/2)
Type of Interrupt Request Default Priority Interrupt Request Generating Source Generating Unit Interrupt Control Register Name Context Switching Macro Service Macro Service Control Word Address -- Vector Table Address
Software
None
BRK instruction execution
--
-- possible --
Not possible Possible
Not
3EH
BRKCS instruction execution
--
Not
--
--
Operand error
None
Invalid operand in MOV STBC, #byte instruction or MOV WDM, #byte instruction, and LOCATION instruction NMI (pin input edge detection)
--
--
Not possible
Not possible
--
3CH
Nonmaskable
None
Edge detection Watchdog timer
--
Not possible Not possible
Not possible Not possible
--
2H
INTWDT (watchdog timer overflow)
--
--
4H
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Table 23-2. Interrupt Request Sources (2/2)
Type of Interrupt Request Default Priority Interrupt Request Generating Source Generating Unit Interrupt Control Register Name Context Switching Macro Service Macro Service Control Word Address 0FE06H 0FE08H 0FE0AH 0FE0CH 0FE0EH 0FE10H 0FE12H 0FE14H 0FE16H 0FE18H 0FE1AH 0FE1CH 0FE1EH 0FE20H Not possible Possible 0FE22H 0FE24H Vector Table Address
Maskable
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INTP0 (pin input edge detection) INTP1 (pin input edge detection) INTP2 (pin input edge detection) INTP3 (pin input edge detection) INTC00 (TM0-CR00 match signal generation) INTC01 (TM0-CR01 match signal generation) INTC10 (TM1-CR10 or TM1WCR10W match signal generation) INTC11 (TM1-CR11 or TM1WCR11W match signal generation) INTC20 (TM2-CR20 or TM2WCR20W match signal generation) INTC21 (TM2-CR21 or TM2WCR21W match signal generation) INTC30 (TM3-CR30 or TM3WCR30W match signal generation) INTP4 (pin input edge detection) INTP5 (pin input edge detection) INTAD (A/D conversion end) INTSER (asynchronous serial interface receive error) INTSR (asynchronous serial interface reception end) INTCSI1 (clocked serial interface transfer end) INTST (asynchronous serial interface transmission end) INTCSI (clocked serial interface transfer end) INTSER2 (asynchronous serial interface 2 receive error) INTSR2 (asynchronous serial interface 2 reception end) INTCSI2 (clocked serial interface 2 transfer end) INTST2 (asynchronous serial interface 2 transmission end) INTIE1 (IEBus data access request) INTIE2 (IEBus communication error and communication end) INTW (watch timer output) INTCSI3 (clocked serial interface 3 transfer end)
Edge detection
Timer/event counter 0
PIC0 PIC1 PIC2 PIC3 CIC00 CIC01
Possible
Possible
6H 8H 0AH 0CH 0EH 10H 12H 14H 16H 18H 1AH 1CH 1EH 20H 22H 24H
Timer/event counter 1
CIC10 CIC11
Timer/event counter 2
CIC20 CIC21
Timer 3 Edge detection A/D converter Asynchronous serial interface/ clocked serial interface 1 Clocked serial interface Asynchronous serial interface 2/ clocked serial interface 2 IEBus controller Watch timer Clocked serial interface 3
CIC30 PIC4 PIC5 ADIC SERIC SRIC CSIIC1 STIC CSIIC
16 17
0FE26H 0FE28H
26H 28H
18 19
SERIC2 SRIC2 CSIIC2 STIC2 IEIC1 IEIC2 WIC CSIIC3
Not possible Possible
0FE2AH 0FE2CH
2AH 2CH
20 21 22 23 24
0FE2EH 0FE32H 0FE34H 0FE36H 0FE38H
2EH 32H 34H 36H 38H
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Remarks 1. The default priority is a fixed number. This indicates the order of priority when interrupt requests specified as having the same priority are generated simultaneously, 2. The INTSR and INTCSI1 interrupts are generated by the same hardware (they cannot both be used simultaneously). Therefore, although the same hardware is used for the interrupts, two names are provided, for use in each of the two modes. The same applies to INTSR2 and INTCSI2. 23.1.1 Software interrupts Interrupts by software consist of the BRK instruction which generates a vectored interrupt and the BRKCS instruction which performs context switching. Software interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control. 23.1.2 Operand error interrupts These interrupts are generated if there is an illegal operand in an MOV STBC, #byte instruction or MOV WDMC, #byte instruction, and LOCATION instruction. Operand error interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control. 23.1.3 Non-maskable interrupts A non-maskable interrupt is generated by NMI pin input or the watchdog timer. Non-maskable interrupts are acknowledged unconditionallyNote, even in the interrupt disabled state. They are not subject to interrupt priority control, and are of higher priority that any other interrupt. Note Except during execution of the service program for the same non-maskable interrupt, and during execution of the service program for a higher-priority non-maskable interrupt 23.1.4 Maskable interrupts A maskable interrupt is one subject to masking control according to the setting of an interrupt mask flag. In addition, acknowledgment enabling/disabling can be specified for all maskable interrupts by means of the IE flag in the program status word (PSW). In addition to normal vectored interruption, maskable interrupts can be acknowledged by context switching and macro service (though some interrupts cannot use macro service: see Table 23-2). The priority order for maskable interrupt requests when interrupt requests of the same priority are generated simultaneously is predetermined (default priority) as shown in Table 23-2. Also, multiprocessing control can be performed with interrupt priorities divided into 4 levels. However, macro service requests are acknowledged without regard to priority control or the IE flag.
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23.2 Interrupt Service Modes There are three PD784938 interrupt service modes, as follows: * Vectored interrupt service * Macro service * Context switching 23.2.1 Vectored interrupt service When an interrupt is acknowledged, the program counter (PC) and program status word (PSW) are automatically saved to the stack, a branch is made to the address indicated by the data stored in the vector table, and the interrupt service routine is executed. 23.2.2 Macro service When an interrupt is acknowledged, CPU execution is temporarily suspended and a data transfer is performed by hardware. Since macro service is performed without the intermediation of the CPU, it is not necessary to save or restore CPU statuses such as the program counter (PC) and program status word (PSW) contents. This is therefore very effective in improving the CPU service time (See 23.8 Macro Service Function). 23.2.3 Context switching When an interrupt is acknowledged, the prescribed register bank is selected by hardware, a branch is made to a preset vector address in the register bank, and at the same time the current program counter (PC) and program status word (PSW) are saved in the register bank (see 23.4.2 BRKCS instruction software interrupt (software context switching) acknowledgment operation and 23.7.2 Context switching). Remark "Context" refers to the CPU registers that can be accessed by a program while that program is being executed. These registers include general registers, the program counter (PC), program status word (PSW), and stack pointer (SP).
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23.3 Interrupt Service Control Registers
PD784938 interrupt service is controlled for each interrupt request by various control registers that perform interrupt
service specification. The interrupt control registers are listed in Table 23-3. Table 23-3. Control Registers
Register Name Interrupt control registers Symbol PIC0 PIC1 PIC2 PIC3 CIC00 CIC01 CIC10 CIC11 CIC20 CIC21 CIC30 PIC4 PIC5 ADIC SERIC SRIC CSIIC1 STIC CSIIC SERIC2 SRIC2 CSIIC2 STIC2 IEIC1 IEIC2 WIC CSIIC3 Interrupt mask registers MK0 MK1 Maskable interrupt request mask control Linked to mask control flags in interrupt control registers Word accesses or byte accesses possible In-service priority register Interrupt mode control register ISPR IMC Records priority of interrupt request currently being acknowledged Controls nesting of maskable interrupts for which lowest priority level (level 3) is specified Specifies priority of interrupts due to NMI pin input and interrupts due to watchdog timer overflow Specifies enabling/disabling of maskable interrupt acknowledgment Function Registers that perform each interrupt request generation recording, mask control, vectored interrupt service or macro service specification, context switching function enabling/disabling, and priority specification.
Watchdog timer mode register
WDM
Program status word
PSW
An interrupt control register is allocated to each interrupt source. The flags of each register perform control of the contents corresponding to the relevant bit position in the register. The interrupt control register flag names corresponding to each interrupt request signal are shown in Table 23-4.
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Table 23-4. Interrupt Control Register Flags Corresponding to Interrupt Request (1/2)
Default Priority Interrupt Request Signal INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC20 INTC21 INTC30 INTP4 INTP5 INTAD INTSER INTSR INTCSI1 16 17 18 19 INTST INTCSI INTSER2 INTSR2 INTCSI2 PIC0 PIC1 PIC2 PIC3 CIC00 CIC01 CIC10 CIC11 CIC20 CIC21 CIC30 PIC4 PIC5 ADIC SERIC SRIC CSIIC1 STIC CSIIC SERIC2 SRIC2 CSIIC2 Interrupt Control Registers Interrupt Request Flag PIF0 PIF1 PIF2 PIF3 CIF00 CIF01 CIF10 CIF11 CIF20 CIF21 CIF30 PIF4 PIF5 ADIF SERIF SRIF CSIIF1 STIF CSIIF SERIF2 SRIF2 CSIIF2 Interrupt Mask Flag PMK0 PMK1 PMK2 PMK3 CMK00 CMK01 CMK10 CMK11 CMK20 CMK21 CMK30 PMK4 PMK5 ADMK SERMK SRMK CSIMK1 STMK CSIMK SERMK2 SRMK2 CSIMK2 Macro Service Enable Flag PISM0 PISM1 PISM2 PISM3 CISM00 CISM01 CISM10 CISM11 CISM20 CISM21 CISM30 PISM4 PISM5 ADISM -- SRISM CSIISM1 STISM CSIISM -- SRISM2 CSIISM2 Priority Specification Flag PPR00 PPR01 PPR10 PPR11 PPR20 PPR21 PPR30 PPR31 CPR000 CPR001 CPR010 CPR011 CPR100 CPR101 CPR110 CPR111 CPR200 CPR201 CPR210 CPR211 CPR300 CPR301 PPR40 PPR41 PPR50 PPR51 ADPR0 ADPR1 SERPR0 SERPR1 SRPR0 SRPR1 CSIPR10 CSIPR11 STPR0 STPR1 CSIPR0 CSIPR1 SERPR20 SERPR21 SRPR20 SRPR21 CSIPR20 CSIPR21 Context Switching Enable Flag PCSE0 PCSE1 PCSE2 PCSE3 CCSE00 CCSE01 CCSE10 CCSE11 CCSE20 CCSE21 CCSE30 PCSE4 PCSE5 ADCSE SERCSE SRCSE CSICSE1 STCSE CSICSE SERCSE2 SRCSE2 CSICSE2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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Table 23-4. Interrupt Control Register Flags Corresponding to Interrupt Request (2/2)
Default Priority Interrupt Request Signal INTST2 INTIE1 INTIE2 INTW INTCSI3 STIC2 IEIC1 IEIC2 WIC CSIIC3 Interrupt Control Registers Interrupt Request Flag STIF2 IEIF1 IEIF2 WIF CSIIF3 Interrupt Mask Flag STMK2 IEMK1 IEMK2 WMK CSIMK3 Macro Service Enable Flag STISM2 IEISM1 IEISM2 WISM CSIISM3 Priority Specification Flag STPR20 SERPR21 IEPR10 IEPR11 IEPR20 IEPR21 WRP0 WRP1 CSIPR30 CSIPR31 Context Switching Enable Flag STCSE2 IECSE1 IECSE2 WCSE CSICSE3
20 21 22 23 24
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23.3.1 Interrupt control registers An interrupt control register is allocated to each interrupt source, and performs priority control, mask control, etc. for the corresponding interrupt request. The interrupt control register format is shown in Figure 23-1. (1) Priority specification flags (xxPR1/xxPR0) The priority specification flags specify the priority on an individual interrupt source basis for the 25 maskable interrupts. Up to 4 priority levels can be specified, and a number of interrupt sources can be specified at the same level. Among maskable interrupt sources, level 0 is the highest priority. If multiple interrupt requests are generated simultaneously among interrupt source of the same priority level, they are acknowledged in default priority order. These flags can be manipulated bit-wise by software. RESET input sets all bits to "1". (2) Context switching enable flag (xxCSE) The context switching enable flag specifies that a maskable interrupt request is to be serviced by context switching. In context switching, the register bank specified beforehand is selected by hardware, a branch is made to a vector address stored beforehand in the register bank, and at the same time the current contents of the program counter (PC) and program status word (PSW) are saved in the register bank. Context switching is suitable for real-time processing, since execution of interrupt servicing can be started faster than with normal vectored interrupt servicing. This flag can be manipulated bit-wise by software. (3) Macro service enable flag (xxISM) The macro service enable flag specifies whether an interrupt request corresponding to that flag is to be handled by vectored interruption or context switching, or by macro service. When macro service processing is selected, at the end of the macro service (when the macro service counter reaches 0) the macro service enable flag is automatically cleared (to 0) by hardware (vectored interrupt service/context switching service). This flag can be manipulated bit-wise by software. RESET input sets all bits to "0". (4) Interrupt mask flag (xxMK) An interrupt mask flag specifies enabling/disabling of vectored interrupt servicing and macro service processing for the interrupt request corresponding to that flag. The interrupt mask contents are not changed by the start of interrupt service, etc., and are the same as the interrupt mask register contents (see 23.3.2 Interrupt Mask Registers (MK0/MK1)). Macro service processing requests are also subject to mask control, and macro service requests can also be masked with this flag. This flag can be manipulated by software. RESET input sets all bits to "1". (5) Interrupt request flag (xxIF) An interrupt request flag is set (to 1) by generation of the interrupt request that corresponds to that flag. When the interrupt is acknowledged, the flag is automatically cleared (to 0) by hardware. This flag can be manipulated by software. RESET input sets all bits to "0".
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Figure 23-1. Interrupt Control Registers (xxICn) (1/4)
7 PIC0 PIF0 6 PMK0 5 PISM0 4 PCSE0 3 0 2 0 1 PPR01 0 PPR00 Address 0FFE0H After reset 43H R/W R/W
PIC1
PIF1
PMK1
PISM1
PCSE1
0
0
PPR11
PPR10
0FFE1H
43H
R/W
PIC2
PIF2
PMK2
PISM2
PCSE2
0
0
PPR21
PPR20
0FFE2H
43H
R/W
PIC3
PIF3
PMK3
PISM3
PCSE3
0
0
PPR31
PPR30
0FFE3H
43H
R/W
CIC00
CIF00
CMK00
CISM00 CCSE00
0
0
CPR001 CPR000
0FFE4H
43H
R/W
CIC01
CIF01
CMK01
CISM01 CCSE01
0
0
CPR011 CPR010
0FFE5H
43H
R/W
CIC10
CIF10
CMK10
CISM10 CCSE10
0
0
CPR101 CPR100
0FFE6H
43H
R/W
CIC11
CIF11
CMK11
CISM11 CCSE11
0
0
CPR111 CPR110
0FFE7H
43H
R/W
xxPRn1 xxPRn0 (Bit 1) (Bit 0) 0 0 1 1 xxCSEn (Bit 4) 0 1 xxISMn (Bit 5) 0 1 xxMKn (Bit 6) 0 1 xxIFn (Bit 7) 0 1 0 1 0 1
Interrupt Request Priority Specification Priority 0 (highest priority) Priority 1 Priority 2 Priority 3
Context Switching Service Specification Serviced by vectored interrupt Serviced by context switching Interrupt Service Mode Specification Vectored interrupt service/ context switching service Macro service
Interrupt Service Enabling/Disabling Interrupt service enabled Interrupt service disabled Interrupt Request Generation Presence/Absence No interrupt request (interrupt signal not being generated) Interrupt request state (interrupt signal being generated)
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Figure 23-1. Interrupt Control Registers (xxICn) (2/4)
7 CIC20 CIF20 6 CMK20 5 4 3 0 2 0 1 0 Address 0FFE8H After reset 43H R/W R/W
CISM20 CCSE20
CPR201 CPR200
CIC21
CIF21
CMK21
CISM21 CCSE21
0
0
CPR211 CPR210
0FFE9H
43H
R/W
CIC30
CIF30
CMK30
CISM30 CCSE30
0
0
CPR301 CPR300
0FFEAH
43H
R/W
PIC4
PIF4
PMK4
PISM4
PCSE4
0
0
PPR41
PPR40
0FFEBH
43H
R/W
PIC5
PIF5
PMK5
PISM5
PCSE5
0
0
PPR51
PPR50
0FFECH
43H
R/W
ADIC
ADIF
ADMK
ADISM
ADCSE
0
0
ADPR1
ADPR0
0FFEDH
43H
R/W
SERIC
SERIF
SERMK
0
SERCSE
0
0
SERPR1 SERPR0
0FFEEH
43H
R/W
SRIC
SRIF
SRMK
SRISM
SRCSE
0
0
SRPR1
SRPR0
0FFEFH
43H
R/W
xxPRn1 xxPRn0 (Bit 1) (Bit 0) 0 0 1 1 xxCSEn (Bit 4) 0 1 xxISMn (Bit 5) 0 1 xxMKn (Bit 6) 0 1 xxIFn (Bit 7) 0 1 0 1 0 1
Interrupt Request Priority Specification Priority 0 (highest priority) Priority 1 Priority 2 Priority 3
Context Switching Service Specification Serviced by vectored interrupt Serviced by context switching Interrupt Service Mode Specification Vectored interrupt service/ context switching service Macro service Interrupt Service Enabling/Disabling Interrupt service enabled Interrupt service disabled Interrupt Request Generation Presence/Absence No interrupt request (interrupt signal not being generated) Interrupt request state (interrupt signal being generated)
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Figure 23-1. Interrupt Control Registers (xxICn) (3/4)
7 CSIIC1 6 5 4 3 0 2 0 1 0 Address 0FFEFH After reset 43H R/W R/W
CSIIF1 CSIMK1 CSIISM1 CSICSE1
CSIPR11 CSIPR10
STIC
STIF
STMK
STISM
STCSE
0
0
STPR1
STPR0
0FFF0H
43H
R/W
CSIIC
CSIIF
CSIMK
CSIISM CSICSE
0
0
CSIPR1 CSIPR0
0FFF1H
43H
R/W
SERIC2 SERIF2 SERMK2
0
SERCSE2
0
0
SERPR21 SERPR20
0FFF2H
43H
R/W
SRIC2
SRIF2
SRMK2 SRISM2 SRCSE2
0
0
SRPR21 SRPR20
0FFF3H
43H
R/W
CSIIC2
CSIIF2 CSIMK2 CSIISM2 CSICSE2
0
0
CSIPR21 CSIPR20
0FFF3H
43H
R/W
STIC2
STIF2
STMK2
STISM2 STCSE2
0
0
STPR21 STPR20
0FFF4H
43H
R/W
xxPRn1 xxPRn0 (Bit 1) (Bit 0) 0 0 1 1 xxCSEn (Bit 4) 0 1 xxISMn (Bit 5) 0 1 xxMKn (Bit 6) 0 1 xxIFn (Bit 7) 0 1 0 1 0 1
Interrupt Request Priority Specification Priority 0 (highest priority) Priority 1 Priority 2 Priority 3
Context Switching Service Specification Serviced by vectored interrupt Serviced by context switching Interrupt Service Mode Specification
Vectored interrupt service/ context switching service Macro service Interrupt Service Enabling/Disabling
Interrupt service enabled Interrupt service disabled Interrupt Request Generation Presence/Absence No interrupt request (interrupt signal not being generated) Interrupt request state (interrupt signal being generated)
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Figure 23-1. Interrupt Control Registers (xxICn) (4/4)
7 IEIC1 IEIF1 6 IEMK1 5 4 3 0 2 0 1 IEPR11 0 IEPR10 Address 0FFF6H After reset 43H R/W R/W
IEISM1 IECSE1
IEIC2
IEIF2
IEMK2
IEISM2 IECSE2
0
0
IEPR21
IEPR20
0FFF7H
43H
R/W
WIC
WIF
WMK
WISM
WCSE
0
0
WPR1
WPR0
0FFF8H
43H
R/W
CSIIC3
CSIIF3
CSIMK3 CSIISM3 CSICSE3
0
0
CSIPR31 CSIPR30
0FFF9H
43H
R/W
xxPRn1 xxPRn0 (Bit 1) (Bit 0) 0 0 1 1 xxCSEn (Bit 4) 0 1 xxISMn (Bit 5) 0 1 xxMKn (Bit 6) 0 1 xxIFn (Bit 7) 0 1 0 1 0 1
Interrupt Request Priority Specification Priority 0 (highest priority) Priority 1 Priority 2 Priority 3
Context Switching Service Specification Serviced by vectored interrupt Serviced by context switching Interrupt Service Mode Specification Vectored interrupt service/ context switching service Macro service Interrupt Service Enabling/Disabling Interrupt service enabled Interrupt service disabled Interrupt Request Generation Presence/Absence No interrupt request (interrupt signal not being generated) Interrupt request state (interrupt signal being generated)
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23.3.2 Interrupt mask registers (MK0/MK1) MK0 and MK1 are composed of interrupt mask flags. MK0 and MK1 are 16-bit register which can be manipulated as 8-bit units, MK0L, MK0H, MK1L, and MK1H, as well as being manipulated as a 16-bit unit. In addition, each bit of MK0 and MK1 can be manipulated individually with a bit manipulation instruction. Each interrupt mask flag controls enabling/disabling of the corresponding interrupt request. When an interrupt mask flag is set (to 1), acknowledgment of the corresponding interrupt request is disabled. When an interrupt mask flag is cleared (to 0), the corresponding interrupt request can be acknowledged as a vectored interrupt or macro service request. Each interrupt mask flag in MK0 and MK1 is the same flag as the interrupt mask flag in the interrupt control register. MK0 and MK1 are provided for en bloc control of interrupt masking. RESET input sets MK0 and MK1 to FFFFH, and all maskable interrupts are disabled. Figure 23-2. Interrupt Mask Register (MK0, MK1) Format (1/2) (1) Byte Accesses
7 MK0L CMK11 6 CMK10 5 CMK01 4 CMK00 3 PMK3 2 PMK2 1 PMK1 0 PMK0 Address 0FFACH After reset FFH R/W R/W
MK0H
CSIMK1 SERMK SRMK
ADMK
PMK5
PMK4
CMK30
CMK21
CMK20
0FFADH
FFH
R/W
MK1L
IEMK2
IEMK1
1
STMK2
CSIMK2 SERMK2 CSIMK SRMK2
STMK
0FFAEH
FFH
R/W
MK1H
1
1
1
1
1
1
CSIMK3
WMK
0FFAFH
FFH
R/W
MK 0 1
Interrupt Request Enabling/Disabling Specification Interrupt service enabled Interrupt service disabled
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Figure 23-2. Interrupt Mask Register (MK0, MK1) Format (2/2) (2) Word Accesses
15 MK0 14 13 ADMK 6 12 PMK5 5 CMK01 12 1 5 1 11 PMK4 4 CMK00 11 1 4 STMK2 10 CMK30 3 PMK3 10 1 3 9 CMK21 2 PMK2 9 CSIMK3 2 8 CMK20 1 PMK1 8 WMK 1 0 STMK 0 PMK0
CSIMK1 SRMK SERMK 7
Address 0FFACH
After reset FFFFH
R/W R/W
CMK11 CMK10 15 MK1 1 14 1 7 IEMK2 13 1 6 IEMK1
Address 0FFAEH
After reset FFFFH
R/W R/W
CSIMK2 SERMK2 CSIMK SRMK2
MK 0 1
Interrupt Request Enabling/Disabling Specification Interrupt service enabled Interrupt service disabled
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23.3.3 In-service priority register (ISPR) ISPR shows the priority level of the maskable interrupt currently being serviced and the non-maskable interrupt being serviced. When a maskable interrupt request is acknowledged, the bit corresponding to the priority of that interrupt request is set (to 1), and remains set until the service program ends. When a non-maskable interrupt is acknowledged, the bit corresponding to the priority of that non-maskable interrupt is set (to 1), and remains set until the service program ends. When an RETI instruction or RETCS instruction is executed, the bit, among those set (to 1) in the ISPR, that corresponds to the highest-priority interrupt request is automatically cleared (to 0) by hardware. The contents of ISPR are not changed by execution of an RETB or RETCSB instruction. RESET input clears ISPR to 00H. Figure 23-3. In-Service Priority Register (ISPR) Format
7 ISPR NMIS 6 WDTS 5 0 4 0 3 2 1 0 Address 0FFA8H After reset 00H R/W R (n = 0 to 3) ISPRn 0 1 Priority Level Priority n interrupt not being acknowledged Priority n interrupt being acknowledged
ISPR3 ISPR2 ISPR1 ISPR0
WDTS 0 1
Watchdog Timer Interrupt Service State Watchdog timer interrupt not being acknowledged Watchdog timer interrupt being acknowledged
NMIS 0 1
NMI Service State NMI interrupt not being acknowledged NMI interrupt being acknowledged
Caution In-service priority register (ISPR) is a read-only register. There is a risk of misoperation if a write is performed on this register.
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23.3.4 Interrupt mode control register (IMC) IMC contains the PRSL flag. The PRSL flag specifies enabling/disabling of nesting of maskable interrupts for which the lowest priority level (level 3) is specified. When IMC is manipulated, the interrupt disabled state (DI state) should be set first to prevent misoperation. IMC can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. RESET input sets IMC to 80H. Figure 23-4. Interrupt Mode Control Register (IMC) Format
7 IMC PRSL 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Address 0FFAAH After reset 80H R/W R/W
PRSL 0 1
Control of Nesting Operations for Maskable Interrupts (Lowest Level) Nesting between interrupts set as level 3 (lowest level) enabled Nesting between interrupts set as level 3 (lowest level) disabled
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23.3.5 Watchdog timer mode register (WDM) The PRC bit of WDM specifies the priority of NMI pin input non-maskable interrupts and watchdog timer overflow nonmaskable interrupts. WDM can be written to only by a dedicated instruction. This dedicated instruction, MOV WDM, #byte, has a special code configuration (4 bytes), and a write is not performed unless the 3rd and 4th bytes of the operation code are mutual complements of 1. If the 3rd and 4th bytes of the operation code are not complements of 1, a write is not performed and an operand error interrupt is generated. In this case, the return address saved in the stack area is the address of the instruction that was the source of the error, and thus the address that was the source of the error can be identified from the return address saved in the stack area. If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result. As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC assembler, RA78K4, only the correct dedicated instruction is generated when MOV WDM, #byte is written), system initialization should be performed by the program. Other write instructions (MOV WDM, A, AND WDM, #byte instruction, SET1 WDM.7, etc.) are ignored and do not perform any operation. That is, a write is not performed to the WDM, and an interrupt such as an operand error interrupt is not generated. WDM can be read at any time by a data transfer instruction. RESET input clears WDM to 00H. Figure 23-5. Watchdog Timer Mode Register (WDM) Format
7 WDM RUN 6 0 5 0 4 PRC 3 0 2 WDI2 1 WDI1 0 0 Address 0FFC2H After reset 00H R/W R/W
See Figure 13-2 in CHAPTER 13 WATCHDOG TIMER FUNCTION for details. Watchdog Timer Interrupt Request Priority Specification Watchdog timer interrupt request < NMI pin input interrupt request Watchdog timer interrupt request > NMI pin input interrupt request
PRC 0 1
Caution The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV WDM, #byte).
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23.3.6 Program status word (PSW) PSW is a register that holds the current status regarding instruction execution results and interrupt requests. The IE flag that sets enabling/disabling of maskable interrupts is mapped in the low-order 8 bits of the PSW (PSWL). PSWL can be read or written to with an 8-bit manipulation instruction, and can also be manipulated with a bit manipulation instruction or dedicated instruction (EI/DI). When a vectored interrupt is acknowledged or a BRK instruction is executed, PSWL is saved to the stack and the IE flag is cleared (to 0). PSWL is also saved to the stack by the PUSH PSW instruction, and is restored from the stack by the RETI, RETB and POP PSW instructions. When context switching or a BRKCS instruction is executed, PSWL is saved to a fixed area in the register bank, and the IE flag is cleared (to 0). PSWL is restored from the fixed area in the register bank by an RETCSI or RETCSB instruction. RESET input clears PSWL to 00H.
Figure 23-6. Program Status Word (PSWL) Format
7 PSWL S 6 Z 5 RSS 4 AC 3 IE 2 P/V 1 0 0 CY After reset 00H Used in normal instruction execution IE 0 1 Interrupt Acknowledgment Enabling/Disabling Disabled Enabled
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23.4 Software Interrupt Acknowledgment Operations A software interrupt is acknowledged in response to execution of a BRK or BRKCS instruction. Software interrupts cannot be disabled. 23.4.1 BRK instruction software interrupt acknowledgment operation When a BRK instruction is executed, the program status word (PSW), program counter (PC) are saved in that order to the stack, the IE flag is cleared (to 0), the vector table (003EH/003FH) contents are loaded into the low-order 16 bits of the PC, and 0000B into the high-order 4 bits, and a branch is performed (the start of the service program must be in the base area). The RETB instruction must be used to return from a BRK instruction software interrupt. Caution The RETI instruction must not be used to return from a BRK instruction software interrupt. 23.4.2 BRKCS instruction software interrupt (software context switching) acknowledgment operation The context switching function can be initiated by executing a BRKCS instruction. The register bank to be used after context switching is specified by the BRKCS instruction operand. When a BRKCS instruction is executed, the program branches to the start address of the interrupt service program (which must be in the base area) stored beforehand in the specified register bank, and the contents of the program status word (PSW) and program counter (PC) are saved in the register bank. Figure 23-7. Context Switching Operation by Execution of a BRKCS Instruction
0000B 7 Transfer PC19 to16 PC15 to 0 6 Exchange 2 Save (bits 8 to 11 of temporary register) Register bank n (n = 0 to 7) A B R5 R7 5 Save Temporary register 1 Save PSW V U T W D H VP UP E L X C R4 R6
Register bank (0 to 7)
3 Register bank switching (RBS0 to RBS2 n) 4 RSS 0 E 0
(I
)
The RETCSB instruction is used to return from a software interrupt due to a BRKCS instruction. The RETCSB instruction must specify the start address of the interrupt service program for the next time context switching is performed by a BRKCS instruction. This interrupt service program start address must be in the base area. Caution The RETCS instruction must not be used to return from a BRKCS instruction software interrupt.
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Figure 23-8. Return from BRKCS Instruction Software Interrupt (RETCSB instruction operation)
Register bank n (n = 0 to 7) PC19 to 16 PC15 to 0 1 Restoration 2 Restoration A B R5 R7 V 4 Restoration (to original register bank) PSW U T W D H VP UP E L X C R4 R6 3 Transfer RETCSB instruction operand
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23.5 Operand Error Interrupt Acknowledgment Operation An operand error interrupt is generated when the data obtained by inverting all the bits of the 3rd byte of the operand of a "MOV STBC, #byte instruction "," LOCATION instruction" or a "MOV WDM, #byte instruction" does not match the 4th byte of the operand. Operand error interrupts cannot be disabled. When an operand error interrupt is generated, the program status word (PSW) and the start address of the instruction that caused the error are saved to the stack, the IE flag is cleared (to 0), the vector table value is loaded into the program counter (PC), and a branch is performed (within the base area only). As the address saved to the stack is the start address of the instruction in which the error occurred, simply writing an RETB instruction at the end of the operand error interrupt service program will result in generation of another operand error interrupt. You should therefore either process the address in the stack or initialize the program by referring to 23.12 Restoring Interrupt Function to Initial State. 23.6 Non-Maskable Interrupt Acknowledgment Operation Non-maskable interrupts are acknowledged even in the interrupt disabled state. Non-maskable interrupts can be acknowledged at all times except during execution of the service program for an identical non-maskable interrupt or a nonmaskable interrupt of higher priority. The relative priorities of non-maskable interrupts are set by the PRC bit of the watchdog timer mode register (WDM) (see 23.3.5 Watchdog timer mode register (WDM)). Except in the cases described in 23.9 When Interrupt Requests and Macro Service are Temporarily Held Pending, a non-maskable interrupt request is acknowledged immediately. When a non-maskable interrupt request is acknowledged, the program status word (PSW) and program counter (PC) are saved in that order to the stack, the IE flag is cleared (to 0), the in-service priority register (ISPR) bit corresponding to the acknowledged non-maskable interrupt is set (to 1), the vector table contents are loaded into the PC, and a branch is performed. The ISPR bit that is set (to 1) is the NMIS bit in the case of a non-maskable interrupt due to edge input to the NMI pin, and the WDTS bit in the case of watchdog timer overflow. When the non-maskable interrupt service program is executed, non-maskable interrupt requests of the same priority as the non-maskable interrupt currently being executed and non-maskable interrupts of lower priority than the non-maskable interrupt currently being executed are held pending. A pending non-maskable interrupt is acknowledge after completion of the non-maskable interrupt service program currently being executed (after execution of the RETI instruction). However, even if the same non-maskable interrupt request is generated more than once during execution of the non-maskable interrupt service program, only one non-maskable interrupt is acknowledged after completion of the non-maskable interrupt service program.
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Figure 23-9. Non-Maskable Interrupt Request Acknowledgment Operations (1/2) (a) When a new NMI request is generated during NMI service program execution
Main routine
(NMIS = 1)
NMI request
NMI request
NMI request held pending since NMIS = 1
Pending NMI request is processed
(b) When a watchdog timer interrupt request is generated during NMI service program execution (when the watchdog timer interrupt priority is higher (when PRC in the WDM = 1))
Main routine
NMI request
Watchdog timer interrupt request
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Figure 23-9. Non-Maskable Interrupt Request Acknowledgment Operations (2/2) (c) When a watchdog timer interrupt request is generated during NMI service program execution (when the NMI interrupt priority is higher (when PRC in the WDM = 0))
Main routine
NMI request
Watchdog timer interrupt request
Watchdog timer interrupt held pending since PRC = 0
Pending watchdog timer interrupt is processed
(d) When an NMI request is generated twice during NMI service program execution
Main routine
NMI request NMI request NMI request
Held pending since NMI service program is being executed
Held pending since NMI service program is being executed
NMI request was generated more than once, but is only acknowledged once
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Cautions 1. Macro service requests are acknowledged and serviced even during execution of a non-maskable interrupt service program. If you do not want macro service processing to be performed during a non-maskable interrupt service program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent macro service generation. 2. The RETI instruction must be used to return from a non-maskable interrupt. Subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. 3. Non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program execution (except when a high non-maskable interrupt request is generated during execution of a low-priority non-maskable interrupt service program) and for a certain period after execution of the special instructions shown in 23.9 When Interrupt Requests and Macro Service are Temporarily Held Pending. Therefore, a non-maskable interrupt will be acknowledged even when the stack pointer (SP) value is undefined, in particular after reset release, etc. In this case, depending on the value of the SP, it may happen that the program counter (PC) and program status word (PSW) are written to the address of a write-inhibited special function register (SFR) (see Table 3-5 in 3.9 Special Function Registers (SFR)), and the CPU becomes deadlocked, or an unexpected signal is output from a pin, or the PC and PSW are written to an address in which RAM is not mounted, with the result that the return from the non-maskable interrupt service program to the main routine is not performed normally and an inadvertent program routine occurs. Therefore, the program following RESET release must be as shown below. CSEG AT 0 DW STRT: LOCATION 0FH; or LOCATION 0 MOVG SP, #imm24 STRT CSEG BASE
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23.7 Maskable Interrupt Acknowledgment Operation A maskable interrupt can be acknowledged when the interrupt request flag is set (to 1) and the mask flag for that interrupt is cleared (to 0). When servicing is performed by macro service, the interrupt is acknowledged and serviced by macro service immediately. In the case of vectored interruption and context switching, an interrupt is acknowledged in the interrupt enabled state (when the IE flag is set (to 1)) if the priority of that interrupt is one for which acknowledgment is permitted. If maskable interrupt requests are generated simultaneously, the interrupt for which the highest priority is specified by the priority specification flag is acknowledged. If the interrupts have the same priority specified, they are acknowledged in accordance with their default priorities. A pending interrupt is acknowledged when a state in which it can be acknowledged is established. The interrupt acknowledgment algorithm is shown in Figure 23-10.
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Figure 23-10. Interrupt Acknowledgment Processing Algorithm
xxIF = 1 Yes
No Interrupt request?
xxMK = 0 Yes Yes
No Interrupt mask released?
xxISM = 1 No
Macro service?
No
Highest default priority among macro service requests? Yes Macro service processing execution
IE = 1 Yes
No Interrupt enabled state?
Higher priority than interrupt currently being serviced? Yes
No
Interrupt request held pending
Higher priority than other existing interrupt requests? Yes Highest default priority among interrupt requests of same priority? Yes xxCSE = 1 No Vectored interrupt generation Yes
No
No
Interrupt request held pending
Context switching?
Context switching generation
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23.7.1 Vectored interrupt When a vectored interrupt maskable interrupt request is acknowledged, the program status word (PSW) and program counter (PC) are saved in that order to the stack, the IE flag is cleared (to 0) (the interrupt disabled state is set), and the in-service priority register (ISPR) bit corresponding to the priority of the acknowledged interrupt is set (to 1). Also, data in the vector table predetermined for each interrupt request is loaded into the PC, and a branch is performed. The return from a vectored interrupt is performed by means of the RETI instruction. Caution When a maskable interrupt is acknowledged by vectored interrupt, the RETI instruction must be used to return from the interrupt. Subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. 23.7.2 Context switching Initiation of the context switching function is enabled by setting (to 1) the context switching enable flag of the interrupt control register. When an interrupt request for which the context switching function is enabled is acknowledged, the register bank specified by 3 bits of the lower address (even address) of the corresponding vector table address is selected. The vector address stored beforehand in the selected register bank is transferred to the program counter (PC), and at the same time the contents of the PC and program status word (PSW) up to that time are saved in the register bank and a branch is made to the interrupt service program. Figure 23-11. Context Switching Operation by Generation of an Interrupt Request
3 Register bank switching (RBS0 to RBS2 n) Vector table n
0000B 7 Transfer PC19 to 16 PC15 to 0 6 Exchange 2 Save (temporary register bits 8 to 11) Register bank n (n = 0 to 7) A B R5 R7 5 Save Temporary register 1 Save PSW V U T W D H VP UP E L 4 RSS 0 E 0) X C R4 R6
Register bank (0 to 7)
(I
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The RETCS instruction is used to return from an interrupt that uses the context switching function. The RETCS instruction must specify the start address of the interrupt service program to be executed when that interrupt is acknowledged next. This interrupt service program start address must be in the base area. Caution The RETCS instruction must be used to return from an interrupt serviced by context switching. Subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. Figure 23-12. Return from Interrupt that Uses Context Switching by Means of RETCS Instruction
Register bank n (n = 0 to 7) PC19 to 16 PC15 to 0 1 Restoration 2 Restoration A B R5 R7 V 4 Restoration (to original register bank) PSW U T W D H VP UP E L X C R4 3 Transfer R6 RETCS instruction operand
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23.7.3 Maskable interrupt priority levels The PD784938 performs multiple interrupt servicing in which an interrupt is acknowledged during servicing of another interrupt. Multiple interrupts can be controlled by priority levels. There are two kinds of priority control, control by default priority and programmable priority control in accordance with the setting of the priority specification flag. In priority control by means of default priority, interrupt service is performed in accordance with the priority preassigned to each interrupt request (default priority) (see Table 23-2). In programmable priority control, interrupt requests are divided into four levels according to the setting of the priority specification flag. Interrupt requests for which multiple interruption is permitted are shown in Table 23-5. Since the IE flag is cleared (to 0) automatically when an interrupt is acknowledged, when multiple interruption is used, the IE flag should be set (to 1) to enable interrupts by executing an EI instruction in the interrupt service program, etc. Table 23-5. Multiple Interrupt Servicing
Priority of Interrupt Currently Being Acknowledged No interrupt being acknowledged 3 00001000 ISPR Value IE Flag in PSW PRSL Flag in IMC x x x 0 1 * * * * * * Acknowledgeable Maskable Interrupts
00000000
0 1 0 1 1
All macro service only All maskable interrupts All macro service only All maskable interrupts All macro service Maskable interrupts specified as priority 0/1/2 All macro service only All macro service Maskable interrupts specified as priority 0/1 All macro service only All macro service Maskable interrupts specified as priority 0 All macro service only All macro service only
2
0000x100
0 1
x x
* * *
1
0000xx10
0 1
x x
* * *
0 Non-maskable interrupts
0000xxx1 1000xxxx 0100xxxx 1100xxxx
x x
x x
* *
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Figure 23-13. Examples of Servicing when Another Interrupt Request is Generated During Interrupt Service (1/3)
Main routine a servicing EI Interrupt request a (level 3) EI Interrupt request b (level 2) b servicing
Since interrupt request b has a higher priority than interrupt request a, and interrupts are enabled, interrupt request b is acknowledged.
c servicing
Interrupt request c (level 3)
Interrupt request d (level 2)
d servicing
The priority of interrupt request d is higher than that of interrupt request c, but since interrupts are disabled, interrupt request d is held pending.
e servicing EI Interrupt request e (level 2) Interrupt request f (level 3) f servicing Although interrupts are enabled, interrupt request f is held pending since it has a lower priority than interrupt request e.
g servicing Interrupt request h (level 1) EI Although interrupts are enabled, interrupt request h is held pending since it has the same priority as interrupt request g. h servicing
Interrupt request g (level 1)
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Figure 23-13. Examples of Servicing when Another Interrupt Request is Generated During Interrupt Service (2/3)
Main routine i servicing EI Interrupt request i (level 1) Macro service request j (level 2) j macro service The macro service request is serviced irrespective of interrupt enabling/disabling and priority.
k servicing Interrupt request l (level 3) Interrupt request m (level 1) EI m servicing The interrupt request is held peding since it has a lower priority than interrupt request k. Interrupt request m generated after interrupt request l has a higher priority, and is therefore acknowledged first. l servicing
Interrupt request k (level 2)
n servicing
Interrupt request n (level 2)
Interrupt request o (level 3) Interrupt request p (level 1) p servicing
o servicing
Since servicing of interrupt request n performed in the interrupt disabled state, interrupt requests o and p are held pending. After interrupt request n servicing, the pending interrupt requests are acknowledged. Although interrupt request o was generated first, interrupt request p has a higher priority and is therefore acknowledged first.
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Figure 23-13. Examples of Servicing when Another Interrupt Request is Generated During Interrupt Service (3/3)
Main routine q servicing EI Interrupt request q (level 3) Interrupt request r (level 2) EI Interrupt request s (level 1) EI Interrupt request t (level 0) r servicing EI EI s servicing t servicing Multiple acknowledgment of levels 3 to 0. If the PRSL bit of the IMC register is set (to 1), only macro service requests and nonmaskable interrupts generate nesting beyond this. If the PRSL bit of the IMC register is cleared (to 0), level 3 interrupts can also be nested during level 3 interrupt servicing (see Figure 23-15).
u servicing EI Interrupt request v (level 0) Interrupt request w (level 3) v servicing Even though the interrupt enabled state is set during servicing of level 0 interrupt request u, the interrupt request is not acknowledged but held pending even though its priority is 0. However, the macro service request is acknowledged and serviced irrespective of its level and even though there is a peding interrupt with a higher priority level.
Interrupt request u (level 0)
w macro service
Interrupt request x (level 1)
Interrupt request yNote (level 2) Interrupt request zNote (level 2)
x servicing Pending interrupt requests y and z are acknowledged after servicing of interrupt request x. As interrupt requests y and z have the same priority level, interrupt request z which has the higher default priority is acknowledged first, irrespective of the order in which the interrupt requests were generated.
z servicing
y servicing
Notes 1. Low default priority 2. High default priority Remarks 1. "a" to "z" in the figure are arbitrary names used to differentiate between the interrupt requests and macro service requests. 2. High/low default priorities in the figure indicate the relative priority levels of the two interrupt requests.
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Figure 23-14. Examples of Servicing of Simultaneously Generated Interrupts
Main routine EI
Interrupt request a (level 2) Macro service request b (level 3) Macro service request c (level 1) Interrupt request d (level 1) Interrupt request e (level 1) Macro service request f (level 1)
Macro service request b servicing Macro service request c servicing Macro service request f servicing Interrupt request d servicing
Interrupt request e servicing
Default priority order a>b>c>d>e>f
Interrupt request a servicing
* When requests are generated simultaneously, they are acknowledged in the order starting with macro service. * Macro service requests are acknowledged in default priority order (b/c/f) (not dependent upon the programmable priority order). * As interrupt requests are acknowledged in high-to-low priority level order, d and e are acknowledged first. * As d and e have the same prority level, the interrupt request with the higher default priority, d, is acknowledged first.
Remark "a" to "f" in the figure are arbitrary names used to differentiate between the interrupt requests and macro service requests.
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Figure 23-15. Differences in Level 3 Interrupt Acknowledgment According to IMC Register Setting
Main routine The PRSL bit of the IMC is set to 1, and nesting between level 3 interrupts is disabled.
IMC 80H EI EI Interrupt request a (level 3) Interrupt request b (level 3)
a servicing
Even though interrupts are enabled, interrupt request b is held pending since it has the same priority as interrupt request a. b servicing
Main routine The PRSL bit of the IMC is set to 0, so that a level 3 interrupt is acknowledged even during level 3 interrupt servicing (nesting is possible).
IMC 00H EI c servicing
EI Interrupt request c (level 3) Interrupt request d (level 3)
d servicing Since level 3 interrupt request c is being serviced in the interrupt enabled state and PRSL = 0, interrupt request d, which is also level 3, is acknowledged.
Main routine
IMC 00H As interrupt requests e and f are the same level, the one with the higher default priority, f, is acknowledged first. When the interrupt enabled state is set during servicing of interrupt request f, pending interrupt request e is acknowledged since PRSL = 0.
Interrupt request e (level 3) Interrupt request f (level 3)
Note1
Note2
f servicing EI EI e servicing
Notes 1. Low default priority 2. High default priority Remarks 1. "a" to "f" in the figure are arbitrary names used to differentiate between the interrupt requests and macro service requests. 2. High or low in default priorities in the figure indicate the relative priority levels of the two interrupt requests.
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23.8 Macro Service Function 23.8.1 Outline of macro service function Macro service is one of the method of interrupts servicing. In the normal interrupt, the start address in the interrupt service program is loaded into the program counter (PC) by saving the PC or program status word (PSW), in the macro service, however, another processing (mainly data transfers) is performed instead of these processing. This processing enables a quick response to interrupt requests. Moreover, processing time can be reduced because the higher transfer speed can be obtained. In addition, there is another advantage in simplifying the vectored interrupt program since the vectored interrupt is generated after the specified number of processing. Figure 23-16. Differences between Vectored Interrupt and Macro Service Processing
Macro service
Main routine
Macro service processing
Main routine
Context switchingNote 1
Main routine
Note 2
Interrupt servicing
Note 3
Main routine
Vectored interruptNote 1
Main routine
Note 4
SEL RBn
Interrupt servicing
Restore PC, PSW
Main routine
Vectored interrupt
Main routine
Note 4
Save general registers
Initialize general registers
Interrupt servicing
Restore general registers
Restore PC & PSW
Main routine
Interrupt request generation
Notes 1. When register bank switching is used, and an initial value has been set in the register beforehand 2. Register bank switching by context switching, saving of PC and PSW 3. Register bank, PC and PSW restoration by context switching 4. PC and PSW saved to the stack, vector address loaded into PC 23.8.2 Types of macro service Macro service can be used with the 23 kinds of interrupt shown in Table 23-6. There are four kinds of operation, which can be used to suit the application.
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Table 23-6. Interrupts for which Macro Service can be Used
Default Priority 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Interrupt Request Generation Source Generating Unit Macro Service Control Word Address 0FE06H 0FE08H 0FE0AH 0FE0CH Timer/event counter 0 0FE0EH 0FE10H Timer/event counter 1 0FE12H 0FE14H Timer/event counter 2 0FE16H 0FE18H Timer 3 Edge detection 0FE1AH 0FE1CH 0FE1EH A/D converter Asynchronous serial interface/ clocked serial interface 1 Clocked serial interface Asynchronous serial interface 2/ clocked serial interface 2 IEBus controller 0FE2EH 0FE26H 0FE20H 0FE24H
INTP0 (pin input edge detection) INTP1 (pin input edge detection) INTP2 (pin input edge detection) INTP3 (pin input edge detection) INTC00 (TM0-CR00 match signal generation) INTC01 (TM0-CR01 match signal generation) INTC10 (TM1-CR10 or TM1W-CR10W match signal generation) INTC11 (TM1-CR11 or TM1W-CR11W match signal generation) INTC20 (TM2-CR20 or TM2W-CR20W match signal generation) INTC21 (TM2-CR21 or TM2W-CR21W match signal generation) INTC30 (TM3-CR30 or TM3W-CR30W match signal generation) INTP4 (pin input edge detection) INTP5 (pin input edge detection) INTAD (A/D conversion end) INTSR (asynchronous serial interface reception end) INTCSI1 (clocked serial interface transfer end)
Edge detection
15
INTST (asynchronous serial interface transmission end)
16
INTCSI (clocked serial interface transfer end)
0FE28H
17
INTSR2 (asynchronous serial interface 2 reception end) INTCSI2 (clocked serial interface 2 transfer end)
0FE2CH
18
INTST2 (asynchronous serial interface 2 transmission end)
19 20 21 22
INTIE1 (IEBus data access request) INTIE2 (IEBus communication error and communication end) INTW (watch timer output) INTCSI3 (clocked serial interface 3 transfer end)
0FE32H 0FE34H
Watch timer Clocked serial interface 3
0FE36H 0FE38H
Remarks 1. The default priority is a fixed number. This indicates the order of priority when macro service requests are generated simultaneously, 2. The INTSR and INTCSI1 interrupts are generated by the same hardware (they cannot both be used simultaneously). Therefore, although the same hardware is used for the interrupts, two names are provided, for use in each of the two modes. The same applies to INTSR2 and INTCSI2.
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There are four kinds of macro service, as shown below. (1) Type A One byte or one word of data is transferred between a special function register (SFR) and memory each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed. Memory that can be used in the transfers is limited to internal RAM addresses 0FE00H to 0FEFFH when the LOCATION 0 instruction is executed, and addresses 0FFE00H to 0FFEFFH when the LOCATION 0FH instruction is executed. The specification method is simple and is suitable for low-volume, high-speed data transfers. (2) Type B As with type A, one byte or one word of data is transferred between a special function register (SFR) and memory each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed. The SFR and memory to be used in the transfers is specified by the macro service channel (the entire 1-Mbyte memory space can be used). This is a general version of type A, suitable for large volumes of transfer data. (3) Type C Data is transferred from memory to two special function registers (SFR) each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed. With type C macro service, not only are data transfers performed to two locations in response to a single interrupt request, but it is also possible to add output data ring control and a function that automatically adds data to a compare register. The entire 1-Mbyte memory space can be used. Type C is mainly used with the INTC10 and INTC11 interrupts, and is used for stepping motor control, etc., by macro service, with P0L or P0H and CR10, CR10W, CR11, and CR11W used as the SFRs to which data is transferred. (4) Counter mode This mode is to decrement the macro service counter (MSC) when an interrupt occurs and is used to count the division operation of an interrupt and interrupt generation circuit. When MSC is 0, a vector interrupt can be generated. To restart the macro service, MSC must be set again. MSC is fixed to 16 bits and cannot be used as an 8-bit counter.
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23.8.3 Basic macro service operation Interrupt requests for which the macro service processing generated by the algorithm shown in Figure 23-10 can be specified are basically serviced in the sequence shown in Figure 23-17. Interrupt requests for which macro service processing can be specified are not affected by the status of the IE flag, but are disabled by setting (to 1) an interrupt mask flag in the interrupt mask register (MK0). Macro service processing can be executed in the interrupt disabled state and during execution of an interrupt service program. Figure 23-17. Macro Service Processing Sequence
Generation of interrupt request for which macro service processing can be specified
Macro service processing execution
; Data transfer, real-time output port control
MSC MSC-1
; Decrement macro service counter (MSC)
MSC = 0? Yes Interrupt service mode bit 0
No
No
VCIE = 1?
Yes
Interrupt request flag 0
Interrupt request generation
Execute next instruction
The macro service type and transfer direction are determined by the value set in the macro service control word mode register. Transfer processing is then performed using the macro service channel specified by the channel pointer according to the macro service type. The macro service channel is memory which contains the macro service counter which records the number of transfers, the transfer destination and transfer source pointers, and data buffers, and can be located at any address in the range FE00H to FEFFH when the LOCATION 0 instruction is executed, or FFE00H to FFEFFH when the LOCATION 0FH instruction is executed.
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23.8.4 Operation at end of macro service In macro service, processing is performed the number of times specified during execution of another program. Macro service ends when the processing has been performed the specified number of times (when the macro service counter (MSC) reaches 0). Either of two operations may be performed at this point, as specified by the VCIE bit (bit 7) of the macro service mode register for each macro service. (1) When VCIE bit is 0 In this mode, an interrupt is generated as soon as the macro service ends. Figure 23-18 shows an example of macro service and interrupt acknowledgment operations when the VCIE bit is 0. This mode is used when a series of operations end with the last macro service processing performed, for instance. It is mainly used in the following cases: * Asynchronous serial interface receive data buffering (INTSR/INTSR2) * A/D conversion result fetch (INTAD) * Compare register update as the result of a match between a timer register and the compare register (INTC00/ INTC01/INTC10/INTC11/INTC20/INTC21/INTC30) * Timer/counter capture register read due to edge input to the INTPn pin (INTP0/INTP1/INTP2/INTP3) Figure 23-18. Operation at End of Macro Service when VCIE = 0
Main routine
EI
Macro service request
Macro service processing
Last macro service request
Macro service processing Servicing of interrupt request due to end of macro service
At the end of macro service (MSC = 0), an interrupt request is generated and acknowledged.
Main routine Servicing of other interrupt EI
Other interrupt request
Last macro service request
Macro service processing
Servicing of interrupt request due to end of macro service
If the last macro service is performed when the interrupt due to the end of macro service cannot be acknowledged while other interrupt servicing is being executed, tec., that interrupt is held pending until it can be acknowledged.
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(2) When VCIE bit is 1 In this mode, an interrupt is not generated after macro service ends. Figure 23-19 shows an example of macro service and interrupt acknowledgment operations when the VCIE bit is 1. This mode is used when the final operation is to be started by the last macro service processing performed, for instance. It is mainly used in the following cases: * Clocked serial interface receive data transfers (INTCSI/INTCSI1/INTCSI2) * Asynchronous serial interface data transfers (INTST/INTST2) * To stop a stepping motor in the case (INTC10/INTC11) of stepping motor control by means of macro service type C using the real-time output port and timer/counter. Figure 23-19. Operation at End of Macro Service when VCIE = 1
Main routine
EI
Macro service request
Macro service processing
Last macro service request
Processing of last macro service
Interrupt request due to the end of the hardware operation started by the last macro service processing
Interrupt servicing
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23.8.5 Macro service control registers (1) Macro service control word The PD784938's macro service function is controlled by the macro service control mode register and macro service channel pointer. The macro service processing mode is set by means of the macro service mode register, and the macro service channel address is indicated by the macro service channel pointer. The macro service mode register and macro service channel pointer are mapped onto the part of the internal RAM shown in Figure 23-20 for each macro service as the macro service control word. When macro service processing is performed, the macro service mode register and channel pointer values corresponding to the interrupt requests for which macro service processing can be specified must be set beforehand. Figure 23-20. Macro Service Control Word Format
Reserved word CSICHP3 CSIMMD3 WCHP WMMD IECHP2 IEMMD2 IECHP1 IEMMD1 Address 0FE39H 0FE38H 0FE37H 0FE36H 0FE35H 0FE34H 0FE33H 0FE32H Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register

Source INTCSI3 INTW INTIE2 INTIE1
STCHP2 STMMD2 SRCHP2/CSICHP2 SRMMD2/CSIMMD2
0FE2FH 0FE2EH 0FE2DH 0FE2CH
Channel pointer Mode register Channel pointer Mode register

INTST2 INTSR2/INTCSI2
CSICHP CSIMMD STCHP STMMD SRCHP/CSICHP1 SRMMD/CSIMMD1
0FE29H 0FE28H 0FE27H 0FE26H 0FE25H 0FE24H
Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register

INTCSI INTST INTSR/INTCSI1
ADCHP ADMMD PCHP5 PMMD5 PCHP4 PMMD4 CCHP30 CMMD30 CCHP21 CMMD21 CCHP20 CMMD20 CCHP11 CMMD11 CCHP10 CMMD10 CCHP01 CMMD01 CCHP00 CMMD00 PCHP3 PMMD3 PCHP2 PMMD2 PCHP1 PMMD1 PCHP0 PMMD0
0FE21H 0FE20H 0FE1FH 0FE1EH 0FE1DH 0FE1CH 0FE1BH 0FE1AH 0FE19H 0FE18H 0FE17H 0FE16H 0FE15H 0FE14H 0FE13H 0FE12H 0FE11H 0FE10H 0FE0FH 0FE0EH 0FE0DH 0FE0CH 0FE0BH 0FE0AH 0FE09H 0FE08H 0FE07H 0FE06H
Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register

INTAD INTP5 INTP4 INTC30 INTC21 INTC20 INTC11 INTC10 INTC01 INTC00 INTP3 INTP2 INTP1 INTP0
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(2) Macro service mode register The macro service mode register is an 8-bit register that specifies the macro service operation. This register is written in internal RAM as part of the macro service control word (see Figure 23-20). The format of the macro service mode register is shown in Figure 23-21. Figure 23-21. Macro Service Mode Register Format (1/2)
7 6 5 4 3 2 1 0
VCIE MOD2 MOD1 MOD0 CHT3 CHT2 CHT1 CHT0
CHT0 CHT1 CHT2 CHT3 MOD2 MOD1 MOD0 0 0 0
0 0 0 0 Counter Mode Counter decrement
1 0 0 0 Type A Data transfer Data size: direction 1 byte Memory SFR Data transfer direction SFR memory
0 0 0 1 Type B Data transfer direction Memory SFR Data transfer direction SFR memory Data size: 1 byte
0
0
1
0 0 1
1 1 0
0 1 0 Data transfer Data size: direction 2 bytes Memory SFR Data transfer direction SFR memory Data transfer direction Memory SFR Data transfer direction SFR memory Data size: 2 bytes
1
0
1
1 1 VCIE 0 1
1 1
0 1 Interrupt Request when MSC = 0
Generated Not generated (next interrupt processing is vectored interrupt)
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Figure 23-21. Macro Service Mode Register Format (2/2)
7 6 5 4 3 2 1 0
VCIE MOD2 MOD1 MOD0 CHT3 CHT2 CHT1 CHT0
CHT0 CHT1 CHT2 CHT3 MOD2 MOD1 MOD0
0 0 1 1
1 0 1 1 Type C
0 1 1 1
1 1 1 1
Decrements MPD Retains MPT 0 0 0 0 1 1 1 1 VCIE 0 1 Generated 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Data size for timer specified by MPT: 2 bytes Decrements MPT No automatic addition Automatic addition No automatic addition Automatic addition
Increments MPD Retains MPT Increments MPT
Data size for timer specified by MPT: 1 byte
No ring control Ring control No ring control Ring control No ring control Ring control No ring control Ring control
Interrupt Request when MSC = 0
Not generated (next interrupt processing is vectored interrupt)
(3) Macro service channel pointer The macro service channel pointer specifies the macro service channel address. The macro service channel can be located in the 256-byte space from FE00H to FEFFH when the LOCATION 0 instruction is executed, or FFE00H to FFEFFH when the LOCATION 0FH instruction is executed, and the high-order 16 bits of the address are fixed. Therefore, the low-order 8 bits of the data stored to the highest address of the macro service channel are set in the macro service channel pointer.
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23.8.6 Macro service type A (1) Operation Data transfers are performed between buffer memory in the macro service channel and an SFR specified in the macro service channel. With type A, the data transfer direction can be selected as memory-to-SFR or SFR-to-memory. Data transfers are performed the number of times set beforehand in the macro service counter. One macro service processing transfers 8-bit or 16-bit data. Type A macro service is useful when the amount of data to be transferred is small, as transfers can be performed at high speed.
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Figure 23-22. Macro Service Data Transfer Processing Flow (Type A)
Macro service request acknowledgment Read contents of macro service mode register
Determine channel type TYPE A Read channel pointer contents (m) Read MSC contents (n) Calculate buffer addressNote Read SFR pointer contents
Other To other macro service processing
Note 1-byte transfer: m-n-1 2-byte transfer: m-n x 2-1
Determine transfer direction
SFR Memory
Memory SFR Read buffer contents, then transfer read data to specified SFR Specified SFR contents, then transfer read data to buffer
MSC MSC-1
MSC = 0? Yes
No
Clear (to 0) interrupt service mode bit (ISM)
VCIE = 1? No
Yes
Clear (to 0) interrupt request flag (IF)
End (Vectored interrupt request generation)
End
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(2) Macro service channel configuration The channel pointer and 8-bit macro service counter (MSC) indicate the buffer address in internal RAM (FE00H to FEFFH when the LOCATION 0 instruction is executed, or FFE00H to FFEFFH when the LOCATION 0FH instruction is executed) which is the transfer source or transfer destination (see Figure 23-23). In the channel pointer, the loworder 8 bits of the address are written to the macro service counter in the macro service channel. The SFR involved with the access is specified by the SFR pointer (SFRP). The low-order 8 bits of the SFR address are written to the SFRP.
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Figure 23-23. Type A Macro Service Channel (a) 1-byte transfers
7 Macro service channel 0 High-order addresses
Macro service counter (MSC) SFR pointer (SFRP) Macro service buffer 1 Macro service buffer 2 MCS = 1 MCS = 2
Macro service buffer n
MCS = n
Macro service control word

Channel pointer Mode register Low-order addresses
Macro service buffer address = (channel pointer) - (macro service counter) - 1
(b) 2-byte transfers
7 Macro service channel Macro service counter (MSC) SFR pointer (SFRP) Macro service (high-order byte) buffer 1 (low-order byte) (high-order byte) Macro service buffer 2 (low-order byte) MCS = 1 0 High-order addresses
MCS = 2
Macro service buffer n
(high-order byte) MCS = n (low-order byte)
Macro service control word

Channel pointer Mode register Low-order addresses
Macro service buffer address = (channel pointer) - (macro service counter) x 2 - 1
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(3) Example of use of type A An example is shown below in which data received via the asynchronous serial interface is transferred to a buffer area in on-chip RAM. Figure 23-24. Asynchronous Serial Reception
(Internal RAM)
0FE7FH
MSC 0EH SFRP 8CHNote
-1 Note Low-order 8 bits of RXB address
0FE70H
Channel pointer 7FH Mode register 11H Type A, SFR memory, 8-bit transfer, interrupt request generation when MSC = 0
Internal bus
Receive buffer (RXB)
RXD/P30
Shift register
INTSR macro service request
Remark Addresses in the figure are the values when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values in the figure.
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23.8.7 Macro service type B (1) Operation Data transfers are performed between a data area in memory and an SFR specified by the macro service channel. With type B, the data transfer direction can be selected as memory-to-SFR or SFR-to-memory. Data transfers are performed the number of times set beforehand in the macro service counter. One macro service processing transfers 8-bit or 16-bit data. This type of macro service is macro service type A for general purposes and is ideal for processing a large amount of data because up to 64 Kbytes of data buffer area when 8-bit data is transferred or 1 Mbyte of data buffer area when 16-bit data is transferred can be set in any address space.
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Figure 23-25. Macro Service Data Transfer Processing Flow (Type B)
Macro service request acknowledgment Read contents of macro service mode register
Determine channel type TYPE B Read channel pointer contents (m)
Other To other macro service processing
Determine transfer direction Memory SFR Select transfer source SFR with SFR pointer Read data from SFR, and write to memory addressed by MP
SFR Memory
Select transfer source memory with macro service pointer (MS) Read data from memory, and write to SFR specified by SFR pointer
Increment MPNote MSC MSC-1
Note 1-byte transfer: +1 2-byte transfer: +2
MSC = 0? Yes
No
Clear (to 0) interrupt service mode bit (ISM)
VCIE = 1? No
Yes
Clear (to 0) interrupt request flag (IF)
End (Vectored interrupt request generation)
End
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(2) Macro service channel configuration The macro service pointer (MP) indicates the data buffer area in the 1-Mbyte memory space that is the transfer destination or transfer source. The low-order 8 bits of the SFR that is the transfer destination or transfer source is written to the SFR pointer (SFRP). The macro service counter (MSC) is a 16-bit counter that specifies the number of data transfers. The macro service channel that stores the MP, SFRP and MSC is located in internal RAM space addresses 0FE00H to 0FEFFH when the LOCATION 0 instruction is executed, or 0FFE00H to 0FFEFFH when the LOCATION 0FH instruction is executed. The macro service channel is indicated by the channel pointer as shown in Figure 23-26. In the channel pointer, the low-order 8 bits of the address are written to the macro service counter in the macro service channel. Figure 23-26. Type B Macro Service Channel
High-order addresses Macro service counter (MSC)
(bits 8 to 15) (bits 0 to 7)
SFR
Macro service channel
SFR pointer (SFRP) (bits 16 to 23)Note Macro service pointer (MP) (bits 8 to 15) (bits 0 to 7) Buffer area
Macro service control word Low-order addresses
Channel pointer Mode register
Macro service buffer address = macro service pointer
Note Bits 20 to 23 must be set to 0.
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(3) Example of use of type B An example is shown below in which parallel data is input from port 3 in synchronization with an external signal. The INTP4 external interrupt pin is used for synchronization with the external signal. Figure 23-27. Parallel Data Input Synchronized with External Interrupts
Macro service control word, Macro service channel (internal RAM)
64 K memory space
00H MSC 0A01FH 0FE6EH SFRP Buffer Area MP 0A000H 20H 03H
Note
-1 Note Low-order 8 bits of port 3 address
00H A0H 00H +1
Channel pointer 6EH Type B, SFR memory, 8-bit transfer, Mode register 18H interrupt request generation when MSC = 0
Internal bus
INTP4
Edge detection
INTP4 Macro service request
Port 3 P37 P36 P35 P34 P33 P32 P31 P30
Remark Macro service channel addresses in the figure are the values when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values in the figure.
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Figure 23-28. Parallel Data Input Timing
Port 3
INTP4
Data fetch (macro service)
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23.8.8 Macro service type C (1) Operation In type C macro service, data in the memory specified by the macro service channel is transferred to two SFRs, for timer use and data use, specified by the macro service channel in response to a single interrupt request (the SFRs can be freely selected). An 8-bit or 16-bit timer SFR can be selected. In addition to the basic data transfers described above, type C macro service, the following functions can be added to type C macro service to reduce the size of the buffer area and alleviate the burden on software. These specifications are made by using the mode register of the macro service control word. (a) Updating of timer macro service pointer It is possible to choose whether the timer macro service pointer (MPT) is to be kept as it is or incremented/ decremented. The MPT is incremented or decremented in the same direction as the macro service pointer (MPD) for data. (b) Updating of data macro service pointer It is possible to choose whether the data macro service pointer (MPD) is to be incremented or decremented. (c) Automatic addition The current compare register value is added to the data addressed by the timer macro service pointer (MPT), and the result is transferred to the compare register. If automatic addition is not specified, the data addressed by the MPT is simply transferred to the compare register. (d) Ring control An output data pattern of the length specified beforehand is automatically output repeatedly.
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Figure 23-29. Macro Service Data Transfer Processing Flow (Type C) (1/2)
Macro service request acknowledgment Read contents of macro service mode register
Determine channel type TYPE C Read channel pointer contents (m) Read memory addressed by MPT
Other To other macro service processing
Automatic addition specified? No Transfer data to compare register
Yes
Add data to compare register
Retain MPT? No
Yes
No
Increment MPT?
Yes Decrement MPT Increment MPTNote Note 1-byte transfer: +1 2-byte transfer: +2
Read memory addressed by MPD
Transfer data to buffer register
No
Increment MPD? Yes
Decrement MPD (-1)
Increment MPD (+1)
1
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Figure 23-29. Macro Service Data Transfer Processing Flow (Type C) (2/2)
1
Ring control? Yes Decrement ring counter
No
Ring counter = 0? Yes
No
Increment MPD? Yes Subtract modulo register contents from data macro service pointer (MPD), and return pointer to start address
No
Add modulo register contents to data macro service pointer (MPD), and return pointer to start address
Load modulo register contents into ring counter
MSC MSC-1
MSC = 0? Yes Clear (to 0) interrupt service mode bit (ISM)
No
VCIE = 1? No
Yes
Clear (to 0) interrupt request flag (IF)
End (Vectored interrupt request generation)
End
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(2)
Macro service channel configuration There are two kinds of type C macro service channel, as shown in Figure 23-30. The timer macro service pointer (MPT) mainly indicates the data buffer area in the 1-Mbyte memory space to be transferred or added to the timer/event counter compare register. The data macro service pointer (MPD) indicates the data buffer area in the 1-Mbyte memory space to be transferred to the real-time output port. The modulo register (MR) specifies the number of repeat patterns when ring control is used. The ring counter (RC) holds the step in the pattern when ring control is used. When initialization is performed, the same value as in the MR is normally set in this counter. The macro service counter (MSC) is a 16-bit counter that specifies the number of data transfers. The low-order 8 bits of the SFR that is the transfer destination is written to the timer SFR pointer (TSFRP) and data SFR pointer (DSFRP). The macro service channel that stores these pointers and counters is located in internal RAM space addresses 0FE00H to 0FEFFH when the LOCATION 0 instruction is executed, or 0FFE00H to 0FFEFFH when the LOCATION 0FH instruction is executed. The macro service channel is indicated by the channel pointer as shown in Figure 23-30. In the channel pointer, the low-order 8 bits of the address are written to the macro service counter in the macro service channel. Figure 23-30. Type C Macro Service Channel (1/2) (a) No ring control
High-order addresses Macro service counter (MSC)
(bits 8 to 15) (bits 0 to 7)
TSFR
Timer SFR pointer (TSFRP) (bits 16 to 23)Note Timer macro service (bits 8 to 15) pointer (MPT) (bits 0 to 7) Data SFR pointer (DSFRP) (bits 16 to 23)Note Data macro service pointer (MPD) (bits 8 to 15)
DSFR
Timer buffer area
Macro service channel
Data buffer area (bits 0 to 7)
Macro service control word
Channel pointer Mode register
Low-order addresses Macro service buffer address = macro service pointer
Note Bits 20 to 23 must be set to 0.
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Figure 23-30. Type C Macro Service Channel (2/2) (b) With ring control
High-order addresses Macro service counter (MSC)
(bits 8 to 15) (bits 0 to 7)
TSFR
Timer SFR pointer (TSFRP) (bits 16 to 23)Note Timer macro service pointer (MPT) Macro service channel
DSFR
Timer buffer area (bits 8 to 15) (bits 0 to 7)
Data SFR pointer (DSFRP) (bits 16 to 23)Note Data macro service pointer (MPD) (bits 8 to 15) (bits 0 to 7) Modulo register (MR) Ring counter (RC) Data buffer area
Macro service control word
Channel pointer Mode register
Low-order addresses Macro service buffer address = macro service pointer
Note Bits 20 to 23 must be set to 0. (3) Examples of use of type C (a) Basic operation An example is shown below in which the output pattern to the real-time output port and the output interval are directly controlled. Update data is transferred from the two data storage areas set in the 1-Mbyte space beforehand to the real-time output function buffer register (P0L) and the compare register (CR10).
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Figure 23-31. Stepping Motor Open Loop Control by Real-Time Output Port
1 M memory space
Macro service control word, macro service channel (internal RAM)
00H MSC 123411H Output timing data area 123409H 123408H T9 ... 0FE5EH TSFRP 04H
-1
T2 T1 D9 ... DSFRP MPT
14H Low-order 8 bits of CR10 address 12H 34H 09H 0EH Low-order 8 bits of P0L address 12H 34H 00H +1 +1
Output data area D2 123400H D1 MPD
Channel pointer Mode register
5EH Type C, MPT/MPD 0FH incremented, 1-byte timer data, no automatic addition, no ring control, interrupt request generation at MSC = 0 Internal bus
Compare register CR10
Buffer register P0L
P0 P00
INTC10 Match Real-time output trigger/ macro service start Timer counter 1 TM1
P01 Output latch P0 P02 P03
Stepping motor
Remark Internal RAM addresses in the figure are the values when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values in the figure.
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Figure 23-32. Data Transfer Control Timing
T6 T3 TM1 count value T1 0H T5 T2 T7 T4 T8
INTC10 timer interrupt
Compare register (CR10)
T1
T2
T3
T4
T5
T6
T7
T8
T9
Buffer register P0L
D1
D2
D3
D4
D5
D6
D7
D8
D9
P00
P01
P02
P03
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(b) Examples of use of automatic addition control and ring control (i) Automatic addition control The output timing data (t) specified by the macro service pointer (MPT) is added to the contents of the compare register, and the result is written back to the compare register. Use of this automatic addition control eliminates the need to calculate the compare register setting value in the program each time. (ii) Ring control With ring control, the predetermined output patterns is prepared for one cycle only, and the one-cycle data patterns are output repeatedly in order in ring form. When ring control is used, only the output patterns for one cycle need be prepared, allowing the size of the data ROM area to be reduced. The macro service counter (MSC) is decremented each time a data transfer is performed. With ring control, too, an interrupt request is generated when MSC = 0. When controlling a stepping motor, for example, the output patterns will vary depending on the configuration of the stepping motor concerned, and the phase excitation method (single-phase excitation, two-phase excitation, etc.), but repeat patterns are used in all cases. Examples of single-phase excitation and 1-2-phase excitation of a 4-phase stepping motor are shown in Figures 23-33 and 23-34.
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Figure 23-33. Single-Phase Excitation of 4-Phase Stepping Motor
1 Phase A 2 3 4 1 2 3
Phase B
Phase C
Phase D
1 cycle (4 patterns)
Figure 23-34. 1-2-Phase Excitation of 4-Phase Stepping Motor
8 Phase A 1 2 3 4 5 6 7 8 1 2 3 4 5
Phase B
Phase C
Phase D 1 cycle (8 patterns)
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Figure 23-35. Automatic Addition Control + Ring Control Block Diagram 1 (when output timing varies with 1-2-phase excitation)
Macro service control word, macro service channel (internal RAM)
1 M memory space
02H MSC 1237FEH t512 . . . t2 Output timing: 123400H t1 123007H D7 . . . Output data (8 items) D1 123000H D0 MPD 12H 30H 00H MR RC 08H 08H -1 +1 DSFRP MPT 0FE5AH TSFRP 00H 14H Low-order 8 bits of CR10 address 12H 34H 00H 0EH Low-order 8 bits of P0L address +2 -1
Channel pointer Addition Mode register
5AH 7FH Type C, MPT/MPD incremented, 2-byte timer data, automatic addition, ring control, interrupt request generation at MSC = 0
Compare register CR10W
Buffer register P0L P00 INTC10
Match Timer counter 1 TM1W
Output latch P0
P01
To stepping P02 motor P03
Remark Internal RAM addresses in the figure are the values when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values in the figure.
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Figure 23-36. Automatic Addition Control + Ring Control Timing Diagram 1 (when output timing varies with 1-2-phase excitation)
FFFFH t7 t5 TM1W count value t2 T0 0H Count start t1 t8 t9 t4 t3 t6
INTC10
Compare register (CR10W)
T0
T1 T0+t1
T2 T1+t2
T3 T2+t3
T4 T3+t4
T5 T6 T4+t5 T5+t6
T7 T6+t7
T8 T7+t8
T9 T8+t9
Buffer register P0L
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
P00
P01
P02
P03
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Figure 23-37. Automatic Addition Control + Ring Control Block Diagram 2 (1-2-phase excitation constant-velocity operation)
Macro service control word, macro service channel (internal RAM)
1 M memory space
FFH MSC Output timing: 1233FFH t 0FE7AH TSFRP FFH 14H Low-order 8 bits of CR10 address 12H 123007H D7 D6 Output data (8 Items) . . . 123000H D0 MPD DSFRP MPT 33H FFH 0EH Low-order 8 bits of P0L address 12H 30H 07H MR RC 08H 08H
Addition
Channel pointer Mode register
7AH 3CH Type C, MPT retained, MPD decremented, 1-byte timer data, automatic addition, ring control, interrupt request generation at MSC = 0
Compare register CR10
Buffer register P0L P00 INTC10
Match Timer counter 1 TM1
Output latch P0
P01
To stepping P02 motor P03
Remark Internal RAM addresses in the figure are the values when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values in the figure.
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Figure 23-38. Automatic Addition Control + Ring Control Timing Diagram 2 (1-2-phase excitation constant-velocity operation)
FFFFH
TM1 count value
t 0H Count start
INTC10
Compare register (CR10)
T0
T1 T0+t
T2 T1+t
T3 T2+t
T4 T3+t
T5 T4+t
T6 T5+t
T7 T6+t
T8 T7+t
T9 T8+t
T10 T9+t
Buffer register P0L
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
P00
P01
P02
P03
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23.8.9 Counter mode (1) Operation MSC is decremented the number of times set in advance to the macro service counter (MSC). Because the number of times an interrupt occurs can be counted, this function can be used as an event counter where the interrupt generation cycle is long. Figure 23-39. Macro Service Data Transfer Processing Flow (counter mode)
Macro service request acknowledged Reads contents of macro service mode register
Identifies channel type Counter mode MSC MSC-1
Others To other macro service processing
MSC is 16 bits wide
MSC = 0?
No
Yes
Clears interrupt processing type bit (ISM) to 0
VCIE = 1? No
Yes
Clears interrupt request flag (IF) to 0
End (Vectored interrupt request is generated)
End
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(2) Configuration of macro service channel The macro service channel consists of only a 16-bit macro service counter. The low-order 8 bits of the address of the MSC are written to the channel pointer. Figure 23-40. Counter Mode
7
Macro service High-order 8 bytes Macro service channel counter (MSC) Low-order 8 bytes
0 High-order addresses
Channel pointer Mode register Low-order addresses
(3) Example of using counter mode Here is an example of counting the number of edges input to external interrupt pin INTP5. Figure 23-41. Counting Number of Edges
(Internal RAM)
High-order 8 bytes MSC 0EH Low-order 8 bytes OFE7EH -1
Channel pointer 7EH Mode register 00H Counter mode Interrupt request is generated when MSC = 0.
Internal bus INTP5 macro service request
INTP5/P26
Remark The internal RAM address in the figure above is the value when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, add 0F0000H to this value.
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23.9 When Interrupt Requests and Macro Service are Temporarily Held Pending When the following instructions are executed, interrupt acknowledgment and macro service processing is deferred for 8 system clock cycles. However, software interrupts are not deferred. EI DI BRK BRKCS RBn RETI RETB RETCS RETCSB !addr16 POP PSW LOCATION 0H or LOCATION 0FH POPU POST MOV PSWL, A MOV PSWL, #byte MOVG SP, #imm24 Write instruction and bit manipulation instruction to an interrupt control registerNote, or the MK0, MK1, IMC or ISPR register (except BT and BF instructions) PSWL bit manipulation instruction (Excluding the BT PSWL. bit, $addr16, BF PSWL. bit, $addr16, SET1 CY, NOT1 CY, and CLR1 CY instructions) Note Interrupt control registers: PIC0, PIC1, PIC2, PIC3, PIC4, PIC5, CIC00, CIC01, CIC10, CIC11, CIC20, CIC21, CIC30, ADIC, SERIC, SRIC, CSIIC1, STIC, CSIIC, SERIC2, SRIC2, CSIIC2, STIC2, IEIC1, IEIC2, WIC, CSIIC3
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Cautions 1. When an interrupt related register is polled using a BF instruction, etc., the branch destination of that BR instruction, etc., should not be that instruction. If a program is written in which a branch is made to that instruction itself, all interrupts and macro service requests will be held pending until a condition whereby a branch is not made by that instruction arises. Bad Example LOOP : BF PIC0.7, $LOOP xxx ... Good Example (1) LOOP : NOP BF PIC0.7, $LOOP ... Good Example (2) LOOP : BT PIC0.7, $NEXT BR $LOOP ... NEXT : ... Using a BTCLR instruction instead of a BT instruction has the advantage that the flag is cleared (to 0) automatically. Interrupts and macro service requests are serviced after execution of the BR instruction, so that interrupts are never held pending for a long period. 2. For a similar reason, if problems are caused by a long pending period for interrupts and macro service when instructions to which the above applies are used in succession, a time at which interrupts and macro service requests can be acknowledged should be provided by inserting an NOP instruction, etc., in the series of instructions.
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... All interrupts and macro service requests are held pending until PIC0.7 is 1. Interrupts and macro service requests are not serviced until after execution of the instruction following the BF instruction. ... Interrupts and macro service requests are serviced after execution of the NOP instruction, so that interrupts are never held pending for a long period.
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23.10 Instructions whose Execution is Temporarily Suspended by an Interrupt or Macro Service Execution of the following instructions is temporarily suspended by an acknowledgeable interrupt request or macro service request, and the interrupt or macro service request is acknowledged. The suspended instruction is resumed after completion of the interrupt service program or macro service processing. Temporarily suspended instructions: MOVM, XCHM, MOVBK, XCHBK CMPME, CMPMNE, CMPMC, CMPMNC CMPBKE, CMPBKNE, CMPBKC, CMPBKNC SACW 23.11 Interrupt and Macro Service Operation Timing Interrupt requests are generated by hardware. The generated interrupt request sets (to 1) an interrupt request flag. When the interrupt request flag is set (to 1), a time of 8 clocks (0.64 s: fCLK = 12.58 MHz) is taken to determine the priority, etc. Following this, if acknowledgment of that interrupt or macro service is enabled, interrupt request acknowledgment processing is performed when the instruction being executed ends. If the instruction being executed is one which temporarily defers interrupts and macro service, the interrupt request is acknowledged after the following instruction (see 23.9 When Interrupt Requests and Macro Service are Temporarily Held Pending for deferred instructions). Figure 23-42. Interrupt Request Generation and Acknowledgment (unit: clocks)
Interrupt request flag
8 clocks
Instruction
Interrupt request acknowledgment processing/macro service processing
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23.11.1 Interrupt acknowledge processing time The time shown in Table 23-7 is required to acknowledge an interrupt request. After the time shown in this table has elapsed, execution of the interrupt processing program is started. Table 23-7. Interrupt Acknowledge Processing Time
(Unit: Clock = 1/fCLK) Vector Table Branch Destination Stack Vectored Interrupts Context Switching IRAM 26 IROM, PRAM IROM EMEM PRAM EMEM EMEM
PRAM 29
EMEM 37 + 4n
IRAM 27
PRAM 30
EMEM 38 + 4n
IRAM 30
PRAM 33
EMEM 41 + 4n
IRAM 31
PRAM 34
EMEM 42 + 4n
22
-
-
23
-
-
22
-
-
23
-
-
Remarks 1. IROM: internal ROM (with high-speed fetch specified) PRAM: peripheral RAM of internal RAM (only when LOCATION 0 instruction is executed in the case of branch destination) IRAM: internal high-speed RAM EMEM: internal ROM when external memory and high-speed fetch are not specified 2. n is the number of wait states per byte necessary for writing data to the stack (the number of wait states is the sum of the number of address wait states and the number of access wait states). 3. It the vector table is EMEM, and if wait states are inserted in reading the vector table, add 2 m to the value of the vectored interrupt in the above table, and add m to the value of context switching, where m is the number of wait states per byte necessary for reading the vector table. 4. It the branch destination is EMEM and if wait states are inserted in reading the instruction at the branch destination, add that number of wait states. 5. If the stack is occupied by PRAM and if the value of the stack pointer (SP) is odd, add 4 to the value in the above table. 6. The number of wait states is the sum of the number of address wait states and the number of access wait states.
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23.11.2 Processing time of macro service Macro service processing time differs depending on the type of the macro service, as shown in Table 23-8. Table 23-8. Macro Service Processing Time
(Units: Clock = 1/fCLK) Processing Type of Macro Service Data Area IRAM Type A SFR memory 1 byte 2 bytes Memory SFR 1 byte 2 bytes Type B SFR memory Memory SFR Type C Counter mode MSC 0 MSC = 0 24 25 24 26 33 34 49 17 25 Others - - - - 35 36 53 - -
Remarks 1. IRAM: internal high-speed RAM 2. In the following cases in the other data areas, add the number of clocks specified below. * If the data size is 2 bytes with IROM or IRAM, and the data is located at an odd address: 4 clocks * If the data size is 1 byte with EMEM: number of wait states for data access * If the data size is 2 bytes with EMEM: 4 + 2n (where n is the number of wait states per byte) 3. If MSC = 0 with type A, B, or C, add 1 clock. 4. With type C, add the following value depending on the function to be used and the status at that time. * Ring control: 4 clocks. Adds 7 more clocks if the ring counter is 0 during ring control.
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23.12 Restoring Interrupt Function to Initial State If an inadvertent program loop or system error is detected by means of an operand error interrupt, the watchdog timer, NMI pin input, etc., the entire system must be restored to its initial state. In the PD784938, interrupt acknowledgment related priority control is performed by hardware. This interrupt acknowledgment related hardware must also be restored to its initial state, otherwise subsequent interrupt acknowledgment control may not be performed normally. A method of initializing interrupt acknowledgment related hardware in the program is shown below. The only way of performing initialization by hardware is by RESET input. Example IRESL: CMP BZ RETI; RETVAL: DW DB DB NEXT: * It is necessary to ensure that a non-maskable interrupt request is not generated via the NMI pin during execution of this program. * After this, on-chip peripheral hardware initialization and interrupt control register initialization are performed. * When interrupt control register initialization is performed, the interrupt request flags must be cleared (to 0). LOWW (IRESL); 0 HIGHW (IRESL); LOWW & HIGHW are assembler operators for calculating low-order 16 bits & high-order 16 bits respectively of symbol NEXT Stack data to return to IRESL with RETI instruction ISPR, #0; $NEXT Forcibly change SP location Forcibly terminate running interrupt service program, return address = IRESL No interrupt service programs running? MOVW MK0, #0FFFFH; MOV MK1L, #0FFH Mask all maskable interrupts
MOVG SP, #RETVAL;
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23.13 Cautions (1) The in-service priority register (ISPR) is read-only. Writing to this register may result in misoperation. (2) The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV WDM/#byte). (3) The RETI instruction must not be used to return from a software interrupt caused by a BRK instruction. (4) The RETCS instruction must not be used to return from a software interrupt caused by a BRKCS instruction. (5) When a maskable interrupt is acknowledged by vectored interruption, the RETI instruction must be used to return from the interrupt. Subsequent interrupt related operations will not be performed normally if a different instruction is used. (6) The RETCS instruction must be used to return from a context switching interrupt. Subsequent interrupt related operations will not be performed normally if a different instruction is used. (7) Macro service requests are acknowledged and serviced even during execution of a non-maskable interrupt service program. If you do not want macro service processing to be performed during a non-maskable interrupt service program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent macro service generation. (8) The RETI instruction must be used to return from a non-maskable interrupt. Subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. (9) Non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program execution (except when a high non-maskable interrupt request is generated during execution of a low-priority non-maskable interrupt service program) and for a certain period after execution of the special instructions shown in 23.9. Therefore, a non-maskable interrupt will be acknowledged even when the stack pointer (SP) value is undefined, in particular after reset release, etc. In this case, depending on the value of the SP, it may happen that the program counter (PC) and program status word (PSW) are written to the address of a write-inhibited special function register (SFR) (see Table 3-6 in 3.9 Special Function Registers (SFR)), and the CPU becomes deadlocked, or the PC and PSW are written to an unexpected signal is output from a pin, or an address is which RAM is not mounted, with the result that the return from the non-maskable interrupt service program is not performed normally and a software upsets occurs. Therefore, the program following RESET release must be as follows. CSEG AT 0 DW STRT: LOCATION 0FH; or LOCATION 0 MOVG SP, #imm24 STRT CSEG BASE
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(10) When an interrupt related register is polled using a BF instruction, etc., the branch destination of that BR instruction, etc., should not be that instruction. If a program is written in which a branch is made to that instruction itself, all interrupts and macro service requests will be held pending until a condition whereby a branch is not made by that instruction arises. Bad Example ... LOOP: BF PIC0.7, $LOOP xxx ... Good Example (1) ... LOOP: NOP BF PIC0.7, $LOOP ... Good Example (2) LOOP: BT PIC0.7, $NEXT BR $LOOP NEXT: ... (11) For a similar reason to that given in (10), if problems are caused by a long pending period for interrupts and macro service when instructions to which the above applies are used in succession, a time at which interrupts and macro service requests can be acknowledged should be provided by inserting an NOP instruction, etc., in the series of instructions.
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All interrupts and macro service requests are held pending until PIC0.7 is 1. Interrupts and macro service requests are not serviced until after execution of the instruction following the BF instruction.
Interrupts and macro service requests are serviced after execution of the NOP instruction, so that interrupts are never held pending for a long period.
Using a BTCLR instruction instead of a BT instruction has the advantage that the flag is cleared (to 0) automatically. Interrupts and macro service requests are serviced after execution of the BR instruction, so that interrupts are never held pending for a long period.
...
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[MEMO]
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The local bus interface function is provided for the connection of external memory (ROM and RAM) and I/Os. External memory (ROM and RAM) and I/Os are accessed using the RD, WR, and ASTB pin signals, with pins AD0 to AD7 used as the multiplexed address/data bus and pins A8 to A19 as the address bus. The basic bus interface timing is shown in Figures 24-6 and 24-7. Also provided are a wait function for interfacing with low-speed memory, a refresh signal output function for refreshing pseudo-static RAM, and a bus hold function for connecting devices that have a bus master function, such as a DMA controller. 24.1 Memory Expansion Function With the PD784938, external memory and I/O expansion can be performed by setting the memory expansion mode register (MM). 24.1.1 Memory expansion mode register (MM) MM is an 8-bit register that performs external expansion memory control, address wait number specification, and internal fetch cycle control. MM can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The MM format is shown in Figure 24-1. RESET input sets MM to 20H.
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Figure 24-1. Memory Expansion Mode Register (MM) Format
7 MM IFCH
6 0
5 AW
4 0
3 MM3
2 MM2
1 MM1
0 MM0
Address 0FFC4H
After reset 20H
R/W R/W
MM3
MM2 MM1 MM0
Mode
Port 4
Port 5
P60 to P63
P64/ RD
P65/ ASTB WR /CLK OUT Port ASTB WR WR WR WR WR WR WR
0 0 0 0 0 0 1 1
0 0 1 1 1 1 0 0
0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
Single-chip mode 256-byte expansion mode 1-Kbyte expansion mode 4-Kbyte expansion mode 16-Kbyte expansion mode 64-Kbyte expansion mode 256-Kbyte expansion mode 1-Mbyte expansion mode Setting prohibited
Port AD0 to AD7 AD0 to AD7 AD0 to AD7 AD0 to AD7 AD0 to AD7 AD0 to AD7 AD0 to AD7
Port Port A8, A9 Port
Port Port Port Port
Port RD RD RD RD RD Port RD RD
A8 to A11 Port
A8 to A13 Port Port A8 to A15 A8 to A15 A8 to A15 Port A16, A17
A16 to A19
Other than the above
AW 0 1
Address Wait Specification Disabled Enabled
IFCH 0
Internal ROM Fetches Fetch performed at same speed as external memory All wait control settings valid High-speed fetches performed Wait control specification invalid
1
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24.1.2 Memory map with external memory expansion The memory map when memory expansion is used is shown in Figures 24-2 and 24-3. External devices at the same addresses as the internal ROM area, internal RAM area and SFR area (excluding the external SFR area (0FFD0H to 0FFDFH)) cannot be accessed. If an access is made to these addresses, the memory or SFR in the PD784938 has access priority and no ASTB signal, RD signal, or WR signal is output (these pins remain at the inactive level). The address bus output level remains at the level output prior to this, and the address/data bus output becomes high-impedance. Except in 1-Mbyte expansion mode, the address output externally is output with the upper part of the address specified by the program masked. Example 1: In 256-byte expansion mode, when address 54321H is accessed by the program, the output address is 21H. Example 2: In 256-byte expansion mode, when address 67821H is accessed by the program, the output address is 21H.
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Figure 24-2. PD784935 Memory Map (1/2) (a) When LOCATION 0 instruction is executed
FFFFFH
External memoryNote 1
External memory
17FFFH Internal ROM 10000H 0FFFFH 0FFE0H 0FFCFH SFR Internal ROM SFR Note 2 SFR Internal RAM SFR Internal RAM Internal ROM SFR External memoryNote 2 SFR Internal RAM
0EB00H
Internal ROM
Internal ROM
Internal ROM
00000H Single-chip mode 256-byte to 256-Kbyte expansion modes 1-Mbyte expansion mode
Notes 1. Any expansion size area in unshaded part 2. External SFR area
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Figure 24-2. PD784935 Memory Map (2/2) (b) When LOCATION 0FH instruction is executed
FFFFFH FFFE0H FFFCFH
SFR
SFR Note 2
SFR External memoryNote 2 SFR Internal RAM
SFR Internal RAM
SFR Internal RAM
FEB00H
External memoryNote 1
External memory
17FFFH
Internal ROM
Internal ROM
Internal ROM
00000H Single-chip mode 256-byte to 256-Kbyte expansion mode 1-Mbyte expansion mode
Notes 1. Any expansion size area in unshaded part 2. External SFR area
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Figure 24-3. PD784936 Memory Map (1/2) (a) When LOCATION 0 instruction is executed
FFFFFH
External memoryNote 1
External memory
1FFFFH Internal ROM 10000H 0FFFFH 0FFE0H 0FFCFH SFR Internal ROM SFR Note 2 SFR Internal RAM SFR Internal RAM Internal ROM SFR External memoryNote 2 SFR Internal RAM
0E500H
Internal ROM
Internal ROM
Internal ROM
00000H Single-chip mode 256-byte to 256-Kbyte expansion modes 1-Mbyte expansion mode
Notes 1. Any expansion size area in unshaded part 2. External SFR area
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Figure 24-3. PD784936 Memory Map (2/2) (b) When LOCATION 0FH instruction is executed
FFFFFH FFFE0H FFFCFH
SFR
SFR Note 2
SFR External memoryNote 2 SFR Internal RAM
SFR Internal RAM
SFR Internal RAM
FE500H
External memoryNote 1
External memory
1FFFFH
Internal ROM
Internal ROM
Internal ROM
00000H Single-chip mode 256-byte to 256-Kbyte expansion mode 1-Mbyte expansion mode
Notes 1. Any expansion size area in unshaded part 2. External SFR area
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Figure 24-4. PD784937 Memory Map (1/2) (a) When LOCATION 0 instruction is executed
FFFFFH
External memoryNote 1
External memory
2FFFFH Internal ROM 10000H 0FFFFH 0FFE0H 0FFCFH SFR Internal ROM SFR Note 2 SFR Internal RAM SFR Internal RAM Internal ROM SFR External memoryNote 2 SFR Internal RAM
0DF00H
Internal ROM
Internal ROM
Internal ROM
00000H Single-chip mode 256-byte to 256-Kbyte expansion modes 1-Mbyte expansion mode
Notes 1. Any expansion size area in unshaded part 2. External SFR area
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Figure 24-4. PD784937 Memory Map (2/2) (b) When LOCATION 0FH instruction is executed
FFFFFH FFFE0H FFFCFH
SFR
SFR Note 2
SFR External memoryNote 2 SFR Internal RAM
SFR Internal RAM
SFR Internal RAM
FDF00H
External memoryNote 1
External memory
1FFFFH
Internal ROM
Internal ROM
Internal ROM
00000H Single-chip mode 256-byte to 256-Kbyte expansion mode 1-Mbyte expansion mode
Notes 1. Any expansion size area in unshaded part 2. External SFR area
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Figure 24-5. PD784938 Memory Map (1/2) (a) When LOCATION 0 instruction is executed
FFFFFH
External memoryNote 1
External memory
3FFFFH Internal ROM 10000H 0FFFFH 0FFE0H 0FFCFH SFR Internal ROM SFR Note 2 SFR Internal RAM SFR Internal RAM Internal ROM SFR External memoryNote 2 SFR Internal RAM
0D600H
Internal ROM
Internal ROM
Internal ROM
00000H Single-chip mode 256-byte to 256-Kbyte expansion modes 1-Mbyte expansion mode
Notes 1. Any expansion size area in unshaded part 2. External SFR area
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Figure 24-5. PD784938 Memory Map (2/2) (b) When LOCATION 0FH instruction is executed
FFFFFH FFFE0H FFFCFH
SFR
SFR Note 2
SFR External memoryNote 2 SFR Internal RAM
SFR Internal RAM
SFR Internal RAM
FD600H
External memoryNote 1
External memory
1FFFFH
Internal ROM
Internal ROM
Internal ROM
00000H Single-chip mode 256-byte to 256-Kbyte expansion mode 1-Mbyte expansion mode
Notes 1. Any expansion size area in unshaded part 2. External SFR area
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24.1.3 Basic operation of local bus interface The local bus interface accesses external memory using ASTB, RD, WR, an address/data bus (AD0 to AD7), and address bus (A8 to A19). When the local bus interface is used, P64, P65, and port 4 automatically operate as RD, WR and AD0 to AD7. On the address bus, only the pins that correspond to the expansion memory size operate as address bus pins. An outline of the memory access timing is shown in Figures 24-6 and 24-7. Figure 24-6. Read Timing
A8 to A19Note (output)
High address
AD0 to AD7
Hi-Z
Low address (output)
Hi-Z
Data (input)
Hi-Z
ASTB (output)
RD (output)
Note The number of address bus pins used depends on the expansion mode size. Figure 24-7. Write Timing
A8 to A19Note (output) Hi-Z AD0 to AD7 (output) Hi-Z Low address
High address
Data
Hi-Z
ASTB (output)
WR (output)
Note The number of address bus pins used depends on the expansion mode size.
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24.2 Wait Function When a low-speed memory or I/O is connected externally to the PD784938, waits can be inserted in the external memory access cycle. There are two kinds of wait cycle, an address wait for securing the address decoding time, and an access wait for securing the access time. 24.2.1 Wait function control registers (1) Memory expansion mode register (MM) The IFCH bit of MM performs wait control setting for internal ROM accesses, and the AW bit performs address wait setting. MM can be read or written to with an 8-bit manipulation instruction. The MM format is shown in Figure 24-8. When RESET is input, MM is set to 20H, the same cycle as for external memory is used for internal ROM accesses, and the address wait function is validated. Figure 24-8. Memory Expansion Mode Register (MM) Format
7 MM IFCH 6 0 5 AW 4 0 3 MM3 2 MM2 1 MM1 0 MM0 Address 0FFC4H After reset 20H R/W R/W
Memory expansion mode settings (see 24.1 Memory Extension Function) AW 0 1 IFCH 0 Address Wait Specification Disabled Enabled Internal ROM Fetches Fetch performed at same speed as external memory All wait control settings valid High-speed fetches performed Wait control specification invalid
1
(2) Programmable wait control registers (PWC1/PWC2) PWC1 and PWC2 specify the number of waits. PWC1 is an 8-bit register that divides the space from 0 to FFFFH into four, and specifies wait control for each of these four spaces. PWC2 is a 16-bit register that divides the space from 10000H to FFFFH into four, and specifies wait control for each of these four spaces. PWC1 can be read or written to with an 8-bit manipulation instruction, and PWC2 with a 16-bit manipulation instruction. The PWC1 and PWC2 formats are shown in Figure 24-9. The high-order 8 bits of PWC2 are fixed at AAH, and therefore ensure that the high-order 8 bits are set to AAH. When RESET is input, PWC1 is set to AAH, and PWC2 to AAAAH, and 2-wait insertion is performed on the entire space.
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Figure 24-9. Programmable Wait Control Register (PWC1/PWC2) Format (a) Programmable wait control register 1 (PWC1)
7 PWC1 PW31 6 5 4 PW20 3 PW11 2 PW10 1 0 Address 0FFC7H After reset AAH R/W R/W
PW30 PW21
PW01 PW00
Address Subject to Wait 000000H to 003FFFH
PW01 PW00
Wait Cycle Insertion
0 0 1 1
0 1 0 1
0 1 2 Access wait cycle inserted only for WAIT pin low-level input period
Address Subject to Wait 004000H to 007FFFH
PW11 PW10
Wait Cycle Insertion
0 0 1 1
0 1 0 1
0 1 2 Access wait cycle inserted only for WAIT pin low-level input period
Address Subject to Wait 008000H to 00BFFFH
PW21 PW20
Wait Cycle Insertion
0 0 1 1
0 1 0 1
0 1 2 Access wait cycle inserted only for WAIT pin low-level input period
Address Subject to Wait 00C000H to 00FFFFHNote
PW31 PW30 0 0 1 1 0 1 0 1 0 1 2
Wait Cycle Insertion
Access wait cycle inserted only for WAIT pin low-level input period
Note Except part overlapping internal data area
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(b) Programmable wait control register 2 (PWC2)
15 PWC2 1 7 PW71 14 0 6 13 1 5 12 0 4 PW60 11 1 3 PW51 10 0 2 PW50 9 1 1 8 0 0 Address 0FFC8H After reset AAAAH R/W R/W
PW70 PW61
PW41 PW40
Address Subject to Wait 010000H to 01FFFFH
PW41 PW40
Wait Cycle Insertion
0 0 1 1
0 1 0 1
0 1 2 Access wait cycle inserted only for WAIT pin low-level input period
Address Subject to Wait 020000H to 03FFFFH
PW51 PW50 0 0 1 1 0 1 0 1 0 1 2
Wait Cycle Insertion
Access wait cycle inserted only for WAIT pin low-level input period
Address Subject to Wait 040000H to 07FFFFH
PW61 PW60
Wait Cycle Insertion
0 0 1 1
0 1 0 1
0 1 2 Access wait cycle inserted only for WAIT pin low-level input period
Address Subject to Wait 080000H to 0FFFFFHNote
PW71 PW70
Wait Cycle Insertion
0 0 1 1
0 1 0 1
0 1 2 Access wait cycle inserted only for WAIT pin low-level input period
Note Except part overlapping internal data area Caution When the bus hold function is used, access wait control cannot be performed by means of the WAIT pin, and 0, 1, or 2 waits must be selected for the entire space.
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24.2.2 Address waits Address waits are used to secure the address decoding time. If the AW bit of the memory expansion mode register (MM) is set (to 1), waits are inserted in every memory accessNote. When an address wait is inserted, the high-level period of the ASTB signal is extended by one system clock cycle (80 ns: fCLK = 12.58 MHz). Note Except for the internal RAM, internal SFRs, and internal ROM during high-speed fetch. If it is specified that the internal ROM is accessed in the same cycle as the external ROM, an address wait state is inserted even when the internal ROM is accessed. Caution If the pseudo-static RAM refresh function is used when the address wait function is used, the refresh pulse is output and, at the same time, the memory is accessed. Therefore, do not use the pseudo-static RAM refresh function when using the address wait function. Figure 24-10. Address Wait Function Read/Write Timing (1/3) (a) Read timing with no address wait insertion
fCLKNote
A8 to A19
High address
AD0 to AD7
Hi-Z
Low address
Hi-Z
Input data
Hi-Z
ASTB
RD
Note fCLK: Internal system clock frequency. This signal is present inside the PD784938 only.
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Figure 24-10. Address Wait Function Read/Write Timing (2/3) (b) Read timing with address wait insertion
fCLKNote
A8 to A19
High address
Hi-Z AD0 to AD7 Low address
Hi-Z Input data
Hi-Z
ASTB
RD
Note fCLK: Internal system clock frequency. This signal is present inside the PD784938 only.
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Figure 24-10. Address Wait Function Read/Write Timing (3/3) (c) Write timing with no address wait insertion
fCLKNote
A8 to A19
High address
AD0 to AD7
Hi-Z
Low address
Hi-Z
Output data
Hi-Z
ASTB
WR
(d) Write timing with address wait insertion
fCLKNote
A8 to A19
High address
AD0 to AD7
Hi-Z
Low address
Hi-Z
Hi-Z Output data
ASTB
WR
Note fCLK: Internal system clock frequency. This signal is present inside the PD784938 only.
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24.2.3 Access waits Access waits are inserted in the RD or WR signal low-level period, and extend the low-level period by 1/fCLK (80 ns: fCLK = 12.58 MHz) per cycle. There are two wait insertion methods, using either the programmable wait function that automatically inserts the preset number of cycles, or the external wait function controlled by a wait signal from outside. For wait cycle insertion control, the 1-Mbyte memory space is divided into eight as shown in Figure 24-11, and control is specified for each space by means of the programmable wait control registers (PWC1/PWC2). Waits are not inserted in accesses to internal ROM or internal RAM using high-speed fetches. In accesses to internal SFRs, waits are inserted at the necessary times regardless of this specification. If access operations are specified as being performed in the same number of cycles as for external ROM, waits are inserted also in internal ROM accesses in accordance with the PWC1 settings. If there is a space for which control by a wait signal from outside has been selected by means of the PWC1/PWC2, the P66 pin operates as the WAIT signal input pin. After RESET input, the P66 pin operates as a general-purpose input/output port. Bus timing in the case of access wait insertion is shown in Figures 24-12 to 24-14. Caution The external wait function cannot be used when the bus hold function is used.
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Figure 24-11. Wait Control Spaces
FFFFFH
512 Kbytes
Controlled by bits PW70 & PW71
80000H 7FFFFH Controlled by PWC2 256 Kbytes Controlled by bits PW60 & PW61
40000H 3FFFFH 128 Kbytes 20000H 1FFFFH 64 Kbytes 10000H 0FFFFH 16 Kbytes 0C000H 0BFFFH 16 Kbytes 08000H 07FFFH 16 Kbytes 04000H 03FFFH 16 Kbytes 00000H Controlled by bits PW30 & PW31 Controlled by bits PW20 & PW21 Controlled by PWC1 Controlled by bits PW10 & PW11 Controlled by bits PW00 & PW01 Controlled by bits PW40 & PW41 Controlled by bits PW50 & PW51
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Figure 24-12. Access Wait Function Read Timing (1/2) (a) 0 wait cycles set
fCLKNote
A8 to A15 (output)
High address
AD0 to AD7
Hi-Z
Low address
Hi-Z
Data (input)
Hi-Z
ASTB (output)
RD (output)
(b) 1 wait cycle set
fCLKNote
A8 to A15 (output)
High address
AD0 to AD7
Hi-Z
Low address
Hi-Z
Data (input)
Hi-Z
ASTB (output)
RD (output)
Note fCLK: Internal system clock frequency. This signal is only present inside the PD784938.
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Figure 24-12. Access Wait Function Read Timing (2/2) (c) 2 wait cycles set
fCLKNote
A8 to A15 (output)
High address
AD0 to AD7
Low address
Hi-Z
Data (input)
Hi-Z
ASTB (output)
RD (output)
Note fCLK: Internal system clock frequency. This signal is only present inside the PD784938.
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Figure 24-13. Access Wait Function Write Timing (1/2) (a) 0 wait cycles set
fCLKNote
A8 to A15 (output)
High address
AD0 to AD7 (output)
Hi-Z
Low address
Hi-Z
Data
Hi-Z
ASTB (output)
WR (output)
(b) 1 wait cycle set
fCLKNote
A8 to A15 (output)
High address
AD0 to AD7 (output)
Hi-Z
Low address
Hi-Z
Data
Hi-Z
ASTB (output)
WR (output)
Note fCLK: Internal system clock frequency. This signal is only present inside the PD784938.
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Figure 24-13. Access Wait Function Write Timing (2/2) (c) 2 wait cycles set
fCLKNote
A8 to A15 (output)
High address
Low AD0 to AD7 Hi-Z address (output)
Hi-Z
Data
Hi-Z
ASTB (output)
WR (output)
Note fCLK: Internal system clock frequency. This signal is only present inside the PD784938.
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Figure 24-14. Timing with External Wait Signal (a) Read timing
fCLKNote
A8 to A15 (output)
High address
AD0 to AD7
Low address
Hi-Z
Data (input)
Hi-Z
ASTB (output)
RD (output)
WAIT (input)
(b) Write timing
fCLKNote
A8 to A15 (output)
High address
AD0 to AD7 (output)
Low address
Hi-Z
Data
Hi-Z
ASTB (output)
WR (output)
WAIT (input)
Note fCLK: Internal system clock frequency. This signal is only present inside the PD784938.
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24.3 Pseudo-Static RAM Refresh Function The PD784938 incorporates a pseudo-static RAM refresh function for direct connection of pseudo-static RAM. The pseudo-static RAM refresh function outputs refresh pulses at any desired intervals. The refresh pulse output interval is specified by the refresh mode register (RFM) setting. The refresh area specification register (RFA) specifies the addresses on which refresh operations can be performed at the same time as memory access operations. This enables bus cycle insertions for refresh operations to be greatly decreased, thus minimizing the reduction in performance due to refresh operations. The PD784938 is provided with a function for supporting self-refresh operations that offers low power consumption by a pseudo-static RAM application system. Cautions 1. The refresh function cannot be used when the bus hold function is used. 2. If the pseudo-static RAM refresh function is used when the address wait function is used, the refresh pulse is output and, at the same time, the memory is accessed. Therefore, do not use the pseudo-static RAM refresh function when using the address wait function.
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24.3.1 Control registers (1) Refresh mode register (RFM) RFM is an 8-bit register that controls the pseudo-static RAM refresh cycle and switching to self-refresh operations. RFM can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The RFM format is shown in Figure 24-15. RESET input clears RFM to 00H and sets the REFRQ pin to port mode, so that it operates as the alternate-function P67 pin. Figure 24-15. Refresh Mode Register (RFM) Format
7 RFM RFLV 6 0 5 0 4 RFEN 3 0 2 0 1 RFT1 0 RFT0 Address 0FFCCH After reset 00H R/W R/W
fCLK = 12.58 MHz RFT1 0 0 1 1 RFT0 0 1 0 1 Refresh Pulse Output Cycle Specification 32/fCLKNote (2.5 s) 64/fCLK (5.1 s) 128/fCLK (10.2 s) 256/fCLK (20.3 s)
Note fCLK: Internal system clock frequency
RFLV RFEN
REFRQ Pin Output Control Port mode Self-refresh operation (REFRQ low level) Refresh pulse output enabled
x
0 1
0 1
Remark x: 0 or 1
Caution The refresh function cannot be used when the bus hold function is used. In this case, ensure that refreshing is specified as disabled.
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(2) Refresh area specification register (RFA) RFA is an 8-bit register that specifies the areas on which refresh operations can be performed at the same time as memory access operations. RFA can be read or written to with an 8-bit manipulation instruction and bit manipulation instruction. The RFA format is shown in Figure 24-16. RESET input clears RFA to 00H. Figure 24-16. Refresh Area Specification Register (RFA) Format
7 RFA
(n = 0 to 7)
6 RFA6
5 RFA5
4 RFA4
3 RFA3
2 RFA2
1 RFA1
0 RFA0
Address After reset R/W 0FFCDH 00H R/W
RFA7
RFAn
Refresh 080000H to 040000H to 020000H to 010000H to 00C000H to 008000H to 004000H to 000000H to Specification 0FFFFFH 07FFFFH 03FFFFH 01FFFFH 00FFFFH 00BFFFH 007FFFH 003FFFH Area 0 1 Refreshing performed at same time as memory access operations in corresponding block Refreshing performed exclusively from memory access operations in corresponding block
24.3.2 Operations (1) Pulse refresh operation To support the pulse refresh cycles of pseudo-static RAM, refresh pulses are output from the REFRQ pin in synchronization with bus cycles. The system clock frequency and bits 1 and 0 (RFT1/RFT0) of the refresh mode register (RFM) are adjusted so that 512 or more refresh pulses are generated in an 8 ms period. Table 24-1. System Clock Frequency and Refresh Pulse Output Cycle when Pseudo-Static RAM is Used
System Clock Frequency (fCLK) MHz 8.192 < fCLK 16 4.096 < fCLK 8.192 2.048 < fCLK 4.096 Refresh Pulse Output Cycle Specification RFT1 RFT0
128/fCLK 64/fCLK 32/fCLK
1 0 0
0 1 0
These pulse refresh operations are performed so that they do not overlap external memory access operations. During a refresh cycle, an external memory access cycle is held pending (ASTB, RD, WR, etc. are inactive), and during an external memory access cycle, a refresh cycle is held pending. If there is no overlapping with an external memory access operation, the refresh cycle is performed without affecting CPU instruction execution.
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(a) Internal memory accesses In the case of internal memory accesses in which the external pseudo-static RAM is not accessed, also, refresh bus cycles are output at the intervals specified by the refresh mode register (RFM) so that the data stored in the pseudo-static RAM is retained. In this case, CPU instruction execution is not affected. Figure 24-17. Pulse Refresh Operation in Internal Memory Access
Refresh timing counter
REFRQ pin output
Refresh cycleNote
Note Cycle specified by the RFT1 and RFT0 bits of the RFM
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(b) External memory accesses When an access is made to an address corresponding to a cleared (to 0) bit in the refresh area specification register (RFA), a refresh pulse is always output from the REFRQ pin at the same time as the RD signal or WR signal, irrespective of the cycle specified by the refresh mode register (RFM). After refresh pulse output, accesses to internal memory or accesses to addresses corresponding to a set (to 1) bit in the RFA continue, and after the time specified by the RFT0 and RFT1 bits of the RFM has elapsed, a refresh bus cycle is generated so as not to overlap a memory access cycle, and a refresh pulse is output. In this way, refreshing can be performed while memory that does not need refreshing, such as PROM, is being accessed, refresh bus cycle insertions can be reduced, and instruction execution can be performed efficiently. Figure 24-18. Refresh Pulse Output Operation
ASTB
RD
WR
REFRQ
Read cycle
Write cycle
Read cycle
Read cycle
Refresh bus cycle
Write cycle
Time specified by RFT0 & RFT1 bits of RFM In case of access to area in which memory access operations and refresh operations are performed exclusively In case of access to area in which memory access operations and refresh operations are performed simultaneously Time specified by RFT0 & RFT1 bits of REM. As refresh pulse has not been output, refresh bus cycle is inserted
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(2) Self-refresh operation This mode is used to retain the contents of pseudo-static RAM in standby mode. (a) Self-refresh operation mode setting When bit 4 (RFEN) of the refresh mode (RFM) register is set to "1", and bit 7 (RFLV) to "0", a low level is output from the REFRQ pin, and the self-refresh operation mode is specified for the pseudo-static RAM. (b) Return from self-refresh operation Refresh pulse output to the pseudo-static RAM is disabled approximately 200 nsNote after the REFRQ pin output level changes from low to high. Therefore, the PD784938 arranges for refresh pulses not to be output during the disabled time by raising the REFRQ pin in synchronization with the refresh timing counter. To enable this low-to-high transition of the REFRQ pin level to be recognized, the RFLV bit read level is set (to 1) when the REFRQ pin level changes from low to high. Note This time varies according to the speed rank, etc. of the pseudo-static RAM. Figure 24-19. Timing for Return from Self-Refresh Operation
Self refresh mode Approximately min. 200 nsNote
REFRQ
Refresh timing counter output
RFLV bit
Software set operation execution
Note Refreshing disabled time
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24.4 Bus Hold Function The bus hold function is provided for the connection of a device that functions as the bus master, such as a DMA controller. In response to a request from the bus master device, all local bus interface pins are set to high impedance (except HLDAK), and local bus interface mastership is passed to that device. The bus hold function cannot be used when the external wait function or refresh function is used. 24.4.1 Hold mode register (HLDM) HLDM is an 8-bit register that specifies enabling/disabling of the bus hold function. HLDM format is shown in Figure 24-20. When RESET is input, HLDM is cleared to 00H, so that the bus hold function is disabled. The HLDRQ and HLDAK pins are set to port mode and operate as the P66 and P67 pins. Figure 24-20. Hold Mode Register (HLDM) Format
7 HLDM HLDE 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Address 0FFC5H After reset 00H R/W R/W
HLDE Bus Hold Enabling/Disabling 0 1 Disabled Enabled
P66 Port HLDRQ
P67
HLDAK
Caution The bus hold function must be disabled when the external wait function or refresh function is used.
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24.4.2 Operation When the HLDE bit of the hold mode register (HLDM) is set (to 1), the bus hold function is enabled. When the bus hold function is enabled, pins P66 and P67 operate as the HLDRQ and HLDAK pins respectively. The HLDRQ pin becomes high-impedance, and the HLDAK pin outputs a low-level signal. If a high-level signal is input to the HLDRQ pin when the bus hold function is enabled, at the end of the access operation being executed the address bus (A8 to A19), address/data bus (AD0 to AD7), RD, WR, and ASTB pins are all set to highimpedance, the HLDAK pin output level is driven high, and the hold mode is established. While the HLDAK pin is high (in the hold mode) the PD784938 does not use the local bus interface, and therefore an external DMA controller, etc. is free to access the memory. When the HLDRQ pin input level changes from high to low, the hold mode is released, the HLDAK pin level changes from high to low, and then the PD784938 resumes use of the local bus. A transition to the hold mode is performed between bus cycles, and the instruction being executed may be suspended. Also, if a transition to the hold mode is made during execution of an instruction that does not use the local bus interface when a program is fetched from the external memory, the PD784938 continues execution of prefetched instructions until it comes to an instruction that uses the local bus interface, and suspends instruction execution when there are no more prefetched instructions. When the hold mode is released, execution of the suspended instruction is resumed from the point at which it was suspended. When a program is fetched from the internal ROM or RAM, execution of instructions until it comes to an instruction that uses the local bus interface continues. Figure 24-21. Hold Mode Timing
ASTB
Hi-Z
A8 to A19
Hi-Z
AD0 to AD7
Hi-Z
RD
Hi-Z
WR
Hi-Z
HLDRQ
HLDAK
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24.5 Cautions (1) When the bus hold function is used, the external wait function cannot be used (access wait control by means of the WAIT pin), and 0, 1, or 2 waits must be selected for the entire space. (2) The refresh function cannot be used when the bus hold function is used. In this case, ensure that refreshing is specified as disabled. (3) Do not set external wait to the internal ROM area. Otherwise, the CPU may be in the deadlock status which can be cleared only by reset input. (4) If the pseudo-static RAM refresh function is used when the address wait function is used, the refresh pulse is output and, at the same time, the memory is accessed. Therefore, do not use the pseudo-static RAM refresh function when using the address wait function. Conversely do not use the address wait function when the pseudo-static RAM refresh function is used.
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CHAPTER 25 STANDBY FUNCTION
25.1 Configuration and Function The PD784938 has a standby function that enables the system power consumption to be reduced. The standby function includes three modes as follows: * HALT mode........ In this mode the CPU operating clock is stopped. Intermittent operation in combination with the normal operation mode enables the total system power consumption to be reduced. * IDLE mode......... In this mode the oscillator continues operating while the entire remainder of the system is stopped. Normal program operation can be restored at a low power consumption close to that of the STOP mode and in a time equal to that of the HALT mode. * STOP mode........In this mode the oscillator is stopped and the entire system is stopped. Ultra-low power consumption can be achieved, consisting of leakage current only. These modes are set by software. The standby mode (STOP/IDLE/HALT mode) transition diagram is shown in Figure 25-1, and the standby function block diagram in Figure 25-2. Figure 25-1. Standby Mode Transition Diagram
Macro service request
cill End of os
Wait of oscillation stabilization
ation sta
bilization
time
Program operation
End of 1st service End of macro service
Macro service
ut No
te
1
N t es qu re t pt pu in ing rru T t te In SE set RE LT HA
np
ID L RE E s TW SE ett in No T tes inp g 1, 3 , N ut MI , IN TP 4,
IN NM TW Not es I, I NT 1, 3 P4 , , IN TP
ro
ac
M
STOP (standby)
IDLE (standby)
IN
Masked interrupt request
HALT (standby)
Notes 1. When INTW, INTP4, and INTP5 are not masked 2. Unmasked interrupt request only 3. At subclock operation Remark Only external input is valid as NMI. The watchdog timer must not be used to release the standby mode (STOP, IDLE, or HALT mode)
En
d
of
1s
g ttin se put in OP ST SET E R
te 1
5i
ut No
TP
IN
re ice rv se
2
qu ts er vic e
5i
np
es
t
e ot
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To watch timer after division by 128 WM3 WM6 System cock oscillator
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Figure 25-2. Standby Function Block Diagram
To peripheral circuit Oscillation stabilization timer (19) RAM PROTECT OSTS0 OSTS1 OSTS2 EXTC Selector HLT F/F QS Q R Selector To peripheral circuit
fxx fxx Frequency divider fxx/2 fxx/4 fxx/8
CPU CLK HALT bit setting STOP bit setting
CHAPTER 25
EXTC
Macro service request
IDLE F/F QS Q R
STANDBY FUNCTION
STP F/F2 QS ESNMI Rising edge detection NMI Rising edge detection ES40, ES50 ES41, ES51 Valid edge Selector Falling edge detection RESET INTW MK ISM Interrupt INTC Macro service request Selector Q R
STP F/F1 QS Q MK ISM R
Falling edge detection INTP4, INTP5
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25.2 Control Registers 25.2.1 Standby control register (STBC) STBC is used to select the STOP mode setting and the internal system clock. To prevent entry into standby mode due to an inadvertent program loop, STBC can only be written to with a dedicated instruction. This dedicated instruction, MOV STBC, #byte, has a special code configuration (4 bytes), and a write is only performed if the 3rd and 4th bytes of the operation code are mutual complements of 1. If the 3rd and 4th bytes of the operation code are not mutual complements of 1, a write is not performed and an operand error interrupt is generated. In this case, the return address saved in the stack area is the address of the instruction that was the source of the error, and thus the address that was the source of the error can be identified from the return address saved in the stack area. If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result. As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC assembler, RA78K4, only the correct dedicated instruction is generated when MOV STBC, #byte is written), system initialization should be performed by the program. Other write instructions (MOV STBC, A, AND STBC, #byte, SET1 STBC.7, etc.) are ignored and do not perform any operation. That is, a write is not performed to STBC, and an interrupt such as an operand error interrupt is not generated. STBC can be read at any time by a data transfer instruction. RESET input sets STBC to 30H. The format of STBC is shown in Figure 25-3. Caution Be sure to use a program that executes a NOP instruction three times to set the standby mode. ... Example MOV STBC, #byte; Sets standby mode NOP NOP NOP ...
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Figure 25-3. Standby Control Register (STBC) Format
7 STBC SELOSC 6 0 5 CK1 4 CK0 3 x 2 0 1 STP 0 HLT Address 0FFC0H After reset 30H R/W R/W
STP 0 0 1 1
HLT 0 1 0 1
Operation Mode Normal operation mode HALT mode STOP mode IDLE mode (fXX = 12.58 MHz)
CK1 0 0 1 1 SELOSC 0 1
CK0 0 1 0 1
Internal System Clock Selection fXX (12.58 MHz)
fXX/2 (6.29 MHz) fXX/4 (3.15 MHz) fXX/8 (1.57 MHz) Oscillation Frequency Control
6.29 MHz 12.58 MHz
Cautions 1. The SELOSC bit must be overwritten after performing the next setting. * Stop the IEBus (Set bit 7 (ENIEBUS) of the bus control register (BCR) to "0".) * If the watch timer is operated with the main clock selected, stop the watch timer (Set bit 3 (WM3) of the watch timer mode register (WM) to "0".) 2. If the above settings are not performed, the IEBus and watch timer may perform incorrectly.
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25.2.2 Oscillation stabilization time specification register (OSTS) OSTS specifies the oscillator operation and the oscillation stabilization time when STOP mode is released. The EXTC bit of OSTS specifies whether crystal/ceramic oscillation or an external clock is used. STOP mode can be set when external clock input is used only when the EXTC bit is set (to 1). Bits OSTS0 to OSTS2 of OSTS select the oscillation stabilization time when STOP mode is released. In general, an oscillation stabilization time of at least 40 ms should be selected when a crystal resonator is used, and at least 4 ms when a ceramic oscillator is used. The time taken for oscillation stabilization is affected by the crystal resonator or ceramic resonator used, and the capacitance of the connected capacitor. Therefore, if you want to set a short oscillation stabilization time, you should consult the crystal resonator or ceramic resonator manufacturer. OSTS can be written to only with an 8-bit transfer instruction. RESET input clears OSTS to 00H. The format of OSTS is shown in Figure 25-4. Figure 25-4. Oscillation Stabilization Time Specification Register (OSTS) Format
7 OSTS 0 6 0 5 0 4 0 3 0 2 1 0 Address 0FFCFH After reset 00H R/W R/W
OSTS2 OSTS1 OSTS0
(fXX = 12.58 MHz) OSTS2 OSTS1 OSTS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Oscillation Stabilization Time Selection Bits 219/fXX (41.7 ms) 218/fXX (20.8 ms) 217/fXX (10.4 ms) 216/fXX (5.2 ms) 215/fXX (2.6 ms) 214/fXX (1.3 ms) 213/fXX (0.7 ms) Setting prohibited
Caution When using the regulator (Refer to CHAPTER 5 REGULATOR), set a value of at least 10.4 ms, taking in consideration the regulator output stabilization time.
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25.3 HALT Mode 25.3.1 HALT mode setting and operating status The HALT mode is selected by setting (to 1) the HLT bit of the standby control (STBC) register. The only writes that can be performed on STBC are 8-bit data writes by means of a dedicated instruction. HALT mode setting is therefore performed by means of the "MOV STBC, #byte" instruction. Caution If HALT mode setting is performed when a condition that releases HALT mode is in effect, HALT mode is not entered, and execution of the next instruction, or a branch to a vectored interrupt service program, is performed. To ensure that a definite HALT mode setting is made, interrupt requests should be cleared (to 0), etc. before entering HALT mode. Table 25-1. Operating Status in HALT Mode
Clock oscillator Internal system clock CPU I/O lines Peripheral functions Internal RAM Bus lines AD0 to AD7 A8 to A19 RD, WR output ASTB output REFRQ output HLDRQ input HLDAK output Operating Operating Operation stoppedNote Retain status prior to HALT mode setting Continue operating Retained High-impedance Retained High level Low level Continue operating Continue operating (input) Continue operating
Note Macro service processing is executed. 25.3.2 HALT mode release HALT mode can be released by the following three sources. * Non-maskable interrupt request * Maskable interrupt request (vectored interrupt/context switching/macro service) * RESET input Release sources and an outline of operations after release are shown in Table 25-2.
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Table 25-2. HALT Mode Release and Operations after Release
Release Source RESET input Non-maskable interrupt request (NMI pin input/ watchdog timer) MKNote 1 IE Note 2 x x x x State on Release -- * Non-maskable interrupt service program not being executed * Low-priority non-maskable interrupt service program being executed * Service program for same request being executed * High-priority non-maskable interrupt service program being executed Maskable interrupt request (excluding macro service request) 0 1 * Interrupt service program not being executed * Low-priority maskable interrupt service program being executed * PRSL bitNote 4 cleared (to 0) during execution of priority level 3 interrupt service program * Same-priority maskable interrupt service program being executed (If PRSL bitNote 4 is cleared (to 0), excluding execution of priority level 3 interrupt service program) * High-priority interrupt service program being executed 0 1 Macro service request 0 0 x x -- -- -- HALT mode maintained Macro service processing execution End condition not established HALT mode again End condition established If VCIE Note 5 = 1: HALT mode again If VCIE Note 5 = 0: Same as release by maskable interrupt request 1 x -- HALT mode maintained Operation after Release Normal reset operation Interrupt request acknowledgment
Execution of instruction after MOV STBC, #byte instruction (interrupt request that released HALT mode is held pendingNote 3)
Interrupt request acknowledgment
Execution of instruction after MOV STBC, #byte instruction (interrupt request that released HALT mode is held pendingNote 3)
Notes 1. Interrupt mask bit in individual interrupt request source 2. Interrupt enable flag in program status word (PSW) 3. Pending interrupt requests are acknowledged when acknowledgment becomes possible. 4. Bit in interrupt mode control register (IMC) 5. Bit in macro service mode register of macro service control word in individual macro service request source
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(1) Release by non-maskable interrupt When a non-maskable interrupt is generate, the PD784938 is released from HALT mode irrespective of whether the interrupt acknowledgment enabled state (EI) or disabled state (DI) is in effect. When the PD784938 is released from HALT mode, if the non-maskable interrupt that released HALT mode can be acknowledged, acknowledgment of that non-maskable interrupt is performed and a branch is made to the service program. If the interrupt cannot be acknowledged, the instruction following the instruction that set the HALT mode (the MOV STBC, #byte instruction) is executed, and the non-maskable interrupt that released the HALT mode is acknowledged when acknowledgment becomes possible. See 23.6 Non-maskable Interrupt Acknowledgment Operation for details of non-maskable interrupt acknowledgment. (2) Release by maskable interrupt request HALT mode release by a maskable interrupt request can only be performed by an interrupt for which the interrupt mask flag is 0. When HALT mode is released, if an interrupt can be acknowledged when the interrupt request enable flag (IE) is set (to 1), a branch is made to the interrupt service program. If the interrupt cannot be acknowledged and if the IE flag is cleared (to 0), execution is resumed from the instruction following the instruction that set the HALT mode. See 23.7 Maskable Interrupt Acknowledgment Operation for details of interrupt acknowledgment. With macro service, HALT mode is released temporarily, service is performed once, then HALT mode is restored. When macro service has been performed the specified number of times, HALT mode is released if the VCIC bit in the macro service mode register of the macro service control word is cleared (to 0). The operation after release in this case is the same as for release by a maskable interrupt described earlier. If the VCIE bit is set (to 1), the HALT mode is entered again and is released by the next interrupt request.
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Table 25-3. HALT Mode Release by Maskable Interrupt Request
Release Source Maskable interrupt request (excluding macro service request) MKNote 1 IE Note 2 0 1 State on Release * Interrupt service program not being executed * Low-priority maskable interrupt service program being executed * PRSL bitNote 4 cleared (to 0) during execution of priority level 3 interrupt service program * Same-priority maskable interrupt service program being executed (If PRSL bitNote 4 is cleared (to 0), excluding execution of priority level 3 interrupt service program) * High-priority interrupt service program being executed 0 1 Macro service request 0 0 x x -- -- -- HALT mode maintained Macro service processing execution End condition not established HALT mode again End condition established If VCIENote 5 = 1: HALT mode again If VCIENote 5 = 0: Same as release by maskable interrupt request HALT mode maintained Operation after Release Interrupt request acknowledgment
Execution of instruction after MOV STBC, #byte instruction (interrupt request that released HALT mode is held pendingNote 3)
1
x
--
Notes 1. Interrupt mask bit in individual interrupt request source 2. Interrupt enable flag in program status word (PSW) 3. Pending interrupt requests are acknowledged when acknowledgment becomes possible. 4. Bit in interrupt mode control register (IMC) 5. Bit in macro service mode register of macro service control word in individual macro service request source (3) Release by RESET input The program is executed after branching to the reset vector address, as in a normal reset operation. However, internal RAM contents retain their value directly before HALT mode was set.
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25.4 STOP Mode 25.4.1 STOP mode setting and operating status The STOP mode is selected by setting (to 1) the STP bit of the standby control register (STBC) register. The only writes that can be performed on STBC are 8-bit data writes by means of a dedicated instruction. STOP mode setting is therefore performed by means of the "MOV STBC, #byte" instruction. Caution If the STOP mode is set when the condition to release the HALT mode is satisfied (refer to 25.3.2 HALT mode release), the STOP mode is not set, but the next instruction is executed or execution branches to a vectored interrupt service program. To accurately set the STOP mode, clear the interrupt request before setting the STOP mode. Table 25-4. Operating Status in STOP Mode
Clock oscillator Internal system clock CPU I/O lines Peripheral functions Internal RAM Bus lines AD0 to AD7 A8 to A19 RD, WR output ASTB output REFRQ output HLDRQ input HLDAK output Oscillation stopped Stopped Operation stopped Retain state prior to STOP mode setting All operation stoppedNote Retained High-impedance High-impedance High-impedance High-impedance Retained High-impedance Low level
Note A/D converter operation is stopped, but if the CS bit of the A/D converter mode register (ADM) is set (to 1), the current consumption does not decrease. Cautions 1. If the STOP mode is set when the EXTC bit of the oscillation stabilization time specification (OSTS) register is cleared (to 0), the X1 pin is shorted internally to VSS (GND potential) to suppress clock generator leakage. Therefore, when the STOP mode is used in a system that uses an external clock, the EXTC bit of OSTS must be set (to 1). If STOP mode setting is performed in a system to which an external clock is input when the EXTC bit of OSTS is cleared (to 0), the PD784938 may suffer damage or reduced reliability. When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the clock input to the X1 pin, to the X2 pin (refer to 4.3.1 Clock oscillator). 2. The CS bit of the A/D converter mode (ADM) register should be cleared (to 0).
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25.4.2 STOP mode release STOP mode is released by NMI input, INTP4 input, INTP5 input, INTW input, and RESET input. Table 25-5. STOP Mode Release and Operations after Release
Release Source MKNote 1 ISMNote 2 IE Note 3 RESET input NMI pin input x x x x x x State after Release -- * Non-maskable interrupt service program not being executed * Low-priority non-maskable interrupt service program being executed * NMI pin input service program being executed * High-priority non-maskable interrupt service program being executed INTP4/INTP5 pin input, INTW input 0 0 1 * Interrupt service program not being executed * Low-priority maskable interrupt service program being executed * PRSL bitNote 5 cleared (to 0) during execution of priority level 3 interrupt service program * Same-priority maskable interrupt service program being executed (If PRSL bitNote 5 is cleared (to 0), excluding execution of priority level 3 interrupt service program) * High-priority interrupt service program being executed 0 1 x 0 0 1 0 x x -- -- STOP mode maintained Operation after Release Normal reset operation Interrupt request acknowledgment
Execution of instruction after MOV STBC, #byte instruction (interrupt request that released STOP mode is held pendingNote 4) Interrupt request acknowledgment
Execution of instruction after MOV STBC, #byte instruction (interrupt request that released STOP mode is held pendingNote 4)
Notes 1. Interrupt mask bit in individual interrupt request source 2. Macro service enable flag in individual interrupt request source 3. Interrupt enable flag in program status word (PSW) 4. Pending interrupt requests are acknowledged when acknowledgment becomes possible. 5. Bit in interrupt mode control register (IMC)
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(1) STOP mode release by NMI input The oscillator resumes oscillation when the valid edge specified by external interrupt mode register 0 (INTM0) is input to the NMI input. STOP mode is released after the oscillation stabilization time specified by the oscillation stabilization time specification register (OSTS). When the PD784938 is released from STOP mode, if a non-maskable interrupt by NMI pin input can be acknowledged, a branch is made to the NMI interrupt service program. If the interrupt cannot be acknowledged (if the STOP mode is set in an NMI interrupt service program, etc.), execution is resumed from the instruction following the instruction that set the STOP mode, and a branch is made to the NMI interrupt service program when acknowledgment becomes possible (by execution of an RETI instruction, etc.). See 23.6 Non-maskable Interrupt Acknowledgment Operation for details of NMI interrupt acknowledgment. Figure 25-5. STOP Mode Release by NMI Input
STOP
Oscillator fXX/2 STP F/F1 STP F/F2 NMI input Rising edge specified
Oscillator stopped
Oscillation stabilization count time
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(2) STOP mode release by INTP4 or INTP5 input When masking of interrupts by INTP4 and INTP5 input is released and macro service is disabled, the oscillator resumes oscillation when the valid edge specified by external interrupt mode register 1 (INTM1) is input to the INTP4 or INTP5 input. Following this, STOP mode is released after the oscillation stabilization time specified by the oscillation stabilization time specification register (OSTS) elapses. When the PD784938 is released from STOP mode, if an interrupt can be acknowledged when the interrupt enable flag (IE) is set (to 1), a branch is made to the interrupt service program. If the interrupt cannot be acknowledged and if the IE flag is cleared (to 0), execution is resumed from the instruction following the instruction that set the STOP mode. See 23.7 Maskable Interrupt Acknowledgment Operation for details of interrupt acknowledgment. Figure 25-6. STOP Mode Release by INTP4/INTP5 Input
STOP
Oscillator fXX/2 STP F/F1 STP F/F2 INTP4, INTP5 input Rising edge specified
Oscillation stopped
Oscillation stabilization count time
(3) STOP mode release by RESET input When RESET input falls from high to low and the reset state is established, the oscillator resumes oscillation. The oscillation stabilization time should be secured while RESET is active. Thereafter, normal operation is started when RESET rises. Unlike an ordinary reset operation, data memory retains its contents prior to STOP mode setting.
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25.5 IDLE Mode 25.5.1 IDLE mode setting and operating status The IDLE mode is selected by setting (to 1) both the STP bit and the HLT bit of the standby control (STBC) register. The only writes that can be performed on the STBC are 8-bit data writes by means of a dedicated instruction. IDLE mode setting is therefore performed by means of the "MOV STBC, #byte" instruction. Caution If the IDLE mode is set when the condition to release the HALT mode is satisfied (refer to 25.3.2 HALT mode release), the IDLE mode is not set, but the next instruction is executed or execution branches to a vectored interrupt service program. To accurately set the IDLE mode, clear the interrupt request before setting the IDLE mode. Table 25-6. Operating States in IDLE Mode
Clock oscillator Internal system clock CPU I/O lines Peripheral functions Oscillation continued Stopped Operation stopped Retain state prior to IDLE mode setting All operation excluding watch timer (WM3 = 1, WM6 = 0) stoppedNote Internal RAM Bus lines AD0 to AD7 A8 to A19 RD, WR output ASTB output REFRQ output HLDRQ input HLDAK output Retained High-impedance High-impedance High-impedance High-impedance Retained High-impedance Low level
Note A/D converter operation is stopped, but if the CS bit of the A/D converter mode register (ADM) is set, the current consumption does not decrease. Caution The CS bit of the A/D converter mode (ADM) register should be reset.
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25.5.2 IDLE mode release IDLE mode is released by NMI input, INTP4 input, INTP5 input, INTW input, or RESET input. Table 25-7. IDLE Mode Release and Operations after Release
Release Source MKNote 1 ISMNote 2 IE Note 3 RESET input NMI pin input x x x x x x State after Release -- * Non-maskable interrupt service program not being executed * Low-priority non-maskable interrupt service program being executed * NMI pin input service program being executed * High-priority non-maskable interrupt service program being executed INTP4/INTP5 pin input, INTW input 0 0 1 * Interrupt service program not being executed * Low-priority maskable interrupt service program being executed * PRSL bitNote 5 cleared (to 0) during execution of priority level 3 interrupt service program * Same-priority maskable interrupt service program being executed (If PRSL bitNote 5 is cleared (to 0), excluding execution of priority level 3 interrupt service program) * High-priority interrupt service program being executed 0 1 x 0 0 1 0 x x -- -- IDLE mode maintained Operation after Release Normal reset operation Interrupt request acknowledgment
Execution of instruction after MOV STBC, #byte instruction (interrupt request that released IDLE mode is held pendingNote 4) Interrupt request acknowledgment
Execution of instruction after MOV STBC, #byte instruction (interrupt request that released IDLE mode is held pendingNote 4)
Notes 1. Interrupt mask bit in individual interrupt request source 2. Macro service enable flag in individual interrupt request source 3. Interrupt enable flag in program status word (PSW) 4. Pending interrupt requests are acknowledged when acknowledgment becomes possible. 5. Bit in interrupt mode control register (IMC)
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(1) IDLE mode release by NMI input IDLE mode is released when the valid edge specified by external interrupt mode register 0 (INTM0) is input to the NMI input. When the PD784938 is released from IDLE mode, if a non-maskable interrupt by NMI pin input can be acknowledged, a branch is made to the NMI interrupt service program. If the interrupt cannot be acknowledged (if the IDLE mode is set in an NMI interrupt service program, etc.), execution is resumed from the instruction following the instruction that set the IDLE mode, and a branch is made to the NMI interrupt service program when acknowledgment becomes possible (by execution of an RETI instruction, etc.). See 23.6 Non-maskable Interrupt Acknowledgment Operation for details of NMI interrupt acknowledgment. (2) IDLE mode release by INTP4 or INTP5 input When masking of interrupts by INTP4 and INTP5 input is released and macro service is disabled, IDLE mode is released when the valid edge specified by external interrupt mode register 1 (INTM1) is input to the INTP4 or INTP5 input. When the PD784938 is released from IDLE mode, if an interrupt can be acknowledged when the interrupt enable flag (IE) is set (to 1), a branch is made to the interrupt service program. If the interrupt cannot be acknowledged and if the IE flag is cleared (to 0), execution is resumed from the instruction following the instruction that set the IDLE mode. See 23.7 Maskable Interrupt Acknowledgment Operation for details of interrupt acknowledgment. (3) IDLE mode release by RESET input When RESET input falls from high to low and the reset state is established, the oscillator resumes oscillation. The oscillation stabilization time should be secured while RESET is active. Thereafter, normal operation is started when RESET rises. Unlike an ordinary reset operation, data memory retains its contents prior to IDLE mode setting.
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25.6 Check Items when STOP Mode/IDLE Mode is Used Check items required to reduce the current consumption when STOP mode/IDLE mode is used are shown below. (1) Is the output level of each output pin appropriate? The appropriate output level for each pin varies according to the next-stage circuit. You should select the output level that minimizes the current consumption. * If high level is output when the input impedance of the next-stage circuit is low, a current will flow from the power supply to the port, resulting in an increased current consumption. This applies when the next-stage circuit is a CMOS IC, etc. When the power supply is off, the input impedance of a CMOS IC is low. In order to suppress the current consumption, or to prevent an adverse effect on the reliability of the CMOS IC, low level should be output. If a high level is output, latchup may result when power is turned on again. * Depending on the next-stage circuit, inputting low level may increase the current consumption. In this case, highlevel or high-impedance output should be used to reduce the current consumption. * If the next-stage circuit is a CMOS IC, the current consumption of the CMOS IC may increase if the output is made high-impedance when power is supplied to it (the CMOS IC may also be overheated and damaged). In this case you should output an appropriate level, or pull the output high or low with a resistor. The method of setting the output level depends on the port mode. * When a port is in control mode, the output level is determined by the status of the on-chip hardware, and therefore the on-chip hardware status must be taken into consideration when setting the output level. * In port mode, the output level can be set by writing to the port output latch and port mode register by software. When a port is in control mode, its output level can be set easily by changing to port mode.
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(2) Is the input pin level appropriate? The voltage level input to each pin should be in the range between VSS potential and VDD potential. If a voltage outside this range is applied, the current consumption will increase and the reliability of the PD784938 may be adversely affected. Also ensure that an intermediate potential is not applied. (3) Are pull-up resistors necessary? An unnecessary pull-up resistor will increase the current consumption and cause a latchup of other devices. A mode should be specified in which pull-up resistors are used only for parts that require them. If there is a mixture of parts that do and do not require pull-up resistors, for parts that do, you should connect a pullup resistor externally and specify a mode in which the on-chip pull-up resistor is not used. (4) Is processing of the address bus, address/data bus, etc., appropriate? In STOP mode and IDLE mode, the address bus, address/data bus, RD and WR pins become high-impedance. Normally, these pins are pulled high with a pull-up resistor. If this pull-up resistor is connected to the backed-up power supply, then if the input impedance of circuitry connected to the non-backed-up power supply is low, a current will flow through the pull-up resistor, and the current consumption will increase. Therefore, the pull-up resistor should be connected to the non-backed-up power supply side as shown in Figure 25-7. Also, in STOP mode and IDLE mode the ASTB pin also becomes high impedance, and the REFRQ/HLDAK pin adopts a fixed level. Countermeasures should be taken with reference to the points noted in (to 1). Figure 25-7. Example of Address/Data Bus Processing
Backed-up power supply VDD VDD CMOS IC, etc. IN/OUT Non-backed-up power supply
PD784938
ADn (n = 0 to 7) VSS
VSS
The voltage level input to the WAIT/HLDRQ pin should be in the range between VSS potential and VDD potential. If a voltage outside this range is applied, the current consumption will increase and the reliability of the PD784938 may be adversely affected. (5) A/D converter The current flowing to the AVDD, AVREF1 pins can be reduced by clearing (0) the CS bit (bit 7) of the A/D converter mode register (ADM). The current can be further reduced, if required, by cutting the current supply to the AVDD, AVREF1 pins with external circuitry. Make sure that the AVDD pin is not at the same potential as the VDD pin. Unless power is supplied to the AVDD pin in the STOP mode, not only does the current consumption increase, but the reliability is also affected.
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25.7 Cautions (1) If HALT/STOP/IDLE mode (standby mode hereafter) setting is performed when a condition that release HALT mode (refer to 25.3.2 HALT mode release) is satisfied, standby mode is not entered, and execution of the next instruction, or a branch to a vectored interrupt service program, is performed. To ensure that a definite standby mode setting is made, interrupt requests should be cleared, etc. before entering standby mode. (2) When crystal/ceramic oscillation is used, the EXTC bit must be cleared (to 0) before use. If the EXTC bit is set (to 1), oscillation will stop. (3) If the STOP mode is set when the EXTC bit of the oscillation stabilization time specification (OSTS) register is cleared (to 0), the X1 pin is shorted internally to VSS (GND potential) to suppress clock generator leakage. Therefore, when the STOP mode is used in a system that uses an external clock, the EXTC bit of OSTS must be set (to 1). If STOP mode setting is performed in a system to which an external clock is input when the EXTC bit of the OSTS is cleared (to 0), the PD784938 may suffer damage or reduced reliability. When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the clock input to the X1 pin, to the X2 pin (refer to 4.3.1 Clock oscillator). (4) In STOP mode and IDLE mode, the CS bit of the A/D converter mode ADM register should be cleared (to 0).
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26.1 Reset Function When low level is input to the RESET input pin, a system reset is affected, the various hardware units are set to the states shown in Table 26-2, and all pins except the power supply pins and the X1 and X2 pins are placed in the highimpedance state. Table 26-1 shows the pin statuses on reset and after reset release. When the RESET input changes from low to high level, the reset state is released, the contents of address 00000H of the reset vector table are set in bits 0 to 7 of the program counter (PC), the contents of address 00001H in bits 8 to 15, and 0000B in bits 16 to 19, a branch is made, and program execution is started at the branch destination address. A reset start can therefore be performed from any address in the base area. The contents of the various registers should be initialized as required in the program in the base area. To prevent misoperation due to noise, the RESET input pin incorporates an analog delay noise elimination circuit (see Figure 26-1). Figure 26-1. Reset Signal Acknowledgment
Execution of instruction at reset start address
Delay
Delay
Delay PC initialization, etc.
RESET (input)
Internal reset signal
Reset start
Reset end
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In a reset operation upon powering on, the RESET signal must be kept active until the oscillation stabilization time has elapsed. As the time taken for oscillation stabilization is influenced by the crystal oscillator/ceramic resonator used and the capacitance of capacitor connected, please contact the manufacturer of the crystal oscillator/ceramic resonator for details. Figure 26-2. Power-On Reset Operation
Execution of instruction at reset start address
Oscillation stabilization time
Delay PC initialization, etc.
VDD
RESET (input)
Internal reset signal
Reset end
Remark fCLK: Internal system clock frequency Table 26-1. Pin Statuses During Reset Input and After Reset Release
Pin Name P00 to P07 P10 to P17 P20/NMI to P27/SI P30/RxD/SI1 to P37/TO3 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD, P65/WR P66/WAIT, P67/REFRQ P70/ANI0 to P77/ANI7 P90 to P97 P100 to P107/SO3 ASTB/CLKOUT PWM0, PWM1 TX RX Input/Output Input/output Input/output Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Output Output Output Input On Reset Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Directly After Reset Release Hi-Z (input port mode) Hi-Z (input port mode) Hi-Z (input port) Hi-Z (input port mode) Hi-Z (input port mode) Hi-Z (input port mode) Hi-Z (input port mode) Hi-Z (input port mode) Hi-Z (input port mode) Hi-Z (input port mode) Hi-Z (input port mode) Hi-Z (input port mode) 0 Low level output Low level output Hi-Z (input port)
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Table 26-2. Hardware Status After Reset (1/2)
Hardware Program counter (PC) State After Reset Set with contents of reset vector table (0000H/0001H). UndefinedNote 02H UndefinedNote
Stack pointer (SP) Program status word (PSW) On-chip RAM Data memory General-purpose registers Ports Port mode registers Ports 0, 1, 2, 3, 4, 5, 6, 7, 9, 10 PM0, 1, 3, 4, 5, 6, 7, 9, 10
Undefined (high impedance) FFH 00H 00H 00H 0000H Undefined
Port mode control registers (PMC1, PMC3, PMC10) Pull-up resistor option register (PUOL, PUOH) Real-time output port control register (RTPC) Timer/counter Timer counters (TM0, TM1W, TM2W, TM3W) Compare registers (CR00, CR01, CR10LW, CR20W, CR30W) Capture registers (CR02, CR12W, CR22W) Capture/compare registers (CR11W, CR21W) Timer control registers (TMC0, TMC1) Timer output control register (TOC) Capture/compare control registers CRC0 CRC1, CRC2 Prescaler mode registers (PRM0, PRM1) One-shot pulse output control register (OSPC) PWM PWM control register (PWMC) PWM prescaler register (PWPR) PWM modulo registers (PWM0, PWM1) A/D converter A/D converter mode register (ADM) A/D conversion result register (ADCR) A/D current cut select register (IEAD) ROM correction ROM correction address register H (CORAH) ROM correction address register L (CORAL) ROM correction control register (CORC) Serial interface Clocked serial interface mode registers (CSIM, CSIM1, CSIM2, CSIM3) Serial shift registers (SIO, SIO1, SIO2, SIO3) Asynchronous serial interface mode registers (ASIM, ASIM2) Asynchronous serial interface status registers (ASIS, ASIS2) Serial receive buffers (RXB, RXB2) Serial transmit shift registers (TXS, TXS2) Baud rate generator control registers (BRGC, BRGC2)
00H
10H 00H 00H 00H 05H 00H Undefined 00H Undefined 00H 00H 0000H 00H 00H Undefined 00H 00H Undefined Undefined 00H
Note When HALT mode, STOP mode, or IDLE mode is released by RESET input, the value before that mode was set is retained.
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Table 26-2. Hardware Status After Reset (2/2)
Hardware Clock output function (CLOM) Watch timer mode register (WM) Memory extension mode register (MM) Programmable wait control registers PWC1 PWC2 Refresh function Refresh mode register (RFM) Refresh area specification register (RFA) Hold mode register (HLDM) Interrupts Interrupt control registers (PIC0, PIC1, PIC2, PIC3, PIC4, PIC5, CIC00, CIC01, CIC10, CIC11, CIC20, CIC21, CIC30, ADIC, SERIC, SRIC, STIC, SERIC2, SRIC2, STIC2, CSIIC, CSIIC1, CSIIC2, IEIC1, IEIC2, WIC, CSIIC3) Interrupt mask registers MK0 MK1 In-service priority register (ISPR) Interrupt mode control register (IMC) External interrupt mode registers (INTM0, INTM1) Sampling clock selection register (SCS0) Standby control register (STBC) Oscillation stabilization time specification register (OSTS) Internal memory size switching register (IMS) IEBus controller Bus control register (BCR) Unit address register (UAR) Slave address register (SAR) Partner address register (PAR) Control data register (CDR) Telegraph-length register (DLR) Data register (DR) Unit status register (USR) Interrupt status register (ISR) Slave status register (SSR) Success count register (SCR) Communication count register (CCR) 41H 01H 20H 00H 01H State After Reset 00H 00H 20H AAH AAAAH 00H 00H 00H 43H
FFFFH FFH 00H 00H 00H 00H 30H 00H FFH 00H 0000H
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Figure 26-3. Reset Input Timing
RESET (input) Hi-Z
ASTB (output)
Other I/O ports
Hi-Z
Reset period
Reset release - instruction execution period
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26.2 Caution Reset input when powering on must remain at the low level until oscillation stabilizes after the supply voltage has reached the prescribed voltage.
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27.1 ROM Correction Functions
PD784938 converts part of the program within the mask ROM into the program within the internal expansion ROM.
The use of ROM correction enables command bugs discovered in the mask ROM to be repaired, and change the flow of the program. ROM correction can be used in a maximum of four locations within the internal ROM (program). Caution Note that ROM correction cannot perform emulation in the in-circuit emulator (IE-784000-R, IE-784000R-EM). In more detail, the command addresses that require repair from the inactive memory connected to an external microcontroller by a user program and the repair command codes are loaded into the peripheral RAM. The above addresses and the internal ROM access addresses are compared by the comparator built into the microcontroller during execution of internal ROM programs (during command fetch), and internal ROM's output data is then converted to call command (CALLT) codes and output when a match is determined. When the CALLT command codes are changed to valid commands by the CPU and executed, the CALLT table is referenced, and the process routine and other peripheral RAM are branched. At this point, a CALLT table is prepared for each repair address for referencing purposes. Four repair address can be set for the PD784938. Matches with address pointer 0: Matches with address pointer 1: Matches with address pointer 2: Matches with address pointer 3: CALLT table (0078H) Conversion command code: FCH CALLT table (007AH) Conversion command code: FDH CALLT table (007CH) Conversion command code: FEH CALLT table (007EH) Conversion command code: FFH Cautions 1. As it is necessary to reserve four locations for the CALLT tables when the ROM correction function is used (0078H, 007AH, 007CH, 007EH), ensure that these are not used for other applications. However, the CALLT tables can be used if the ROM correction function is not being used. 2. If there are two or more channels for which the correction operation is enabled, do not set the same correction address. 3. Be sure to set the address where the start command code is stored as the correction address. The differences between 78K/IV ROM correction and 78K/0 ROM correction are shown in Table 27-1.
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Table 27-1. Differences between 78K/IV ROM Correction and 78K/0 ROM Correction
Difference Generated command codes 78K/IV CALLT instruction (1-byte instruction: FCH, FDH, FEH, FFH) Instruction fetch only None As there is a possibility that the addresses match owing to an invalid fetch, the status is not necessary CALLT Table 0078H, 007AH, 007CH, 007EH Peripheral RAM 78K/0
Address comparison conditions Correction status flag
Instruction fetch only Yes
Jump destination address during correction
Fixed address on the peripheral RAM
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27.2 ROM Correction Configuration ROM correction is composed of the following hardware. Table 27-2. ROM Correction Configuration
Item Register Control register Configuration ROM correction address register H, L (CORAH, CORAL) ROM correction control register (CORC)
A ROM correction block diagram is shown in Figure 27-1, and Figure 27-2 shows an example of memory mapping. Figure 27-1. ROM Correction Block Diagram
Program counter (PC)
Match Comparator Correction branch process request signal (CALLT command)
Correction address pointer n
ROM correction address register (CORAH, CORAL)
CORENn CORCHm ROM correction control register (CORC) Internal bus
Remark n = 0 to 3, m = 0, 1
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Figure 27-2. Memory Mapping Example (PD784938)
03FFFFH Internal ROM 00FFFFH SFR 00FF00H 00FEFFH Internal RAM 00D600H 00D5FFH 00FD00H 00FCFFH Peripheral RAM (correction program) 00D600H 00FEFFH High-speed internal RAM
00007FH (Reference table 3) (Reference table 2) (Reference table 1) (Reference table 0) CALLT Table area 000040H 00003FH
Internal ROM
Vector table area
000000H
000000H
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(1) ROM correction address register (CORAH, CORAL) The register that sets the header address (correction address) of the command within the mask ROM that needs to be repaired. A maximum of four program locations can be repaired with ROM correction. First of all, the channel is selected with bit 0 (CORCH0) and bit 1 (CORCH1) of the ROM correction control register (CORC), and the address is then set in the specified channel's address pointer when the address is written in CORAH and CORAL. Figure 27-3. ROM Correction Address Register (CORAH, CORAL) Format
7 CORAH 0 Address FF79H After reset 00H R/W R/W
15 CORAL
0
Address FF7AH
After reset 0000H
R/W R/W
(2) Comparator The ROM correction address registers H and L (CORAH, CORAL) normally compare the corrected address value with the fetch register value. If any of the ROM correction control register (CORC) bits between bit 4 to bit 7 (COREN0 to 3) are 1 and the correct address matches the fetch address value, a table reference instruction (CALLT) is issued from the ROM correction circuit. 27.3 Control Register for ROM Correction ROM correction is controlled by the ROM correction control register (CORC). (1) ROM correction control register (CORC) The register that controls the issuance of the table reference instruction (CALLT) when the correct address set in ROM correction address registers H and L (CORAH, CORAL) match the value of the fetch address. This is composed of a correction enable flag (COREN0 to 3) that enables or disables match detection with the comparator, and four channel correction pointers. CORC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CORC to 00H.
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Figure 27-4. ROM Correction Control Register (CORC) Format
Address 0FF88H Symbol CORC 7 COREN3 After reset 00H 6 COREN2 5 COREN1 R/W 4 COREN0 3 0 2 0 1 CORCH1 0 CORCH0
CORENn
Controls the Match Detection for the ROM Correction Address Register and the Fetch Address. Disabled Enabled
0 1
CORCH1 CORCH0 0 0 1 1 0 1 0 1
Channel Selection Address pointer channel 0 Address pointer channel 1 Address pointer channel 2 Address pointer channel 3
Remark n = 0 to 3
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27.4 Use of ROM Correction <1> The correct address and post-correction instruction (correction program) are stored in the microcontroller external non-volatile memory (EEPROM). <2> A substitute instruction is read from the non-volatile memory with the use of a serial interface when the initialization program is running after being reset, and this is stored in the peripheral RAM and external memory. The correction channel is then selected, the address for the command that requires correction is read and set in the ROM correction address registers (CORAH, CORAL), and the correction enable flag (COREN0 to 3) is set at 1. A maximum of four locations can be set. <3> Execute the CALLT instruction during execution of the corrected address.
Program execution (internal ROM)
Correct address executed?
No
Yes
CALLT execution
<4> CALLT routine branch When matched with address pointer 0: CALLT table (0078H) When matched with address pointer 1: CALLT table (007AH) When matched with address pointer 2: CALLT table (007CH) When matched with address pointer 3: CALLT table (007EH) <5> Execute substitute instruction <6> Add +3 to the stack pointer (SP) <7> Restore to any addresses with the branch instruction (BR)
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27.5 Conditions for Executing ROM Correction In order to use the ROM correction function, it is necessary for the external environment and program to satisfy the following conditions. (1) External environment Must be connected externally to an non-volatile memory, and be configured to read that data. (2) Target program The data setting instruction for CORC, CORAH and CORAL will be previously annotated in the target program (program stored in the ROM). The set-up data (the items written in lower-case in the set-up example below) must be read from the external non-volatile memory, and the correct number of required correction pointers must be set. Example of four pointer settings MOV MOVW MOV MOV MOVW MOV MOV MOVW MOV MOV MOV MOV MOV CORC, #00H; Specified channel 0 Sets the channel 0 matching address Specified channel 1 Sets the channel 1 matching address Specified channel 2 Sets the channel 2 matching address Specified channel 3 Sets the channel 3 matching address ; Sets 00H when correction is disabled ; Sets F0H when correction is operated BR BR ; NOMAL instruction ; next instruction (3) Setting the branch instruction in the CALLT table. In the case of the above program, the header address for the BR!!COR_ADDR instruction is specified. (COR ADDR indicates the address where the correction program is located.) The reason for this being branched into the CALLT instruction and BR instruction is owing to the fact that only the base area can be branched with CALLT. There is no necessity to branch into two levels when it is to be attached to the RAM base area with the LOCATION instruction. $NORMAL ! ! COR ADDR; Specifies the address of the correction program CORAL, #ch0 datal; CORC, #01H;
CORAH, #ch0 datah; Sets the channel 0 matching address CORAL, #ch1 datal; CORC, #02H;
CORAH, #ch1 datah; Sets the channel 1 matching address CORAL, #ch2 datal; CORC, #chH;
CORAH, #ch2 datah; Sets the channel 2 matching address CORAL, #ch3 datah; Sets the channel 3 matching address CORAH, #ch3 datal; CORC, #romcor en
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The PD78F4938 is a flash memory version of the PD784938 Subseries. The PD78F4938 has on-chip flash memory that allows write, erase, and rewrite of programs in the state in which it is mounted on the substrate. Table 28-1 shows the differences between the flash memory version (PD78F4938) and the mask ROM versions (PD784935, 784936, 784937, and 784938). Table 28-1. Differences between the PD78F4938 Mask ROM Versions
Item Internal ROM type Internal ROM capacity
PD78F4938
Flash memory 256 Kbytes
Mask ROM Versions Mask ROM
PD784935: PD784936: PD784937: PD784938: PD784935: PD784936: PD784937: PD784938:
Not available Available Not available
96 Kbytes 128 Kbytes 192 Kbytes 256 Kbytes 5,120 bytes 6,656 bytes 8,192 bytes 10,240 bytes
Internal RAM capacity
10,240 bytes
Internal memory size switching register (IMS) IC pin VPP pin
Available Not available Available
Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then massproducing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version.
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28.1 Internal Memory Size Switching Register (IMS) IMS is a register to prevent a certain part of the internal memory from being used by software. By setting the IMS, it is possible to establish a memory map that is the same as that of mask ROM version with a different internal memory (ROM, RAM) with capacity. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to FFH. Figure 28-1. Internal Memory Size Switching Register (IMS) Format
Address Symbol IMS 0FFFCH 7 1 After reset FFH 6 1 5 ROM1 W 4 ROM0 3 1 2 1 1 RAM1 0 RAM0
ROM1 0 0 1 1
ROM0 0 1 0 1 256 Kbytes 96 Kbytes 128 Kbytes 192 Kbytes
Internal ROM Capacity Selection
RAM1 0 0 1 1
RAM0 0 1 0 1
Internal RAM Capacity Selection 10,240 bytes 5,120 bytes 6,656 bytes 8,192 bytes
Caution IMS is not available for mask ROM versions (PD784935, 784936, 784937, and 784938). The IMS settings to create the same memory map as mask ROM versions are shown in Table 28-2. Table 28-2. Internal Memory Size Switching Register (IMS) Settings
Relevant Mask ROM Version IMS Setting DDH EEH FFH CCH
PD784935 PD784936 PD784937 PD784938
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28.2 Flash Memory Programming Using Flashpro II and Flashpro III Flash memory can be written while mounted on the target system (on-board writing). Connect the dedicated flash programmer (Flashpro II (part number FL-PR2), Flashpro III (part number FL-PR3 and FG-FP3)) to the host computer and target system for programming. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro II or Flashpro III. Remark FL-PR2 and FL-PR3 are products of Naito Densei Machida Mfg. Co., Ltd. 28.2.1 Selecting communication mode The Flashpro II or III is used to write data into a flash memory by serial communications. Select the communication mode for writing from Table 28-3. Figure 28-2 shows the format used to select the communication mode. Each communication mode is selected with the number of VPP pulses shown in Table 28-3. Table 28-3. Communication Mode
Communication Mode 3-wire serial I/O Number of Channels 1 Pins Used SCK3/P105 SI3/P106 SO3/P107 RxD/P30 TxD/P31 Number of VPP Pulses 1
UART
1
8
Caution Always select the communication mode using the number of VPP pulses shown in Table 28-3. Figure 28-2. Communication Mode Selection Format
VPP pulses 10 V VPP VDD VSS VDD RESET VSS Flash memory write mode 1 2 n
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28.2.2 Flash memory programming functions By transmitting and receiving various commands and data by the selected communication mode, operations such as writing to the flash memory are performed. Table 28-4 shows the major functions. Table 28-4. Flash Memory Programming Functions
Function Batch erase Block erase Batch blank check Block blank check Data write Erase the entire memory contents. Erase the contents of the specified memory block where one memory block is 16 Kbytes. Checks the erase state of the entire memory. Checks the erase state of the specified block. Writes to the flash memory based on the start write address and the number of data written (number of bytes). Compares the data input to the contents of the entire memory. Compares the data input to the contents of the specified memory block. Description
Batch verify Block verify
Verification for the flash memory entails supplying the data to be verified from an external source via a serial interface, and then outputting the existence of unmatched data to the external source after referencing the blocks or all of the data. Consequently, the flash memory is not equipped with a read function, and it is not possible for third parties to read the contents of the flash memory with the use of the verification function.
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28.2.3 Connecting Flashpro II or Flashpro III The connection between the Flashpro II or Flashpro III and the PD78F4938 differs with the communication mode (3wire serial I/O or UART). Figures 28-3 and 28-4 are the connection diagrams in each case. Figure 28-3. Flashpro II and Flashpro III Connection in 3-Wire Serial I/O Mode
Flashpro II or Flashpro III VPP VDD RESET SCK SO SI VSS
PD78F4938
VPP VDD RESET SCK SI SO VSS
Figure 28-4. Flashpro II and Flashpro III Connection in UART Mode
Flashpro II or Flashpro III VPP VDD RESET SO SI VSS
PD78F4938
VPP VDD RESET RxD TxD VSS
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29.1 Conventions (1) Operand identifiers and descriptions (1/2)
Identifier r, r'Note 1 r1Note 1 r2 r3 rp, rp'Note 2 rp1Note 2 rp2 rg, rg' sfr sfrp postNote 2 Description X (R0), A (R1), C (R2), B (R3), R4, R5, R6, R7, R8, R9, R10, R11, E (R12), D (R13), L (R14), H (R15) X (R0), A (R1), C (R2), B (R3), R4, R5, R6, R7 R8, R9, R10, R11, E (R12), D (R13), L (R14), H (R15) V, U, T, W AX (RP0), BC (RP1), RP2, RP3, VP (RP4), UP (RP5), DE (RP6), HL (RP7) AX (RP0), BC (RP1), RP2, RP3 VP (RP4), UP (RP5), DE (RP6), HL (RP7) VVP (RG4), UUP (RG5), TDE (RG6), WHL (RG7) Special function register symbol (see Special Function Register Application Table) Special function register symbol (register for which 16-bit operation is possible: see Special Function Register Application Table) AX (RP0), BC (RP1), RP2, RP3, VP (RP4), UP (RP5)/PSW, DE (RP6), HL (RP7) Multiple descriptions are permissible. However, UP is only used with PUSH/POP instructions, and PSW with PUSHU/POPU instructions. [TDE], [WHL], [TDE+], [WHL+], [TDE-], [WHL-], [VVP], [UUP]: Register indirect addressing [TDE+byte], [WHL+byte], [SP+byte], [UUP+byte], [VVP+byte]: Based addressing imm24 [A], imm24 [B], imm24 [DE], imm24 [HL]: Indexed addressing [TDE+A], [TDE+B], [TDE+C], [WHL+A], [WHL+B], [WHL+C], [VVP+DE], [VVP+HL]: Based indexed addressing All mem except [WHL+] and [WHL-] [TDE], [WHL] [AX], [BC], [RP2], [RP3], [VVP], [UUP], [TDE], [WHL]
mem
mem1 mem2 mem3
Notes 1. Setting the RSS bit to 1 enables R4 to R7 to be used as X, A, C, and B, but this function should only be used when using a 78K/III Series program. 2. Setting the RSS bit to 1 enables RP2 and RP3 to be used as AX and BC, but this function should only be used when using a 78K/III Series program.
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(1) Operand identifiers and descriptions (2/2)
Identifier Note saddr, saddr' saddr1 saddr2 saddrp saddrp1 saddrp2 saddrg saddrg1 saddrg2 addr24 addr20 addr16 addr11 addr8 addr5 imm24 word byte bit n locaddr Description
FD20H to FF1FH immediate data or label FE00H to FEFFH immediate data or label FD20H to FDFFH, FF00H to FF1FH immediate data or label FD20H to FF1EH immediate data or label (16-bit operation) FE00H to FEFFH immediate data or label (16-bit operation) FD20H to FDFFH, FF00H to FF1EH immediate data or label (16-bit operation) FD20H to FEFDH immediate data or label (24-bit operation) FE00H to FEFDH immediate data or label (24-bit operation) FD20H to FDFFH immediate data or label (24-bit operation) 0H to FFFFFFH immediate data or label 0H to FFFFFH immediate data or label 0H to FFFFH immediate data or label 800H to FFFH immediate data or label 0FE00H to 0FEFFHNote immediate data or label 40H to 7EH immediate data or label 24-bit immediate data or label 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label 3-bit immediate data 00H or 0FH
Note The addresses shown here apply when 00H is specified by the LOCATION instruction. When 0FH is specified by the LOCATION instruction, F0000H should be added to the address values shown.
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(2) Operand column symbols
Symbol + - # ! !! $ $! / [] [%] Auto-increment Auto-decrement Immediate data 16-bit absolute address 24-bit/20-bit absolute address 8-bit relative address 16-bit relative address Bit inversion Indirect addressing 24-bit indirect addressing Description
(3) Flag column symbols
Symbol (Blank) 0 1 x P V R No change Cleared to 0 Set to 1 Set or cleared depending on result P/V flag operates as parity flag P/V flag operates as overflow flag Previously saved value is restored Description
(4) Operation column symbols
Symbol jdisp8 jdisp16 PCHW PCLW Description Signed two's complement data (8 bits) indicating relative address distance between start address of next instruction and branch address Signed two's complement data (16 bits) indicating relative address distance between start address of next instruction and branch address PC bits 16 to 19 PC bits 0 to 15
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(5) Number of bytes of instruction that includes mem in operands
mem Mode Register Indirect Addressing 2Note Based Addressing 3 Indexed Addressing 5 Based Indexed Addressing 2
Number of bytes
1
Note One-byte instruction only when [TDE], [WHL], [TDE+], [TDE-], [WHL+], or [WHL-] is written as mem in an MOV instruction. (6) Number of bytes of instruction that includes saddr, saddrp, r, or rp in operands For some instructions that include saddr, saddrp, r, or rp in their operands, two "Bytes" entries are given, separated by a slash ("/"). The entry that applies is shown in the table below.
Identifier saddr saddrp r rp Left-Hand "Bytes" Figure saddr2 saddrp2 r1 rp1 Right-Hand "Bytes" Figure saddr1 saddrp1 r2 rp2
(7) Description of instructions that include mem in operands and string instructions Operands TDE, WHL, VVP, and UUP (24-bit registers) can also be written as DE, HL, VP, and UP respectively. However, they are still treated as TDE, WHL, VVP, and UUP (24-bit registers) when written as DE, HL, VP, and UP.
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29.2 List of Operations (1) 8-bit data transfer instruction: MOV
Mnemonic Operands Bytes Operation S MOV r, #byte saddr, #byte sfr, #byte !addr16, #byte !!addr24, #byte r, r' A, r A, saddr2 r, saddr saddr2, A saddr, r A, sfr r, sfr sfr, A sfr, r saddr, saddr' r, !addr16 !addr16, r r, !!addr24 !!addr24, r A, [saddrp] A, [%saddrg] A, mem [saddrp], A [%saddrg], A mem, A PSWL, #byte PSWH, #byte PSWL, A PSWH, A A, PSWL A, PSWH r3, #byte A, r3 r3, A 2/3 3/4 3 5 6 2/3 1/2 2 3 2 3 2 3 2 3 4 4 4 5 5 2/3 3/4 1 to 5 2/3 3/4 1 to 5 3 3 2 2 2 2 3 2 2 r byte (saddr) byte sfr byte (saddr16) byte (addr24) byte r r' Ar A (saddr2) r (saddr) (saddr2) A (saddr) r A sfr r sfr sfr A sfr r (saddr) (saddr') r (addr16) (addr16) r r (addr24) (addr24) r A ((saddrp)) A ((saddrg)) A (mem) ((saddrp)) A ((saddrg)) A (mem) A PSWL byte PSWH byte PSWL A PSWH A A PSWL A PSWH r3 byte A r3 r3 A x x x x x x x x x x Z Flags AC P/V CY
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(2) 16-bit data transfer instruction: MOVW
Mnemonic Operands Bytes Operation S MOVW rp, #word saddrp, #word sfrp, #word !addr16, #word !!addr24, #word rp, rp' AX, saddrp2 rp, saddrp saddrp2, AX saddrp, rp AX, sfrp rp, sfrp sfrp, AX sfrp, rp saddrp, saddrp' rp, !addr16 !addr16, rp rp, !!addr24 !!addr24, rp AX, [saddrp] AX, [%saddrg] AX, mem [saddrp], AX [%saddrg], AX mem, AX 3 4/5 4 6 7 2 2 3 2 3 2 3 2 3 4 4 4 5 5 3/4 3/4 2 to 5 3/4 3/4 2 to 5 rp word (saddrp) word sfrp word (addr16) word (addr24) word rp rp' AX (saddrp2) rp (saddrp) (saddrp2) AX (saddrp) rp AX sfrp rp sfrp sfrp AX sfrp rp (saddrp) (saddrp') rp (addr16) (addr16) rp rp (addr24) (addr24) rp AX ((saddrp)) AX ((saddrg)) AX (mem) ((saddrp)) AX ((saddrg)) AX (mem) AX Z Flags AC P/V CY
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(3) 24-bit data transfer instruction: MOVG
Mnemonic Operands Bytes Operation S MOVG rg, #imm24 rg, rg' rg, !!addr24 !!addr24, rg rg, saddrg saddrg, rg WHL, [%saddrg] [%saddrg], WHL WHL, mem1 mem1, WHL 5 2 5 5 3 3 3/4 3/4 2 to 5 2 to 5 rg imm24 rg rg' rg (addr24) (addr24) rg rg (saddrg) (saddrg) rg WHL ((saddrg)) ((saddrg)) WHL WHL (mem1) (mem1) WHL Z Flags AC P/V CY
(4) 8-bit data exchange instruction: XCH
Mnemonic Operands Bytes Operation S XCH r, r' A, r A, saddr2 r, saddr r, sfr saddr, saddr' r, !addr16 r, !!addr24 A, [saddrp] A, [%saddrg] A, mem 2/3 1/2 2 3 3 4 4 5 2/3 3/4 2 to 5 r r' Ar A (saddr2) r (saddr) r sfr (saddr) (saddr') r (addr16) r (addr24) A ((saddrp)) A ((saddrg)) A (mem) Z Flags AC P/V CY
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(5) 16-bit data exchange instruction: XCHW
Mnemonic Operands Bytes Operation S XCHW rp, rp' AX, saddrp2 rp, saddrp rp, sfrp AX, [saddrp] AX, [%saddrg] AX, !addr16 AX, !!addr24 saddrp, saddrp' AX, mem 2 2 3 3 3/4 3/4 4 5 4 2 to 5 rp rp' AX (saddrp2) rp (saddrp) rp sfrp AX ((saddrp)) AX ((saddrg)) AX (addr16) AX (addr24) (saddrp) (saddrp') AX (mem) Z Flags AC P/V CY
(6) 8-bit operation instructions: ADD, ADDC, SUB, SUBC, CMP, AND, OR, XOR
Mnemonic Operands Bytes Operation S ADD A, #byte r, #byte saddr, #byte sfr, #byte r, r' A, saddr2 r, saddr saddr, r r, sfr sfr, r saddr, saddr' A, [saddrp] A, [%saddrg] [saddrp], A [%saddrg], A A, !addr16 A, !!addr24 !addr16, A !!addr24, A A, mem mem, A 2 3 3/4 4 2/3 2 3 3 3 3 4 3/4 3/4 3/4 3/4 4 5 4 5 2 to 5 2 to 5 A, CY A + byte r, CY r + byte (saddr), CY (saddr) + byte sfr, CY sfr + byte r, CY r + r' A, CY A + (saddr2) r, CY r + (saddr) (saddr), CY (saddr) + r r, CY r + sfr sfr, CY sfr + r (saddr), CY (saddr) + (saddr') A, CY A + ((saddrp)) A, CY A + ((saddrg)) ((saddrp)), CY ((saddrp)) + A ((saddrg)), CY ((saddrg)) + A A, CY A + (addr16) A, CY A + (addr24) (addr16), CY (addr16) + A (addr24), CY (addr24) + A A, CY A + (mem) (mem), CY (mem) + A x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x x x x x Flags AC P/V CY x x x x x x x x x x x x x x x x x x x x x V V V V V V V V V V V V V V V V V V V V V x x x x x x x x x x x x x x x x x x x x x
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Mnemonic
Operands
Bytes
Operation S Z x x x x x x x x x x x x x x x x x x x x x
Flags AC P/V CY x x x x x x x x x x x x x x x x x x x x x V V V V V V V V V V V V V V V V V V V V V x x x x x x x x x x x x x x x x x x x x x
ADDC
A, #byte r, #byte saddr, #byte sfr, #byte r, r' A, saddr2 r, saddr saddr, r r, sfr sfr, r saddr, saddr' A, [saddrp] A, [%saddrg] [saddrp], A [%saddrg], A A, !addr16 A, !!addr24 !addr16, A !!addr24, A A, mem mem, A
2 3 3/4 4 2/3 2 3 3 3 3 4 3/4 3/4 3/4 3/4 4 5 4 5 2 to 5 2 to 5
A, CY A + byte + CY r, CY r + byte + CY (saddr), CY (saddr) + byte + CY sfr, CY sfr + byte + CY r, CY r + r' + CY A, CY A + (saddr2) + CY r, CY r + (saddr) + CY (saddr), CY (saddr) + r + CY r, CY r + sfr + CY sfr, CY sfr + r + CY (saddr), CY (saddr) + (saddr') + CY A, CY A + ((saddrp)) + CY A, CY A + ((saddrg)) + CY ((saddrp)), CY ((saddrp)) + A + CY ((saddrg)), CY ((saddrg)) + A + CY A, CY A + (addr16) + CY A, CY A + (addr24) + CY (addr16), CY (addr16) + A + CY (addr24), CY (addr24) + A + CY A, CY A + (mem) + CY (mem), CY (mem) + A + CY
x x x x x x x x x x x x x x x x x x x x x
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Mnemonic
Operands
Bytes
Operation S Z x x x x x x x x x x x x x x x x x x x x x
Flags AC P/V CY x x x x x x x x x x x x x x x x x x x x x V V V V V V V V V V V V V V V V V V V V V x x x x x x x x x x x x x x x x x x x x x
SUB
A, #byte r, #byte saddr, #byte sfr, #byte r, r' A, saddr2 r, saddr saddr, r r, sfr sfr, r saddr, saddr' A, [saddrp] A, [%saddrg] [saddrp], A [%saddrg], A A, !addr16 A, !!addr24 !addr16, A !!addr24, A A, mem mem, A
2 3 3/4 4 2/3 2 3 3 3 3 4 3/4 3/4 3/4 3/4 4 5 4 5 2 to 5 2 to 5
A, CY A - byte r, CY r - byte (saddr), CY (saddr) - byte sfr, CY sfr - byte r, CY r - r' A, CY A - (saddr2) r, CY r - (saddr) (saddr), CY (saddr) - r r, CY r - sfr sfr, CY sfr - r (saddr), CY (saddr) - (saddr') A, CY A - ((saddrp)) A, CY A - ((saddrg)) ((saddrp)), CY ((saddrp)) - A ((saddrg)), CY ((saddrg)) - A A, CY A - (addr16) A, CY A - (addr24) (addr16), CY (addr16) - A (addr24), CY (addr24) - A A, CY A - (mem) (mem), CY (mem) - A
x x x x x x x x x x x x x x x x x x x x x
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Mnemonic
Operands
Bytes
Operation S Z x x x x x x x x x x x x x x x x x x x x x
Flags AC P/V CY x x x x x x x x x x x x x x x x x x x x x V V V V V V V V V V V V V V V V V V V V V x x x x x x x x x x x x x x x x x x x x x
SUBC
A, #byte r, #byte saddr, #byte sfr, #byte r, r' A, saddr2 r, saddr saddr, r r, sfr sfr, r saddr, saddr' A, [saddrp] A, [%saddrg] [saddrp], A [%saddrg], A A, !addr16 A, !!addr24 !addr16, A !!addr24, A A, mem mem, A
2 3 3/4 4 2/3 2 3 3 3 3 4 3/4 3/4 3/4 3/4 4 5 4 5 2 to 5 2 to 5
A, CY A - byte - CY r, CY r - byte - CY (saddr), CY (saddr) - byte - CY sfr, CY sfr - byte - CY r, CY r - r' - CY A, CY A - (saddr2) - CY r, CY r - (saddr) - CY (saddr), CY (saddr) - r - CY r, CY r - sfr - CY sfr, CY sfr - r - CY (saddr), CY (saddr) - (saddr') - CY A, CY A - ((saddrp)) - CY A, CY A - ((saddrg)) - CY ((saddrp)), CY ((saddrp)) - A - CY ((saddrg)), CY ((saddrg)) - A - CY A, CY A - (addr16) - CY A, CY A - (addr24) - CY (addr16), CY (addr16) - A - CY (addr24), CY (addr24) - A - CY A, CY A - (mem) - CY (mem), CY (mem) - A - CY
x x x x x x x x x x x x x x x x x x x x x
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Mnemonic
Operands
Bytes
Operation S Z x x x x x x x x x x x x x x x x x x x x x
Flags AC P/V CY x x x x x x x x x x x x x x x x x x x x x V V V V V V V V V V V V V V V V V V V V V x x x x x x x x x x x x x x x x x x x x x
CMP
A, #byte r, #byte saddr, #byte sfr, #byte r, r' A, saddr2 r, saddr saddr, r r, sfr sfr, r saddr, saddr' A, [saddrp] A, [%saddrg] [saddrp], A [%saddrg], A A, !addr16 A, !!addr24 !addr16, A !!addr24, A A, mem mem, A
2 3 3/4 4 2/3 2 3 3 3 3 4 3/4 3/4 3/4 3/4 4 5 4 5 2 to 5 2 to 5
A - byte r - byte (saddr) - byte sfr - byte r - r' A - (saddr2) r - (saddr) (saddr) - r r - sfr sfr - r (saddr) - (saddr') A - ((saddrp)) A - ((saddrg)) ((saddrp)) - A ((saddrg)) - A A - (addr16) A - (addr24) (addr16) - A (addr24) - A A - (mem) (mem) - A
x x x x x x x x x x x x x x x x x x x x x
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Mnemonic
Operands
Bytes
Operation S Z x x x x x x x x x x x x x x x x x x x x x
Flags AC P/V CY P P P P P P P P P P P P P P P P P P P P P
AND
A, #byte r, #byte saddr, #byte sfr, #byte r, r' A, saddr2 r, saddr saddr, r r, sfr sfr, r saddr, saddr' A, [saddrp] A, [%saddrg] [saddrp], A [%saddrg], A A, !addr16 A, !!addr24 !addr16, A !!addr24, A A, mem mem, A
2 3 3/4 4 2/3 2 3 3 3 3 4 3/4 3/4 3/4 3/4 4 5 4 5 2 to 5 2 to 5
byte r r byte
AA (saddr) (saddr) sfr sfr rr
x x
byte
x x x x x
byte
r' A A (saddr2) r r (saddr)
(saddr) (saddr)
r
x x x
rr
sfr sfr sfr r
(saddr) (saddr) AA
(saddr')
x x x x x x x x x x x
((saddrp)) A A ((saddrg))
A ((saddrg)) ((saddrg)) A A A (addr16) A A (addr24) (addr16) (addr16) A (addr24) (addr24) A A A (mem) (mem) (mem) A
((saddrp)) ((saddrp))
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Mnemonic
Operands
Bytes
Operation S Z x x x x x x x x x x x x x x x x x x x x x
Flags AC P/V CY P P P P P P P P P P P P P P P P P P P P P
OR
A, #byte r, #byte saddr, #byte sfr, #byte r, r' A, saddr2 r, saddr saddr, r r, sfr sfr, r saddr, saddr' A, [saddrp] A, [%saddrg] [saddrp], A [%saddrg], A A, !addr16 A, !!addr24 !addr16, A !!addr24, A A, mem mem, A
2 3 3/4 4 2/3 2 3 3 3 3 4 3/4 3/4 3/4 3/4 4 5 4 5 2 to 5 2 to 5
AA
byte r r byte
(saddr) (saddr) sfr sfr
x x
byte
x x x x x
byte
rr
r' A A (saddr2) r r (saddr)
(saddr) (saddr)
r
x x x
sfr sfr sfr r
rr (saddr) (saddr) AA
(saddr')
x x x x x x x x x x x
((saddrp)) A A ((saddrg))
A ((saddrg)) ((saddrg)) A A A (addr16) A A (addr24) (addr16) (addr16) A (addr24) (addr24) A A A (mem) (mem) (mem) A
((saddrp)) ((saddrp))
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Operands
Bytes
Operation S Z x x x x x x x x x x x x x x x x x x x x x
Flags AC P/V CY P P P P P P P P P P P P P P P P P P P P P
XOR
A, #byte r, #byte saddr, #byte sfr, #byte r, r' A, saddr2 r, saddr saddr, r r, sfr sfr, r saddr, saddr' A, [saddrp] A, [%saddrg] [saddrp], A [%saddrg], A A, !addr16 A, !!addr24 !addr16, A !!addr24, A A, mem mem, A
2 3 3/4 4 2/3 2 3 3 3 3 4 3/4 3/4 3/4 3/4 4 5 4 5 2 to 5 2 to 5
byte r r byte
AA (saddr) (saddr) sfr sfr rr
x x
byte
x x x x x
byte
r' A A (saddr2) r r (saddr)
(saddr) (saddr)
r
x x x
rr
sfr sfr sfr r
(saddr) (saddr) AA
(saddr')
x x x x x x x x x x x
((saddrp)) A A ((saddrg))
A ((saddrg)) ((saddrg)) A A A (addr16) A A (addr24) (addr16) (addr16) A (addr24) (addr24) A A A (mem) (mem) (mem) A
((saddrp)) ((saddrp))
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(7) 16-bit operation instructions: ADDW, SUBW, CMPW
Mnemonic Operands Bytes Operation S ADDW AX, #word rp, #word rp, rp' AX, saddrp2 rp, saddrp saddrp, rp rp, sfrp sfrp, rp saddrp, #word sfrp, #word saddrp, saddrp' SUBW AX, #word rp, #word rp, rp' AX, saddrp2 rp, saddrp saddrp, rp rp, sfrp sfrp, rp saddrp, #word sfrp, #word saddrp, saddrp' CMPW AX, #word rp, #word rp, rp' AX, saddrp2 rp, saddrp saddrp, rp rp, sfrp sfrp, rp saddrp, #word sfrp, #word saddrp, saddrp' 3 4 2 2 3 3 3 3 4/5 5 4 3 4 2 2 3 3 3 3 4/5 5 4 3 4 2 2 3 3 3 3 4/5 5 4 AX, CY AX + word rp, CY rp + word rp, CY rp + rp' AX, CY AX + (saddrp2) rp, CY rp + (saddrp) (saddrp), CY (saddrp) + rp rp, CY rp + sfrp sfrp, CY sfrp + rp (saddrp), CY (saddrp) + word sfrp, CY sfrp + word (saddrp), CY (saddrp) + (saddrp') AX, CY AX - word rp, CY rp - word rp, CY rp - rp' AX, CY AX - (saddrp2) rp, CY rp - (saddrp) (saddrp), CY (saddrp) - rp rp, CY rp - sfrp sfrp, CY sfrp - rp (saddrp), CY (saddrp) - word sfrp, CY sfrp - word (saddrp), CY (saddrp) - (saddrp') AX - word rp - word rp - rp' AX - (saddrp2) rp - (saddrp) (saddrp) - rp rp - sfrp sfrp - rp (saddrp) - word sfrp - word (saddrp) - (saddrp') x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Flags AC P/V CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
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(8) 24-bit operation instructions: ADDG, SUBG
Mnemonic Operands Bytes Operation S ADDG rg, rg' rg, #imm24 WHL, saddrg SUBG rg, rg' rg, #imm24 WHL, saddrg 2 5 3 2 5 3 rg, CY rg + rg' rg, CY rg + #imm24 WHL, CY WHL + (saddrg) rg, CY rg - rg' rg, CY rg - imm24 WHL, CY WHL - (saddrg) x x x x x x Z x x x x x x Flags AC P/V CY x x x x x x V V V V V V x x x x x x
(9) Multiplication instructions: MULU, MULUW, MULW, DIVUW, DIVUX
Mnemonic Operands Bytes Operation S MULU MULUW MULW DIVUW DIVUX r rp rp r rp 2/3 2 2 2/3 2 AX A x r AX (upper half), rp (lower half) AX x rp AX (upper half), rp (lower half) AX x rp AX (quotient), r (remainder) AX / rNote 1 AXDE (quotient), rp (remainder) AXDE / rpNote 2 Z Flags AC P/V CY
Notes 1. When r = 0, r X, AX FFFFH 2. When rp = 0, pr DE, AXDE FFFFFFFFH (10) Special operation instructions: MACW, MACSW, SACW
Mnemonic Operands Bytes Operation S MACW byte 3 AXDE (B) x (C) + AXDE, B B + 2, C C + 2, byte byte - 1 End if(byte = 0 or P/V = 1) MACSW byte 3 AXDE (B) x (C) + AXDE, B B + 2, C C + 2, byte byte - 1 if byte = 0 then End if P/V = 1 then if overflow AXDE 7FFFFFFFH, End if underflow AXDE 80000000H, End AX |(TDE) - (WHL)| + AX, TDE TDE + 2, WHL WHL + 2 C C - 1 End if(C = 0 or CY = 1) x x x V x x Z x Flags AC P/V CY x V x
SACW
[TDE+], [WHL+]
4
x
x
x
V
x
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(11) Increment/decrement instructions: INC, DEC, INCW, DECW, INCG, DECG
Mnemonic Operands Bytes Operation S INC r saddr DEC r saddr INCW rp saddrp DECW rp saddrp INCG DECG rg rg 1/2 2/3 1/2 2/3 2/1 3/4 2/1 3/4 2 2 rr+1 (saddr) (saddr) + 1 r r -1 (saddr) (saddr) - 1 rp rp + 1 (saddrp) (saddrp) + 1 rp rp - 1 (saddrp) (saddrp) - 1 rg rg + 1 rg rg - 1 x x x x Z x x x x Flags AC P/V CY x x x x V V V V
(12) Adjustment instructions: ADJBA, ADJBS, CVTBW
Mnemonic Operands Bytes Operation S ADJBA ADJBS CVTBW 2 2 1 Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract X A, A 00H if A7 = 0 X A, A FFH if A7 = 1 x x Z x x Flags AC P/V CY x x P P x x
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(13) Shift/rotate instructions: ROR, ROL, RORC, ROLC, SHR, SHL, SHRW, SHLW, ROR4, ROL4
Mnemonic Operands Bytes Operation S ROR ROL RORC ROLC SHR SHL SHRW r, n r, n r, n r, n r, n r, n rp, n 2/3 2/3 2/3 2/3 2/3 2/3 2 (CY, (CY,
r7 r0
Flags Z AC P/V CY P P P P x x x x x x x x 0 0 0 P P P x x x x x x x x

r0, rm - 1 r7, rm + 1

rm) rm)
x n times n = 0 - 7 x n times n = 0 - 7
rm)
(CY (CY (CY (CY
r0, r7 r7, r0
CY, CY, 0, 0,
rp15
rm - 1 rm
x n times n = 0 - 7 x n times n = 0 - 7
+1
rm)
r0, r7 r7, r0
rm - 1 rm + 1
rm) rm)
x n times n = 0 - 7 x n times n = 0 - 7
(CY rp0, n=0-7
0, 0,
rpm - 1
rpm) x n times rpm) x n times
SHLW
rp, n
2
(CY rp15, n=0-7
rp0
rpm + 1
0
P
ROR4
mem3
2
A3 - 0 (mem3)3 - 0, (mem3)7 - 4 A3 - 0, (mem3)3 - 0 (mem3)7 - 4 A3 - 0 (mem3)7 - 4, (mem3)3 - 0 A3 - 0, (mem3)7 - 4 (mem3)3 - 0
ROL4
mem3
2
(14) Bit manipulation instructions: MOV1, AND1, OR1, XOR1, NOT1, SET1, CLR1
Mnemonic Operands Bytes Operation S MOV1 CY, saddr.bit CY, sfr.bit CY, X.bit CY, A.bit CY, PSWL.bit CY, PSWH.bit CY, !addr16.bit CY, !!addr24.bit CY, mem2.bit saddr.bit, CY sfr.bit, CY X.bit, CY A.bit, CY PSWL.bit, CY PSWH.bit, CY !addr16.bit, CY !!addr24.bit, CY mem2.bit, CY 3/4 3 2 2 2 2 5 2 2 3/4 3 2 2 2 2 5 6 2 CY (saddr.bit) CY sfr.bit CY X.bit CY A.bit CY PSWL.bit CY PSWH.bit CY !addr16.bit CY !!addr24.bit CY mem2.bit (saddr.bit) CY sfr.bit CY X.bit CY A.bit CY PSWL.bit CY PSWH.bit CY !addr16.bit CY !!addr24.bit CY mem2.bit CY x x x x x Z Flags AC P/V CY x x x x x x x x x
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Mnemonic
Operands
Bytes
Operation S Z
Flags AC P/V CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
AND1
CY, saddr.bit CY, /saddr.bit CY, sfr.bit CY, /sfr.bit CY, X.bit CY, /X.bit CY, A.bit CY, /A.bit CY, PSWL.bit CY, /PSWL.bit CY, PSWH.bit CY, /PSWH.bit CY, !addr16.bit CY, /!addr16.bit CY, !!addr24.bit CY, /!!addr24.bit CY, mem2.bit CY, /mem2.bit
3/4 3/4 3 3 2 2 2 2 2 2 2 2 5 5 2 6 2 2 3/4 3/4 3 3 2 2 2 2 2 2 2 2 5 5 2 6 2 2
OR1
CY, saddr.bit CY, /saddr.bit CY, sfr.bit CY, /sfr.bit CY, X.bit CY, /X.bit CY, A.bit CY, /A.bit CY, PSWL.bit CY, /PSWL.bit CY, PSWH.bit CY, /PSWH.bit CY, !addr16.bit CY, /!addr16.bit CY, !!addr24.bit CY, /!!addr24.bit CY, mem2.bit CY, /mem2.bit
(saddr.bit) CY CY (saddr.bit) CY CY sfr.bit CY CY sfr.bit CY CY X.bit CY CY X.bit CY CY A.bit CY CY A.bit CY CY PSWL.bit CY CY PSWL.bit CY CY PSWH.bit CY CY PSWH.bit CY CY !addr16.bit CY CY !addr16.bit CY CY !!addr24.bit CY CY !!addr24.bit CY CY mem2.bit CY CY mem2.bit CY CY (saddr.bit) CY CY (saddr.bit) CY CY sfr.bit CY CY sfr.bit CY CY X.bit CY CY X.bit CY CY A.bit CY CY A.bit CY CY PSWL.bit CY CY PSWL.bit CY CY PSWH.bit CY CY PSWH.bit CY CY !addr16.bit CY CY !addr16.bit CY CY !!addr24.bit CY CY !!addr24.bit CY CY mem2.bit CY CY mem2.bit
CY CY
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Mnemonic
Operands
Bytes
Operation S Z
Flags AC P/V CY x x x x x x x x x
XOR1
CY, saddr.bit CY, sfr.bit CY, X.bit CY, A.bit CY, PSWL.bit CY, PSWH.bit CY, !addr16.bit CY, !!addr24.bit CY, mem2.bit
3/4 3 2 2 2 2 5 2 2 3/4 3 2 2 2 2 5 2 2 1 2/3 3 2 2 2 2 5 2 2 1 2/3 3 2 2 2 2 5 2 2 1
(saddr.bit) CY CY sfr.bit CY CY X.bit CY CY A.bit CY CY PSWL.bit CY CY PSWH.bit CY CY !addr16.bit CY CY !!addr24.bit CY CY mem2.bit
CY CY (saddr.bit) (saddr.bit) sfr.bit sfr.bit X.bit X.bit A.bit A.bit PSWL.bit PSWL.bit PSWH.bit PSWH.bit !addr16.bit !addr16.bit !!addr24.bit !!addr24.bit mem2.bit mem2.bit CY CY (saddr.bit) 1 sfr.bit 1 X.bit 1 A.bit 1 PSWL.bit 1 PSWH.bit 1 !addr16.bit 1 !!addr24.bit 1 mem2.bit 1 CY 1 (saddr.bit) 0 sfr.bit 0 X.bit 0 A.bit 0 PSWL.bit 0 PSWH.bit 0 !addr16.bit 0 !!addr24.bit 0 mem2.bit 0 CY 0 x x x x x x x x x x x x
NOT1
saddr.bit sfr.bit X.bit A.bit PSWL.bit PSWH.bit !addr16.bit !!addr24.bit mem2.bit CY
x
x
SET1
saddr.bit sfr.bit X.bit A.bit PSWL.bit PSWH.bit !addr16.bit !!addr24.bit mem2.bit CY
x
1
CLR1
saddr.bit sfr.bit X.bit A.bit PSWL.bit PSWH.bit !addr16.bit !!addr24.bit mem2.bit CY
x
0
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(15) Stack manipulation instructions: PUSH, PUSHU, POP, POPU, MOVG, ADDWG, SUBWG, INCG, DECG
Mnemonic Operands Bytes Operation S PUSH PSW sfrp sfr post rg PUSHU POP post PSW sfrp sfr post rg POPU MOVG post SP, #imm24 SP, WHL WHL, SP ADDWG SUBWG INCG DECG SP, #word SP, #word SP SP 1 3 3 2 2 2 1 3 3 2 2 2 5 2 2 4 4 2 2 (SP - 2) PSW, SP SP - 2 (SP - 2) sfrp, SP SP - 2 (SP - 1) sfr, SP SP - 1 {(SP - 2) post, SP SP - 2} x m timesNote (SP - 3) rg, SP SP - 3 {(UUP - 2) post, UUP UUP - 2} x m timesNote PSW (SP), SP SP + 2 sfrp (SP), SP SP + 2 sfr (SP), SP SP + 1 {post (SP), SP SP + 2} x m timesNote rg (SP), SP SP + 3 {post (UUP), UUP UUP + 2} x m timesNote SP imm24 SP WHL WHL SP SP SP + word SP SP - word SP SP + 1 SP SP - 1 R R R R R Z Flags AC P/V CY
Note m = number of registers specified by "post"
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(16) Call/return instructions: CALL, CALLF, CALLT, BRK, BRKCS, RET, RETI, RETB, RETCS, RETCSB
Mnemonic Operands Bytes Operation S CALL !addr16 3 (SP - 3) (PC + 3), SP SP - 3, PCHW 0, PCLW addr16 (SP - 3) (PC + 4), SP SP - 3, PC addr20 (SP - 3) (PC + 2), SP SP - 3, PCHW 0, PCLW rp (SP - 3) (PC + 2), SP SP - 3, PC rg (SP - 3) (PC + 2), SP SP - 3, PCHW 0, PCLW (rp) (SP - 3) (PC + 2), SP SP - 3, PC (rg) (SP - 3) (PC + 3), SP SP - 3, PC PC + 3 + jdisp16 (SP - 3) (PC + 2), SP SP - 3, PC19 - 12 0, PC11 1, PC10 - 0 addr11 CALLT [addr5] 1 (SP - 3) (PC + 1), SP SP - 3, PCHW 0, PCLW (addr5) (SP - 2) PSW, (SP - 1)0 - 3 (PC + 1)HW, (SP - 4) (PC + 1)LW, SP SP - 4 PCHW 0, PCLW (003EH) BRKCS RBn 2 PCLW RP2, RP3 PSW, RBS2 - 0 n, RSS 0, IE 0, RP38 - 11 PCHW, PCHW 0 PC (SP), SP SP + 3 PCLW (SP), PCHW (SP + 3)0 - 3, PSW (SP + 2), SP SP + 4 Clears to 0 flag with highest priority of flags of ISPR that are set (1) PCLW (SP), PCHW (SP + 3)0 - 3, PSW (SP + 2), SP SP + 4 PSW RP3, PCLW RP2, RP2 addr16, PCHW RP38 - 11 Clears to 0 flag with highest priority of flags of ISPR that are set (1) PSW RP3, PCLW RP2, RP2 addr16, PCHW RP38 - 11 R R R R R Z Flags AC P/V CY
!!addr20
4
rp
2
rg
2
[rp]
2
[rg]
2
$!addr20
3
CALLF
!addr11
2
BRK
1
RET RET1
1 1
RETB
1
R
R
R
R
R
RETCS
!addr16
3
R
R
R
R
R
RETCSB
!addr16
4
R
R
R
R
R
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(17) Unconditional branch instruction: BR
Mnemonic Operands Bytes Operation S BR !addr16 !!addr20 rp rg [rp] [rg] $addr20 $!addr20 3 4 2 2 2 2 2 3 PCHW 0, PCLW addr16 PC addr20 PCHW 0, PCLW rp PC rg PCHW 0, PCLW (rp) PC (rg) PC PC + 2 + jdisp8 PC PC + 3 + jdisp16 Z Flags AC P/V CY
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(18) Conditional branch instructions: BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ
Mnemonic Operands Bytes Operation S BNZ BNE BZ BE BNC BNL BC BL BNV BPO BV BPE BP BN BLT BGE BLE BGT BNH BH BF $addr20 $addr20 $addr20 $addr20 $addr20 $addr20 $addr20 $addr20 saddr.bit, $addr20 sfr.bit, $addr20 X.bit, $addr20 A.bit, $addr20 PSWL.bit, $addr20 PSWH.bit, $addr20 !addr16.bit, $addr20 !!addr24.bit, $addr20 mem2.bit, $addr20 2 2 3 3 3 3 3 3 4/5 4 3 3 3 3 6 3 3 PC PC + 2 + jdisp8 if S = 0 PC PC + 2 + jdisp8 if S = 1 $addr20 2 PC PC + 2 + jdisp8 if P/V = 1 $addr20 2 PC PC + 2 + jdisp8 if P/V = 0 $addr20 2 PC PC + 2 + jdisp8 if CY = 1 $addr20 2 PC PC + 2 + jdisp8 if CY = 0 $addr20 2 PC PC + 2 + jdisp8 if Z = 1 $addr20 2 PC PC + 2 + jdisp8 if Z = 0 Z Flags AC P/V CY
S=1 PC PC + 3 + jdisp8 if P/V S = 0 PC PC + 3 + jdisp8 if (P/V S) Z = 1 PC PC + 3 + jdisp8 if (P/V S) Z = 0 PC PC + 3 + jdisp8 if Z CY = 1 PC PC + 3 + jdisp8 if Z CY = 0
PC PC + 3 + jdisp8 if P/V PC PC + 4Note + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if X.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 3 + jdisp8 if PSWL.bit = 0 PC PC + 3 + jdisp8 if PSWH.bit = 0 PC PC + 3 + jdisp8 if !addr16.bit = 0 PC PC + 3 + jdisp8 if !!addr24.bit = 0 PC PC + 3 + jdisp8 if mem2.bit = 0
Note When the number of bytes is 4. When 5, the operation is: PC PC + 5 + jdisp8.
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Mnemonic
Operands
Bytes
Operation S Z
Flags AC P/V CY
BT
saddr.bit, $addr20 sfr.bit, $addr20 X.bit, $addr20 A.bit, $addr20 PSWL.bit, $addr20 PSWH.bit, $addr20 !addr16.bit, $addr20 !!addr24.bit, $addr20 mem2.bit, $addr20
3/4 4 3 3 3 3 6 3 3 4/5
PC PC +
3Note 1
+ jdisp8 if (saddr.bit) = 1
PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if X.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 3 + jdisp8 if PSWL.bit = 1 PC PC + 3 + jdisp8 if PSWH.bit = 1 PC PC + 3 + jdisp8 if !addr16.bit = 1 PC PC + 3 + jdisp8 if !!addr24.bit = 1 PC PC + 3 + jdisp8 if mem2.bit = 1 {PC PC + 4 Note 2 + jdisp8, (saddr.bit) 0} if (saddr.bit) = 1 {PC PC + 4 + jdisp8, sfr.bit 0} if sfr.bit = 1 {PC PC + 3 + jdisp8, X.bit 0} if X.bit = 1 {PC PC + 3 + jdisp8, A.bit 0} if A.bit = 1 {PC PC + 3 + jdisp8, PSWL.bit 0} if PSWL.bit = 1 {PC PC + 3 + jdisp8, PSWH.bit 0} if PSWH.bit = 1 {PC PC + 3 + jdisp8, !addr16.bit 0} if !addr16.bit = 1 {PC PC + 3 + jdisp8, !!addr24.bit 0} if !!addr24.bit = 1 {PC PC + 3 + jdisp8, mem2.bit 0} if mem2.bit = 1 x x x x x
BTCLR
saddr.bit, $addr20
sfr.bit, $addr20 X.bit, $addr20 A.bit, $addr20 PSWL.bit, $addr20
4 3 3 3
PSWH.bit, $addr20
3
!addr16.bit, $addr20
6
!!addr24.bit, $addr20
3
mem2.bit, $addr20
3
Notes 1. When the number of bytes is 3. When 4, the operation is: PC PC + 4 + jdisp8. 2. When the number of bytes is 4. When 5, the operation is: PC PC + 5 + jdisp8.
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Mnemonic
Operands
Bytes
Operation S Z
Flags AC P/V CY
BFSET
saddr.bit, $addr20
4/5
{PC PC + if (saddr.bit) = 0
4Note 2
+ jdisp8, (saddr.bit) 1}
sfr.bit, $addr20 X.bit, $addr20 A.bit, $addr20 PSWL.bit, $addr20
4 3 3 3
{PC PC + 4 + jdisp8, sfr.bit 1} if sfr.bit = 0 {PC PC + 3 + jdisp8, X.bit 1} if X.bit = 0 {PC PC + 3 + jdisp8, A.bit 1} if A.bit = 0 {PC PC + 3 + jdisp8, PSWL.bit 1} if PSWL.bit = 0 {PC PC + 3 + jdisp8, PSWH.bit 1} if PSWH.bit = 0 {PC PC + 3 + jdisp8, !addr16.bit 1} if !addr16.bit = 0 {PC PC + 3 + jdisp8, !!addr24.bit 1} if !!addr24.bit = 0 {PC PC + 3 + jdisp8, mem2.bit 1} if mem2.bit = 0 B B - 1, PC PC + 2 + jdisp8 if B 0 C C - 1, PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, PC PC + 3Note 1 = jdisp8 if (saddr) 0 x x x x x
PSWH.bit, $addr20
3
!addr16.bit, $addr20
6
!!addr24.bit, $addr20
3
mem2.bit, $addr20
3
DBNZ
B, $addr20 C, $addr20 $addr, $addr20
2 2 3/4
Notes 1. When the number of bytes is 3. When 4, the operation is: PC PC + 4 + jdisp8. 2. When the number of bytes is 4. When 5, the operation is: PC PC + 5 + jdisp8. (19) CPU control instructions: MOV, LOCATION, SEL, SWRS, NOP, EI, DI
Mnemonic Operands Bytes Operation S MOV STBC, #byte WDM, #byte LOCATION locaddr 4 4 4 STBC byte WDM byte SFR, internal data area location address upper word specification RSS 0, RBS2 - 0 n RSS 1, RBS2 - 0 n RSS RSS No Operaton IE 1 (Enable interrupt) IE 0 (Disable interrupt) Z Flags AC P/V CY
SEL
RBn RBn, ALT
2 2 2 1 1 1
SWRS NOP EI DI
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(20) String instructions: MOVTBLW, MOVM, XCHM, MOVBK, XCHBK, CMPME, CMPMNE, CMPMC, CMPMNC, CMPBKE, CMPBKNE, CMPBKC, CMPBKNC
Mnemonic Operands Bytes Operation S MOVTBLW !addr8, byte 4 (addr8 + 2) (addr8), byte byte - 1, addr8 addr8 - 2 End if byte = 0 (TDE) A, TDE TDE + 1, C C - 1 End if C = 0 (TDE) A, TDE TDE - 1, C C - 1 End if C = 0 (TDE) A, TDE TDE + 1, C C - 1 End if C = 0 (TDE) A, TDE TDE - 1, C C - 1 End if C = 0 (TDE) (WHL), TDE TDE + 1, WHL WHL + 1, C C - 1 End if C = 0 (TDE) (WHL), TDE TDE - 1, WHL WHL - 1, C C - 1 End if C = 0 (TDE) (WHL), TDE TDE +1, WHL WHL + 1, C C - 1 End if C = 0 (TDE) (WHL), TDE TDE - 1, WHL WHL - 1, C C - 1 End if C = 0 (TDE) - A, TDE TDE + 1, C C - 1 End if C = 0 or Z = 0 (TDE) - A, TDE TDE - 1, C C - 1 End if C = 0 or Z = 0 (TDE) - A, TDE TDE + 1, C C - 1 End if C = 0 or Z = 1 (TDE) - A, TDE TDE - 1, C C - 1 End if C = 0 or Z = 1 (TDE) - A, TDE TDE + 1, C C - 1 End if C = 0 or CY = 0 (TDE) - A, TDE TDE - 1, C C - 1 End if C = 0 or CY = 0 (TDE) - A, TDE TDE + 1, C C - 1 End if C = 0 or CY = 1 (TDE) - A, TDE TDE - 1, C C - 1 End if C = 0 or CY = 1 (TDE) (WHL), TDE TDE + 1, WHL WHL + 1, C C - 1 End if C = 0 or Z = 0 [TDE-], [WHL-] 2 (TDE) (WHL), TDE TDE - 1, WHL WHL - 1, C C - 1 End if C = 0 or Z = 0 (TDE) - (WHL), TDE TDE + 1, WHL WHL + 1, C C - 1 End if C = 0 or Z = 1 (TDE) - (WHL), TDE TDE - 1, WHL WHL - 1, C C - 1 End if C = 0 or Z = 1 (TDE) - (WHL), TDE TDE + 1, WHL WHL + 1, C C - 1 End if C = 0 or CY = 0 (TDE) - (WHL), TDE TDE - 1, WHL WHL - 1, C C - 1 End if C = 0 or CY = 0 (TDE) - (WHL), TDE TDE + 1, WHL WHL + 1, C C - 1 End if C = 0 or CY = 1 (TDE) - (WHL), TDE TDE - 1, WHL WHL - 1, C C - 1 End if C = 0 or CY = 1 x x x x x x x x x x x x x x x x x x x x x V x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x V V V V V V V V V x x x x x x x x x Z Flags AC P/V CY
MOVW
[TDE+], A [TDE-], A
2 2 2 2 2
XCHM
[TDE+], A [TDE-], A
MOVBK
[TDE+], [WHL+]
[TDE-], [WHL-]
2
XCHBK
[TDE+], [WHL+]
2
[TDE-], [WHL-]
2
CMPME
[TDE+], A [TDE-], A
2 2 2 2 2 2 2 2 2
CMPMNE
[TDE+], A [TDE-], A
CMPMC
[TDE+], A [TDE-], A
CMPMNC
[TDE+], A [TDE-], A
CMPBKE
[TDE+], [WHL+]
CMPBKNE
[TDE+], [WHL+]
2
V
[TDE-], [WHL-]
2
V
CMPBKC
[TDE+], [WHL+]
2
V
[TDE-], [WHL-]
2
V
CMPBKNC
[TDE+], [WHL+]
2
V
[TDE-], [WHL-]
2
V
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29.3 Instructions Listed by Type of Addressing (1) 8-bit instructions (combinations expressed by writing A for r are shown in parentheses) MOV, XCH, ADD, ADDC, SUB, SUBC, AND OR XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC Table 29-1. List of Instructions by 8-Bit Addressing
2nd Operand 1st Operand A (MOV) (MOV) MOV XCH (MOV)Note 6 MOV (XCH)Note 6 (XCH) (MOV) (XCH) #byte A r r' saddr saddr' sfr !addr16 !!addr24 mem [saddrp] [%saddrg] MOV XCH ADDNote 1 r3 PSWL PSWH MOV (MOV) (XCH) (ADD)Note 1 RORNote 3 MULU DIVUW INC DEC saddr MOV (MOV)Note 6 MOV MOV ADDNote 1 sfr MOV MOV MOV INC DEC DBNZ PUSH POP [WHL+] [WHL-] n NoneNote 2
ADD Note 1 (XCH)
(ADD)Note 1 (ADD)Note 1 (ADD)Notes 1, 6 (ADD)Note 1 ADDNote 1 r MOV (MOV) MOV XCH MOV XCH MOV XCH ADD Note 1 MOV XCH
ADD Note 1 (XCH)
(ADD)Note 1 ADDNote 1 ADDNote 1
ADD Note 1 (ADD)Note 1 ADDNote 1 XCH
ADD Note 1 (ADD)Note 1 ADDNote 1 !addr16 !!addr24 mem [saddrp] [%saddrg] mem3 MOV (MOV) ADDNote 1 MOV ADDNote 1 MOV
ROR4 ROL4
r3 PSWL PSWH B, C STBC, WDM [TDE+] [TDE-]
MOV
MOV
DBNZ MOV (MOV) (ADD)
Note 1
MOVBKNote 5
MOVMNote 4
Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD. 2. There is no 2nd operand, or the 2nd operand is not an operand address. 3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR. 4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM. 5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK. 6. If saddr is saddr2 in this combination, there is a short code length instruction.
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(2) 16-bit instructions (combinations expressed by writing AX for rp are shown in parentheses) MOVM, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 29-2. List of Instructions by 16-Bit Addressing
2nd Operand 1st Operand AX (MOVW) ADDW
Note 1
#word
AX
rp rp'
saddrp saddrp'
sfrp
!addr16 !!addr24
mem [saddrp] [%saddrg]
[WHL+]
byte
n
None Note 2
(MOVW) (XCHW)
(MOVW) (XCHW)
(MOVW)Note 3 MOVW (XCHW) Note 3 (XCHW)
(MOVW) XCHW
MOVW XCHW
(MOVW) (XCHW)
(ADD)Note 1 (ADDW)Note 1 (ADDW)Notes 1,3 (ADDW)Note 1 rp MOVW ADDWNote 1 (MOVW) (XCHW) MOVW XCHW MOVW XCHW MOVW XCHW MOVW SHRW SHLW MULWNote 4 INCW DECW INCW DECW
(ADDW)Note 1 ADDWNote 1 ADDWNote 1 ADDWNote 1 saddrp MOVW (MOVW)
Note 3
MOVW
MOVW ADDWNote 1
ADDWNote 1 (ADDW)Note 1 ADDWNote 1 XCHW
sfrp
MOVW
MOVW
MOVW
PUSH POP MOVTBLW
ADDWNote 1 (ADDW)Note 1 ADDWNote 1 !addr16 !!addr24 mem [saddrp] [%saddrg] PSW MOVW MOVW (MOVW) MOVW
PUSH POP
SP
ADDWG SUBWG
post
PUSH POP PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes 1. SUBW and CMPW are the same as ADDW. 2. There is no 2nd operand, or the 2nd operand is not an operand address. 3. If saddrp is saddrp2 in this combination, there is a short code length instruction. 4. MULUW and DIVUX are the same as MULW.
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(3) 24-bit instructions (combinations expressed by writing WHL for rg are shown in parentheses) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 29-3. List of Instructions by 24-Bit Addressing
2nd Operand 1st Operand WHL (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG (MOVG) MOVG MOVG MOVG #imm24 WHL rg rg' saddrg !!addr24 mem1 [%saddrg] SP NoneNote
rg
MOVG
INCG DECG PUSH POP
saddrg !!addr24 mem1 [%saddrg] SP MOVG
(MOVG) (MOVG) MOVG MOVG MOVG
MOVG MOVG
INCG DECG
Note There is no 2nd operand, or the 2nd operand is not an operand address. (4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 29-4. List of Instructions by Bit Manipulation Instruction Addressing
2nd Operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 AND1 OR1 XOR1 MOV1 /saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 SET1 NoneNote
1st Operand CY
NOT1 SET1 CLR1
saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit
NOT1 SET1 CLR1 BF BT BTCLR BFSET
Note There is no 2nd operand, or the 2nd operand is not an operand address.
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(5) Call/return instructions/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 29-5. List of Instructions by Call/Return Instruction/Branch Instruction Addressing
Instruction Address Operand Basic instructions BCNote BR CALL BR CALL BR RETCS RETCSB Compound instructions BF BT BTCLR BFSET DBNZ CALL BR CALL BR CALL BR CALL BR CALL BR CALLF CALLT BRKCS BRK RET RETI RETB $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None
Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
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The following development tools are available for the development of systems that employ the PD784938 Subseries. Figure A-1 shows the development tool configuration. * Support of PC98-NX Series Unless otherwise specified, products that operate in IBM PC/ATTM or compatibles can operate in the PC98-NX Series. When using PC98-NX Series, refer to the descriptions for IBM PC/AT or compatibles. * Windows Unless otherwise specified, "Windows" refers the following OSs. * Windows 3.1 * Windows 95 * Windows NT Ver.4.0
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Figure A-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K4-NS
Language processing Software * * * * Assembler package C compiler package C library source file Device file
Debugging tools * System simulator * Integrated debugger * Device file
Software for embedding * Real-time OS * OS
Host machine (PC) Interface adapter, PC card interface, etc.
Flash memory programming environment Flash programmer
In-circuit emulator Emulation board Power supply unit
Flash memory writing adapter
On-chip flash memory version
Emulation probe
Conversion socket Target system
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Figure A-1. Development Tool Configuration (2/2) (2) When using in-circuit emulator IE-784000-R
Language processing software * * * * Assembler package C compiler package C library source file Device file
Debugging tools * System simulator * Integrated debugger * Device file
Software for embedding * Real-time OS * OS
Host machine (PC or EWS)
Interface board
Flash memory programming environment Flash programmer
In-circuit emulator Interface adapter Emulation board
Flash memory writing adapter
I/O emulation board Probe board
On-chip flash memory version
Emulation probe conversion board
Emulation probe
Conversion socket Target system
Remark Items in broken line boxes differ according to the development environment. Refer to A.3.1 Hardware.
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A.1 Language Processing Software
RA78K4 Assembler package This assembler converts programs written in mnemonics into an object codes executable with a microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with an optional device file (DF784937). This assembler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) on Windows. Part Number: SxxxxRA78K4 CC78K4 C compiler package This compiler converts programs written in C language into object codes executable with a microcontroller. This compiler should be used in combination with an optional assembler package (RA78K4) and device file (DF784937). This C compiler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) on Windows. Part Number: SxxxxCC78K4 DF784937Note This file contains information peculiar to the device. This device file should be used in combination with an optional tool (RA78K4, CC78K4, SM78K4, ID78K4-NS, and ID78K4). Corresponding OS and host machine differ depending on the tool to be used with. Part Number: Sxxxx784937 CC78K4-L C library source file This is a source file of functions configuring the object library included in the C compiler package. This file is required to match the object library included in C compiler package to the customer's specifications. Operating environment for the source file is not dependent on the OS. Part Number: SxxxxCC78K4-L
Note The DF784937 can be used in common with the RA78K4, CC78K4, SM78K4, ID78K4-NS, and ID78K4.
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Remark xxxx in the part number differs depending on the host machine and OS used.
SxxxxRA78K4 SxxxxCC78K4 SxxxxDF784937 SxxxxCC78K4-L
xxxx AA13 AB13 BB13 3P16 3K13 3K15 3R13 NEWSTM (RISC) HP9000 Series 700TM Host Machine PC-9800 Series IBM PC/AT or compatibles OS Windows (Japanese Windows (Japanese Windows (English version)Note version)Note Supply Medium 3.5-inch 2HD FD 3.5-inch 2HC FD
version)Note DAT (DDS) HP-UX 3.5-inch 2HC FD 1/4-inch CGMT 3.5-inch 2HC FD
HP-UX (Rel. 10.10) SunOS (Rel. 4.1.4) Solaris (Rel. 2.5.1) NEWS-OS (Rel. 6.1)
SPARCstationTM
Note Can be operated in DOS environment. A.2 Flash Memory Programming Tools
Flashpro II (part number FL-PR2) Flashpro III (part number FL-PR3, PG-FP3) Flash programmer FA-100GFNote Flash memory writing adapter Flash programmer dedicated to microcontrollers with on-chip flash memory.
Flash memory writing adapter used connected to the Flashpro II, Flashpro III. * FA-100GF: For 100-pin plastic QFP (GF-3BA type)
Note Under development Remark FL-PR2, FL-PR3, and FA-100GF are products of Naito Densei Machida Mfg. Co., Ltd. Phone: +81-44-822-3813 Naito Densei Machida Mfg. Co., Ltd.
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A.3 Debugging Tools A.3.1 Hardware (1/2) (1) When using the in-circuit emulator IE-78K4-NS
IE-78K4-NS In-circuit emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K/IV Series product. It corresponds to integrated debugger (ID78K4-NS). This emulator should be used in combination with power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. This adapter is used for supplying power from a receptacle of 100-V to 200-V AC.
IE-70000-MC-PS-B Power supply unit IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-C PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF Interface adapter IE-784937-NS-EM1Note Emulation board NP-100GF Emulation probe EV-9200GF-100 Conversion socket (Refer to Figures A-2 and A-3)
This adapter is required when using the PC-9800 Series computer (except notebook type) as the IE-78K4-NS host machine (C bus supported). This is PC card and interface cable required when using the PC-9800 Series notebooktype computer as the IE-78K4-NS host machine (PCMCIA socket supported). This adapter is required when using the IBM PC/AT or compatibles as the IE-78K4-NS host machine (ISA bus supported). This adapter is required when connecting a personal computer that includes a PCI bus as the IE-78K4-NS host machine. This board is used to emulate the operations of the peripheral hardware peculiar to a device. It should be used in combination with an in-circuit emulator. This probe is used to connect the in-circuit emulator to the target system and is designed for 100-pin plastic QFP (GF-3BA type). This conversion socket connects the NP-100GF to the target system board designed to mount a 100-pin plastic QFP (GF-3BA type).
Note Under development Remarks 1. NP-100GF is a product of Naito Densei Machida Mfg. Co., Ltd. Phone: +81-44-822-3813 Naito Densei Machida Mfg. Co., Ltd. 2. EV-9200GF-100 is sold in units of five.
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A.3.1 Hardware (2/2) (2) When using the in-circuit emulator IE-784000-R
IE-784000-R In-circuit emulator The IE-784000-R is an in-circuit emulator that can be used in all members of the 78K/IV Series. Use in combination with the separately purchased IE-784000-R-EM and IE-784937-NSEM1. For debugging, connect to the host machine. Using in combination with the mandatory, separately purchased, integrated debugger (ID78K4) and device file, allows debugging on the source program level in C language and structured assembly language. The C0 coverage function provides efficient debugging and program inspection. Connecting with the host machine by either EthernetTM or a dedicated bus requires a separately purchased interface adapter. This adapter is required when using the PC-9800 Series computer (except notebook type) as the IE-784000-R host machine (C bus supported). This adapter is required when using the IBM PC/AT or compatibles as the IE-784000-R host machine (ISA bus supported). This is adapter and cable required when using an EWS computer as the IE-784000-R host machine, and is used connected to the board in the IE-784000-R. 10Base-5 is supported for Ethernet, but a commercially available conversion adapter is required for other formats. The emulation board that is used with all units in the 78K/IV Series.
IE-70000-98-IF-C Interface adapter IE-70000-PC-IF-C Interface adapter IE-78000-R-SV3 Interface adapter
IE-784000-R-EM Emulation board IE-784937-NS-EM1Note or IE-784937-SL-EM1 Emulation board IE-78K4-R-EX3Note Emulation probe conversion board EP-78064GF-R Emulation probe EV-9200GF-100 Conversion socket (Refer to Figures A-2 and A-3)
Board for emulating peripheral hardware that is inherent to a device.
100-pin conversion board required when using the IE-784937-NS-EM1 on the IE-784000-R.
This probe is used to connect the in-circuit emulator to the target system and is designed for 100-pin plastic QFP (GF-3BA type). This conversion socket connects the EP-78064GF-R to the target system board designed to mount a 100-pin plastic QFP (GF-3BA type).
Note Under development Remark EV-9200GF-100 is sold in units of five.
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A.3.2 Software (1/2)
SM78K4 System simulator This system simulator is used to perform debugging at C source level or assembler level while simulating the operation of the target system on a host machine. This simulator runs on Windows. Use of the SM78K4 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency and software quality. The SM78K4 should be used in combination with the optional device file (DF784937). Part Number: SxxxxSM78K4
Remark xxxx in the part number differs depending on the host machine and OS used.
SxxxxSM78K4
xxxx AA13 AB13 BB13 Host Machine PC-9800 Series IBM PC/AT or compatibles OS Windows (Japanese version) Windows (Japanese version) Windows (English version) Supply Medium 3.5-inch 2HD FD 3.5-inch 2HC FD
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A.3.2 Software (2/2)
ID78K4-NSNote Integrated debugger (supporting in-circuit emulator IE-78K4-NS) This debugger is a control program to debug 78K/IV Series microcontrollers. It adopts a graphical user interface, which is equivalent visually and operationally to Windows or OSF/MotifTM. It also has an enhanced debugging function for C language programs, and thus trace results can be displayed on screen in C-language level by using the windows integration function which links a trace result with its source program, disassembled display, and memory display. In addition, by incorporating function modules such as task debugger and system performance analyzer, the efficiency of debugging programs, which run on real-time OSs can be improved. It should be used in combination with the optional device file (DF784937). Part Number: SxxxxID78K4-NS, SxxxxID78K4
ID78K4 Integrated debugger (supporting in-circuit emulator IE-784000-R)
Note Under development Remark xxxx in the part number differs depending on the host machine and OS used.
SxxxxID78K4-NS
xxxx AA13 AB13 BB13 Host Machine PC-9800 Series IBM PC/AT or compatibles OS Windows (Japanese version) Windows (Japanese version) Windows (English version) Supply Medium 3.5-inch 2HD FD 3.5-inch 2HC FD
SxxxxID78K4
xxxx AA13 AB13 BB13 3P16 3K13 3K15 3R13 NEWS (RISC) HP9000 Series 700 SPARCstation Host Machine PC-9800 Series IBM PC/AT or compatibles OS Windows (Japanese version) Windows (Japanese version) Windows (English version) HP-UX (Rel. 10.10) SunOS (Rel. 4.1.4) Solaris (Rel. 2.5.1) NEWS-OS (Rel. 6.1) DAT (DDS) 3.5-inch 2HC FD 1/4 inch CGMT 3.5-inch 2HC FD Supply Medium 3.5-inch 2HD FD 3.5-inch 2HC FD
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A.4 Drawings of Conversion Socket (EV-9200GF-100) and Recommended Board Mounting Pattern Mount the EP-78064GF-R in combination on the board. Figure A-2. Package Drawing of EV-9200GF-100 (reference) (unit: mm)
A B F M N
E
O
R D C S
K
EV-9200GF-100
1
No.1 pin index
P
G H I EV-9200GF-100-G0E ITEM A B C D E F G H I J K L M N O P Q R S MILLIMETERS 24.6 21 15 18.6 4-C 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 INCHES 0.969 0.827 0.591 0.732 4-C 0.079 0.031 0.472 0.89 0.996 0.236 0.654 0.76 0.323 0.315 0.098 0.079 0.014
2.3 1.5
0.091 0.059
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L
J
APPENDIX A
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Figure A-3. Recommended Board Mounting Pattern of EV-9200GF-100 (reference) (unit: mm) G
J K
D H F E
L
I
C B A EV-9200GF-100-P1E ITEM A B C D E F G H I J K L Caution MILLIMETERS 26.3 21.6 INCHES 1.035 0.85
+0.001 +0.002 0.650.02 x 29=18.850.05 0.026-0.002 x 1.142=0.742-0.002 +0.001 +0.003 0.650.02 x 19=12.350.05 0.026-0.002 x 0.748=0.486-0.002
15.6 20.3 12 0.05 6 0.05 0.35 0.02
0.614 0.799
+0.003 0.472-0.002 +0.003 0.236-0.002 +0.001 0.014-0.001 +0.001 0.093-0.002
2.36 0.03 2.3 1.57 0.03
0.091
+0.001 0.062-0.002
Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
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A.5 Check Sheet for PD784938 Subseries Development Tools The following development tools are necessary for using the PD784938 Subseries products. Check if the necessary tools are at hand (the dotted line in the table below indicates either of the tools above or below the line should be selected). * Host machine: PC-9800 Series
Order Code IE-784000-R IE-784000-R-EM IE-784937-R-EM1 IE-784937-NS-EM1 IE-70000-98-IF-B (other than notebook type personal computer), IE-70000-98-IF-C IE-70000-98N-IF (for notebook type personal computer) IE-78000R-SV3 IE-78K4-R-EX3 EP-78064GF-R EV-9200GF-100 FA-100GF (necessary for using flash memory version) Check Remark
SAA13ID78K4 (3.5") S5A13DF784937 (3.5") S5A10DF784937 (5") S5A13RA78K4 (3.5") S5A10RA78K4 (5") S5A13CC78K4 (3.5")Note 1 S5A10CC78K4 (5")Note 1 S5A13CC78K4-L (3.5")Note 2 S5A10CC78K4-L (5")Note 2
Notes 1. Necessary for using the C compiler. 2. Necessary for remodelling the library of the C compiler.
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APPENDIX A
DEVELOPMENT TOOLS
* Host machine: IBM PC/AT
Order Code IE-784000-R IE-784000-R-EM IE-784937-R-EM1 IE-784937-NS-EM1 IE-70000-PC-IF-B, IE-70000-PC-IF-C IE-78000R-SV3 IE-78K4-R-EX3 EP-78064GF-R EV-9200GF-100 FA-100GF (necessary for using flash memory version) Check Remark
SBB13ID78K4 (3.5") (English version) SAB13ID78K4 (3.5") (Japanese version) S5A13DF784937 (3.5") S5A10DF784937 (5") S5A13RA78K4 (3.5") S5A10RA78K4 (5") S5A13CC78K4 (3.5")Note 1 S5A10CC78K4 (5")Note 1 S5A13CC78K4-L (3.5")Note 2 S5A10CC78K4-L (5")Note 2
Notes 1. Necessary for using the C compiler. 2. Necessary for remodelling the library of the C compiler.
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APPENDIX B
EMBEDDED SOFTWARE
The following embedded software products are available for efficient program development and maintenance of the
PD784938 Subseries.
Real-Time OS (1/2)
RX78K/IV Real-time OS RX78K/IV is a real-time OS conforming to the ITRON specifications. Tool (configurator) for generating nucleus of RX78K/IV and plural information tables is supplied. Used in combination with an optional assembler package (RA78K4) and device file (DF784937). The real-time OS is a DOS-based application. It should be used in the DOS Prompt when using in Windows. Part number: SxxxxRX78K4
Caution When purchasing the RX78K/IV, fill in the purchase application form in advance and sign the User Agreement. Remark xxxx and in the part number differ depending on the host machine and OS used.
SxxxxRX78K4-
001 100K 001M 010M S01 Source program Product Outline Evaluation object Mass-production object Maximum Number for Use in Mass Production Do not use for mass-produced product. 0.1 million units 1 million units 10 million units Source program for mass-produced object
xxxx AA13 AB13 BB13 3P16 3K13 3K15 3R13
Host Machine PC-9800 Series IBM PC/AT or compatibles
OS Windows (Japanese version)Note
Supply Medium 3.5-inch 2HD FD 3.5-inch 2HC FD
Windows (Japanese version)Note Windows (English version)Note
HP9000 Series 700 SPARCstation
HP-UX (Rel. 10.10) SunOS (Rel. 4.1.4) Solaris (Rel. 2.5.1)
DAT (DDS) 3.5-inch 2HC FD 1/4-inch CGMT 3.5-inch 2HC FD
NEWS (RISC)
NEWS-OS (Rel. 6.1)
Note
Can also be operated in DOS environment.
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EMBEDDED SOFTWARE
Real-Time OS (2/2)
MX78K4 OS MX78K4 is an OS for ITRON specification subsets. A nucleus for the MX78K4 is also included as a companion product. This manages tasks, events, and time. In the task management, determining the task execution order and switching from task to the next task are performed. The MX78K4 is a DOS-based application. It should be used in the DOS Prompt when using in Windows. Part number: SxxxxMX78K4-
Remark xxxx and in the part number differ depending on the host machine and OS used.
SxxxxMX78K4-
001 xx S01 Product Outline Evaluation object Mass-production object Source program Maximum Number for Use in Mass Production Use in preproduction stages. Use in mass production stages. Only the users who purchased mass-production objects are allowed to purchase this program.
xxxx AA13 AB13 BB13 3P16 3K13 3K15 3R13
Host Machine PC-9800 Series IBM PC/AT or compatibles
OS Windows (Japanese version)Note Windows (Japanese version)Note Windows (English version)Note
Supply Medium 3.5-inch 2HD FD 3.5-inch 2HC FD
HP9000 Series 700 SPARCstation
HP-UX (Rel. 10.10) SunOS (Rel. 4.1.4) Solaris (Rel. 2.5.1)
DAT (DDS) 3.5-inch 2HC FD 1/4-inch CGMT 3.5-inch 2HC FD
NEWS (RISC)
NEWS-OS (Rel. 6.1)
Note
Can also be operated in DOS environment.
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APPENDIX C REGISTER INDEX
C.1 Register Name Index [A] A/D conversion result register (ADCR) ... 406 A/D converter mode register (ADM) ... 407 A/D current cut select register (IEAD) ... 410 Asynchronous serial interface mode register (ASIM) ... 428, 433 Asynchronous serial interface mode register 2 (ASIM2) ... 428, 433 Asynchronous serial interface status register (ASIS) ... 434 Asynchronous serial interface status register 2 (ASIS2) ... 434 [B] Baud rate generator control register (BRGC) ... 451 Baud rate generator control register 2 (BRGC2) ... 451 Bus control register (BCR) ... 484 [C] Capture/compare control register 0 (CRC0) ... 223 Capture/compare control register 1 (CRC1) ... 279 Capture/compare control register 2 (CRC2) ... 314 Capture/compare register (CR11/CR11W, CR21/CR21W) ... 275, 310 Capture register (CR02, CR12/CR12W, CR22/CR22W) ... 220, 275, 310 Clock output mode register (CLOM) ... 513 Clocked serial interface mode register (CSIM) ... 459 Clocked serial interface mode register 1 (CSIM1) ... 428, 443 Clocked serial interface mode register 2 (CSIM2) ... 428, 443 Clocked serial interface mode register 3 (CSIM3) ... 459 Communication count register (CCR) ... 499 Compare register (CR00, CR01, CR10/CR10W, CR20/CR20W, CR30/CR30W) ... 220, 275, 310, 375 Control data register (CDR) ... 487 [D] Data register (DR) ... 491 [E] External interrupt mode register 0 (INTM0) ... 518 External interrupt mode register 1 (INTM1) ... 519 [H] Hold mode register (HLDM) ... 634 [I] In-service priority register (ISPR) ... 540 Internal memory size switching register (IMS) ... 82 Interrupt control register ... 533
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APPENDIX C
REGISTER INDEX
Interrupt mask register (MK0H, MK0L, MK1H, MK1L) ... 538 Interrupt mode control register (IMC) ... 541 Interrupt status register (ISR) ... 494 [M] Macro service mode register ... 567 Memory expansion mode register (MM) ... 603, 615 [O] One-shot pulse output control register (OSPC) ... 225 Oscillation stabilization time specification register (OSTS) ... 109, 641 [P] Partner address register (PAR) ... 486 Port 0 (P0) ... 119 Port 0 buffer register (P0L, P0H) ... 204 Port 0 mode register (PM0) ... 120 Port 1 (P1) ... 126 Port 1 mode control register (PMC1) ... 131 Port 1 mode register (PM1) ... 131 Port 2 (P2) ... 137 Port 3 (P3) ... 143 Port 3 mode control register (PMC3) ... 149 Port 3 mode register (PM3) ... 148 Port 4 (P4) ... 155 Port 4 mode register (PM4) ... 156 Port 5 (P5) ... 162 Port 5 mode register (PM5) ... 163 Port 6 (P6) ... 169 Port 6 mode register (PM6) ... 175 Port 7 (P7) ... 179 Port 7 mode register (PM7) ... 180 Port 9 (P9) ... 183 Port 9 mode register (PM9) ... 184 Port 10 (P10) ... 188 Port 10 mode control register (PMC10) ... 193 Port 10 mode register (PM10) ... 193 Prescaler mode register 0 (PRM0) ... 222, 377 Prescaler mode register 1 (PRM1) ... 278, 313 Program status word (PSWL) ... 543 Programmable wait control register 1 (PWC1) ... 616 Programmable wait control register 2 (PWC2) ... 617 Pull-up resistor option register H (PUOH) ... 187, 197 Pull-up resistor option register L (PUOL) ... 123, 135, 141, 153, 159, 166, 178 PWM control register (PWMC) ... 397 PWM modulo register 0 (PWM0) ... 398 PWM modulo register 1 (PWM1) ... 398 PWM prescaler register (PWPR) ... 398
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APPENDIX C
REGISTER INDEX
[R] Real-time output port control register (RTPC) ... 203 Refresh area specification register (RFA) ... 630 Refresh mode register (RFM) ... 629 ROM correction adress register H (CORAH) ... 667 ROM correction adress register L (CORAL) ... 667 ROM correction control register (CORC) ... 667 [S] Sampling clock selection register (SCS0) ... 520 Serial receive buffer (RXB) ... 431 Serial receive buffer 2 (RXB2) ... 431 Serial shift register (SIO) ... 458 Serial shift register 1 (SIO1) ... 442 Serial shift register 2 (SIO2) ... 442 Serial shift register 3 (SIO3) ... 457 Serial transmit shift register (TXS) ... 431 Serial transmit shift register 2 (TXS2) ... 431 Slave address register (SAR) ... 486 Slave status register (SSR) ... 498 Standby control register (STBC) ... 108, 639 Success count register (SCR) ... 499 [T] Telegraph length register (DLR) ... 490 Timer control register 0 (TMC0) ... 221, 376 Timer control register 1 (TMC1) ... 277, 312 Timer output control register (TOC) ... 224, 315 Timer counter 0 (TM0) ... 220 Timer counter 1 (TM1/TM1W) ... 275 Timer counter 2 (TM2/TM2W) ... 310 Timer counter 3 (TM3/TM3W) ... 375 [U] Unit address register (UAR) ... 486 Unit status register (USR) ... 492 [W] Watch timer mode register (WM) ... 393 Watchdog timer mode register (WDM) ... 389, 542
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APPENDIX C
REGISTER INDEX
C.2 Register Symbol Index [A] ADCR ADIC ADM ASIM ASIM2 ASIS ASIS2 [B] BCR BRGC BRGC2 [C] CCR CDR CIC00 CIC01 CIC10 CIC11 CIC20 CIC21 CIC30 CLOM CORAH CORAL CORC CR00 CR01 CR02 CR10/CR10W CR11/CR11W CR12/CR12W CR20/CR20W CR21/CR21W CR22/CR22W CR30/CR30W CRC0 CRC1 CRC2 CSIIC CSIIC1 CSIIC2 CSIIC3 CSIM : Communication Count Register ... 499 : Control Data Register ... 486 : Interrupt Control Register ... 534 : Interrupt Control Register ... 534 : Interrupt Control Register ... 534 : Interrupt Control Register ... 534 : Interrupt Control Register ... 535 : Interrupt Control Register ... 535 : Interrupt Control Register ... 535 : Clock Output Mode Register ... 513 : ROM Correction Address Register H ... 667 : ROM Correction Address Register L ... 667 : ROM Correction Control Register ... 667 : Compare Register ... 220 : Compare Register ... 220 : Capture Register ... 220 : Compare Register ... 275 : Capture/Compare Register ... 275 : Capture Register ... 275 : Compare Register ... 310 : Capture/Compare Register ... 310 : Capture Register ... 310 : Compare Register ... 375 : Capture/Compare Control Register 0 ... 223 : Capture/Compare Control Register 1 ... 279 : Capture/Compare Control Register 2 ... 314 : Interrupt Control Register ... 536 : Interrupt Control Register ... 536 : Interrupt Control Register ... 536 : Interrupt Control Register ... 537 : Clocked Serial Interface Mode Register ... 459 : Bus Control Register ... 484 : Baud Rate Generator Control Register ... 451 : Baud Rate Generator Control Register 2 ... 451 : A/D Conversion Result Register ... 406 : Interrupt Control Register ... 535 : A/D Converter Mode Register ... 407 : Asynchronous Serial Interface Mode Register ... 428, 433 : Asynchronous Serial Interface Mode Register 2 ... 428, 433 : Asynchronous Serial Interface Status Register ... 434 : Asynchronous Serial Interface Status Register 2 ... 434
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APPENDIX C
REGISTER INDEX
CSIM1 CSIM2 CSIM3 [D] DLR DR [H] HLDM [I] IEAD IEIC1 IEIC2 IMC IMS INTM0 INTM1 ISPR ISR [M] MK0H MK0L MK1H MK1L MM [O] OSPC OSTS [P] P0 P0H P0L P1 P2 P3 P4 P5 P6 P7 P9 P10 PAR PIC0
: Clocked Serial Interface Mode Register 1 ... 428, 443 : Clocked Serial Interface Mode Register 2 ... 428, 443 : Clocked Serial Interface Mode Register 3 ... 459
: Telegraph Length Register ... 490 : Data Register ... 491
: Hold Mode Register ... 634
: A/D Current Cut Select Register ... 410 : Interrupt Control Register ... 537 : Interrupt Control Register ... 537 : Interrupt Mode Control Register ... 541 : Internal Memory Size Switching Register ... 82 : External Interrupt Mode Register 0 ... 518 : External Interrupt Mode Register 1 ... 519 : In-Service Priority Register ... 540 : Interrupt Status Register ... 494
: Interrupt Mask Register H ... 538 : Interrupt Mask Register L ... 538 : Interrupt Mask Register 1H ... 538 : Interrupt Mask Register 1L ... 538 : Memory Expansion Mode Register ... 603, 615
: One-Shot Pulse Output Control Register ... 225 : Oscillation Stabilization Time Specification Register ... 109, 641
: Port 0 ... 119 : Port 0 Buffer Register H ... 204 : Port 0 Buffer Register L ... 204 : Port 1 ... 126 : Port 2 ... 137 : Port 3 ... 143 : Port 4 ... 155 : Port 5 ... 162 : Port 6 ... 169 : Port 7 ... 179 : Port 9 ... 183 : Port 10 ... 188 : Partner Address Register ... 486 : Interrupt Control Register ... 534
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APPENDIX C
REGISTER INDEX
PIC1 PIC2 PIC3 PIC4 PIC5 PM0 PM1 PM3 PM4 PM5 PM6 PM7 PM9 PM10 PMC1 PMC3 PMC10 PRM0 PRM1 PSWL PUOH PUOL PWC1 PWC2 PWM0 PWM1 PWMC PWPR [R] RFA RFM RTPC RXB RXB2 [S] SAR SCR SCS0 SERIC SERIC2 SIO SIO1 SIO2 SIO3 SRIC SRIC2
: Interrupt Control Register ... 534 : Interrupt Control Register ... 534 : Interrupt Control Register ... 534 : Interrupt Control Register ... 535 : Interrupt Control Register ... 535 : Port 0 Mode Register ... 120 : Port 1 Mode Register ... 131 : Port 3 Mode Register ... 148 : Port 4 Mode Register ... 156 : Port 5 Mode Register ... 163 : Port 6 Mode Register ... 175 : Port 7 Mode Register ... 180 : Port 9 Mode Register ... 184 : Port 10 Mode Register ... 193 : Port 1 Mode Control Register ... 131 : Port 3 Mode Control Register ... 149 : Port 10 Mode Control Register ... 193 : Prescaler Mode Register 0 ... 222, 377 : Prescaler Mode Register 1 ... 278, 313 : Program Status Word ... 543 : Pull-Up Resistor Option Register H ... 187, 197 : Pull-Up Resistor Option Register L ... 123, 135, 141, 153, 159, 166, 178 : Programmable Wait Control Register 1 ... 616 : Programmable Wait Control Register 2 ... 617 : PWM Modulo Register 0 ... 398 : PWM Modulo Register 1 ... 398 : PWM Control Register ... 397 : PWM Prescaler Register ... 398
: Refresh Area Specification Register ... 630 : Refresh Mode Register ... 629 : Real-Time Output Port Control Register ... 203 : Serial Receive Buffer ... 431 : Serial Receive Buffer 2 ... 431
: Slave Address Register ... 486 : Success Count Register ... 499 : Sampling Clock Selection Register ... 520 : Interrupt Control Register ... 535 : Interrupt Control Register ... 536 : Serial Shift Register ... 458 : Serial Shift Register 1 ... 442 : Serial Shift Register 2 ... 442 : Serial Shift Register 3 ... 457 : Interrupt Control Register ... 535 : Interrupt Control Register ... 536
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APPENDIX C
REGISTER INDEX
SSR STBC STIC STIC2 [T] TM0 TM1/TM1W TM2/TM2W TM3/TM3W TMC0 TMC1 TOC TXS TXS2 [U] UAR USR [W] WDM WIC WM
: Slave Status Register ... 498 : Standby Control Register ... 108, 639 : Interrupt Control Register ... 536 : Interrupt Control Register ... 536
: Timer Counter 0 ... 220 : Timer Counter 1 ... 275 : Timer Counter 2 ... 310 : Timer Counter 3 ... 375 : Timer Control Register 0 ... 221, 376 : Timer Control Register 1 ... 277, 312 : Timer Output Control Register ... 224, 315 : Serial Transmit Shift Register ... 431 : Serial Transmit Shift Register 2 ... 431
: Unit Address Register ... 486 : Unit Status Register ... 492
: Watchdog Timer Mode Register ... 389, 542 : Interrupt Control Register ... 537 : Watch Timer Mode Register ... 393
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